Jose
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534cb00c42
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fixed: uart module and simulation-only signals handling
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2026-03-07 21:53:09 +01:00 |
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Jose
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d7e166ca6f
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refactor: renamed top.v to riscv.v
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2026-03-03 04:05:49 +01:00 |
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Jose
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a4b158d6a8
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add: uart_tx module
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2026-03-03 03:41:56 +01:00 |
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Jose
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a890b031a7
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add: dual port imem and uart
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2026-03-03 01:44:27 +01:00 |
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Jose
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98f948ab18
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refactor: renamed all signals for consistency
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2026-03-02 23:34:31 +01:00 |
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Jose
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e7cd451e7e
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prototype works
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2026-03-02 23:20:54 +01:00 |
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Jose
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8f2b31259c
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Initial commit
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2026-02-20 11:33:05 +01:00 |
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Jose
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fcdfb29c39
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Initial commit
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2026-02-20 11:32:16 +01:00 |
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