Gallardo7761/riscv-ac
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  • 534cb00c42 fixed: uart module and simulation-only signals handling main Jose 2026-03-07 21:53:09 +01:00
  • d7e166ca6f refactor: renamed top.v to riscv.v Jose 2026-03-03 04:05:49 +01:00
  • a4b158d6a8 add: uart_tx module Jose 2026-03-03 03:41:56 +01:00
  • a890b031a7 add: dual port imem and uart Jose 2026-03-03 01:44:27 +01:00
  • 98f948ab18 refactor: renamed all signals for consistency Jose 2026-03-02 23:34:31 +01:00
  • e7cd451e7e prototype works Jose 2026-03-02 23:20:54 +01:00
  • 8f2b31259c Initial commit Jose 2026-02-20 11:33:05 +01:00
  • fcdfb29c39 Initial commit Jose 2026-02-20 11:32:16 +01:00