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fixed: uart module and simulation-only signals handling

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This commit is contained in:
Jose
2026-03-07 21:53:09 +01:00
parent d7e166ca6f
commit 534cb00c42
35 changed files with 24 additions and 143 deletions
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2
riscv-ac.sim/sim_1/behav/xsim/compile.sh
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@@ -6,7 +6,7 @@
# Simulator : AMD Vivado Simulator
# Description : Script for compiling the simulation design source files
#
# Generated by Vivado on Tue Mar 03 03:46:01 CET 2026
# Generated by Vivado on Wed Mar 04 01:36:45 CET 2026
# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

2
riscv-ac.sim/sim_1/behav/xsim/elaborate.sh
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@@ -6,7 +6,7 @@
# Simulator : AMD Vivado Simulator
# Description : Script for elaborating the compiled design
#
# Generated by Vivado on Tue Mar 03 03:46:03 CET 2026
# Generated by Vivado on Wed Mar 04 01:36:46 CET 2026
# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

2
riscv-ac.sim/sim_1/behav/xsim/simulate.sh
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@@ -6,7 +6,7 @@
# Simulator : AMD Vivado Simulator
# Description : Script for simulating the design by launching the simulator
#
# Generated by Vivado on Tue Mar 03 03:46:04 CET 2026
# Generated by Vivado on Wed Mar 04 01:36:48 CET 2026
# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.

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riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsim.rlx
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{
crc : 16958966524678923290 ,
crc : 8975882019563799446 ,
ccp_crc : 0 ,
cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_riscv_behav xil_defaultlib.tb_riscv xil_defaultlib.glbl" ,
buildDate : "Nov 14 2025" ,

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riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_riscv_behav/xsimSettings.ini
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@@ -28,8 +28,8 @@ VARIABLE_PROTOINST_FILTER=true
SCOPE_NAME_COLUMN_WIDTH=100
SCOPE_DESIGN_UNIT_COLUMN_WIDTH=83
SCOPE_BLOCK_TYPE_COLUMN_WIDTH=103
OBJECT_NAME_COLUMN_WIDTH=147
OBJECT_VALUE_COLUMN_WIDTH=49
OBJECT_NAME_COLUMN_WIDTH=75
OBJECT_VALUE_COLUMN_WIDTH=75
OBJECT_DATA_TYPE_COLUMN_WIDTH=75
PROCESS_NAME_COLUMN_WIDTH=75
PROCESS_TYPE_COLUMN_WIDTH=75

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riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/alu.sdb
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riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx
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@@ -4,7 +4,6 @@ Nov 14 2025
12:36:23
/home/jomaa/git/riscv-ac/riscv-ac.sim/sim_1/behav/xsim/glbl.v,1756381829,verilog,,,,glbl,,,,,,,,
,,,,,,tb_riscv,,,,,,,,
,,,,,,,,,,,,,,
/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/alu.v,1772490502,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/control.v,,alu,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/control.v,1772486779,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/dmem.v,,control,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/dmem.v,1772490163,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/ex_me.v,,dmem,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
@@ -18,6 +17,6 @@ Nov 14 2025
/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/me_wb.v,1772490599,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/pc.v,,me_wb,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/pc.v,1772490088,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/regfile.v,,pc,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/regfile.v,1772483280,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/riscv.v,,regfile,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/riscv.v,1772505870,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/uart_bootloader.v,,riscv,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/riscv.v,1772584556,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/uart_bootloader.v,,riscv,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/uart_bootloader.v,1772505678,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/uart_tx.v,,uart_bootloader,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/uart_tx.v,1772503459,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sim_1/new/tb_riscv.v,,uart_tx,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,

13
riscv-ac.srcs/sources_1/new/riscv.v
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@@ -25,9 +25,9 @@ module riscv (
input wire rst,
input wire rx,
output wire tx,
output wire [1:0] leds
// output wire [7:0] uart_tx_data, // SOLO SIMULACION
// output wire uart_tx_en // SOLO SIMULACION
output wire [1:0] leds,
output wire [7:0] uart_tx_data, // SOLO SIMULACION
output wire uart_tx_en // SOLO SIMULACION
);
// ==========================================
@@ -53,7 +53,7 @@ module riscv (
// ETAPA IF
// ==========================================
wire [31:0] npc_IF, pc4_IF, ir_IF, next_pc_IF, pc_stall;
wire PC_En, IF_ID_En, IF_ID_Clr;
wire PC_En, IF_ID_En, IF_ID_Clr, Branch_Taken;
assign next_pc_IF = (Branch_Taken) ? branch_target_ID : pc4_IF;
assign pc4_IF = npc_IF + 4;
@@ -99,7 +99,6 @@ module riscv (
// Señales de Control
wire we_reg_ID, we_mem_ID, mem_to_reg_ID, alu_src_ID, branch_ID, jump_ID;
wire [3:0] alu_op_ID;
wire Branch_Taken;
wire [31:0] branch_target_ID;
control u_control (
@@ -212,8 +211,8 @@ module riscv (
// --- hacemos un apaño pa poder sacar cosas a la UART (MMIO) ---
wire is_uart = (alu_res_ME == 32'hFFFFFFFC);
wire dmem_we = we_mem_ME & ~is_uart; // si va pa la UART no escribimos en memoria
wire [7:0] uart_tx_data;
wire uart_tx_en;
//wire [7:0] uart_tx_data;
//wire uart_tx_en;
assign uart_tx_en = we_mem_ME & is_uart;
assign uart_tx_data = regB_ME[7:0];

126
riscv-ac.srcs/sources_1/new/uart_bootloader.v
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@@ -19,128 +19,6 @@
//
//////////////////////////////////////////////////////////////////////////////////
module uart_bootloader (
input wire clk, // Reloj de la placa (12 MHz)
input wire rx, // Cable de entrada de datos desde el USB
output reg [31:0] prog_data, // Instrucción completa de 32 bits
output reg [31:0] prog_addr, // Dirección donde vamos a guardarla
output reg prog_we, // Señal para escribir en la imem
output wire cpu_rst // Mantiene al RISC-V en reset mientras programamos
);
// Parámetros para 12 MHz y 115200 baudios
// 12.000.000 / 115200 = 104 ciclos por bit
localparam CLKS_PER_BIT = 104;
// 1 segundo de timeout a 12 MHz para soltar el reset
localparam TIMEOUT_LIMIT = 12_000_000;
// Estados de la máquina UART RX
localparam S_IDLE = 2'b00;
localparam S_START = 2'b01;
localparam S_DATA = 2'b10;
localparam S_STOP = 2'b11;
reg [1:0] state = S_IDLE;
reg [7:0] clk_count = 0;
reg [2:0] bit_index = 0;
reg [7:0] rx_byte = 0;
reg rx_done = 0;
// --- 1. MÁQUINA DE ESTADOS UART RX ---
always @(posedge clk) begin
rx_done <= 0;
case (state)
S_IDLE: begin
clk_count <= 0;
bit_index <= 0;
if (rx == 1'b0) // Detectamos el Start Bit (baja a 0)
state <= S_START;
end
S_START: begin
if (clk_count == (CLKS_PER_BIT / 2)) begin
if (rx == 1'b0) begin // Confirmamos que es un Start bit válido
clk_count <= 0;
state <= S_DATA;
end else
state <= S_IDLE;
end else
clk_count <= clk_count + 1;
end
S_DATA: begin
if (clk_count == CLKS_PER_BIT - 1) begin
clk_count <= 0;
rx_byte[bit_index] <= rx; // Guardamos el bit
if (bit_index == 7) begin
bit_index <= 0;
state <= S_STOP;
end else
bit_index <= bit_index + 1;
end else
clk_count <= clk_count + 1;
end
S_STOP: begin
if (clk_count == CLKS_PER_BIT - 1) begin
rx_done <= 1; // ¡Byte recibido de lujo!
state <= S_IDLE;
end else
clk_count <= clk_count + 1;
end
endcase
end
// --- 2. ENSAMBLADOR DE 32 BITS Y CONTROL DE TIMEOUT ---
reg [1:0] byte_count = 0;
reg [23:0] timeout_counter = 0;
reg is_programming = 1; // Empezamos en modo programación por defecto
// El procesador está en reset (apagado) mientras is_programming sea 1
assign cpu_rst = is_programming;
always @(posedge clk) begin
prog_we <= 0; // Por defecto no escribimos
if (rx_done) begin
// Ha llegado un byte nuevo, reseteamos el timeout
timeout_counter <= 0;
is_programming <= 1;
// RISC-V usa Little Endian (el byte menos significativo llega primero)
prog_data <= {rx_byte, prog_data[31:8]};
if (byte_count == 3) begin
byte_count <= 0;
prog_we <= 1; // ¡Tenemos los 32 bits! Damos la orden de escribir
// Avanzamos la dirección para la siguiente instrucción (después de escribir)
end else begin
byte_count <= byte_count + 1;
end
end else begin
// Si acabamos de escribir, subimos la dirección
if (prog_we) begin
prog_addr <= prog_addr + 4;
end
// Control de timeout (perro guardián)
if (is_programming) begin
if (timeout_counter == TIMEOUT_LIMIT) begin
is_programming <= 0; // ¡Se acabó el tiempo! Soltamos al procesador
prog_addr <= 0; // Reseteamos el puntero para la próxima vez
byte_count <= 0;
end else begin
timeout_counter <= timeout_counter + 1;
end
end
end
end
endmodule`timescale 1ns / 1ps
`default_nettype none
module uart_bootloader (
input wire clk, // reloj de la placa (12 MHz)
input wire rx, // cable de entrada de datos desde el USB
@@ -153,8 +31,8 @@ module uart_bootloader (
// parámetros para 12 MHz y 115200 de baudrate
// 12e6 / 115200 = 104 ciclos por bit
// 1 segundo de timeout a 12 MHz para soltar el reset
localparam CLKS_PER_BIT = 104; // 868;
localparam TIMEOUT_LIMIT = 12_000_000; // 50000;
localparam CLKS_PER_BIT = 868; // 104;
localparam TIMEOUT_LIMIT = 50000; // 12_000_000;
localparam S_IDLE = 2'b00;
localparam S_START = 2'b01;

2
riscv-ac.srcs/sources_1/new/uart_tx.v
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@@ -28,7 +28,7 @@ module uart_tx (
);
// 12e6 / 115200 = 104 ciclos
localparam CLKS_PER_BIT = 104; // 104;
localparam CLKS_PER_BIT = 868; // 104;
localparam S_IDLE = 2'b00;
localparam S_START = 2'b01;

11
riscv-ac.xpr
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@@ -61,7 +61,7 @@
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/>
<Option Name="DSABoardId" Val="cmod_a7-35t"/>
<Option Name="WTXSimLaunchSim" Val="56"/>
<Option Name="WTXSimLaunchSim" Val="58"/>
<Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/>
@@ -207,6 +207,7 @@
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="riscv"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
@@ -302,7 +303,9 @@
<Runs Version="1" Minor="22">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/riscv.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2025"/>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2025">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -312,7 +315,9 @@
</Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 12 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2025"/>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2025">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>