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Jose 98f948ab18 refactor: renamed all signals for consistency
2026-03-02 23:34:31 +01:00
riscv-ac.sim/sim_1/behav/xsim
refactor: renamed all signals for consistency
2026-03-02 23:34:31 +01:00
riscv-ac.srcs
refactor: renamed all signals for consistency
2026-03-02 23:34:31 +01:00
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README.md
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riscv-ac.xpr
refactor: renamed all signals for consistency
2026-03-02 23:34:31 +01:00
tb_top_behav.wcfg
prototype works
2026-03-02 23:20:54 +01:00

README.md

riscv-ac

FPGA playground for implementing RISC-V (AC version). This is for learning purposes.

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Description
FPGA playground for implementing RISC-V (AC version). This is for learning purposes.
Readme GPL-3.0 6.4 MiB
Languages
Verilog 69.9%
Tcl 24.7%
Shell 5.4%