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Jose
49
riscv-ac.srcs/sources_1/new/alu.v
Normal file
49
riscv-ac.srcs/sources_1/new/alu.v
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@@ -0,0 +1,49 @@
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||||
`timescale 1ns / 1ps
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||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 02/20/2026 09:21:52 AM
|
||||
// Design Name:
|
||||
// Module Name: alu
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
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||||
|
||||
|
||||
module alu(
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input [31:0] A, B,
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input [3:0] sel,
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output reg [31:0] R,
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output zero
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);
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always @(*) begin
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case(sel)
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4'b0000: R <= A + B; // add
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4'b0001: R <= A - B; // sub
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4'b0010: R <= A & B; // and
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4'b0011: R <= A | B; // or
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4'b0100: R <= A ^ B; // xor
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4'b0101: R <= A << B[4:0]; // sll (shamt = 5 bits)
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4'b0110: R <= A >> B[4:0]; // srl (logical)
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4'b0111: R <= ($signed(A) < $signed(B)) ? 1 : 0; // slt signed
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4'b1000: R <= (A < B) ? 1 : 0; // sltu unsigned
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4'b1001: R <= $signed(A) >>> B[4:0]; // sra arithmetic right
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4'b1010: R <= 32'b0; // default / nop opcional
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default: R <= 32'b0;
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endcase
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end
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assign zero = (R == 0);
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endmodule
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114
riscv-ac.srcs/sources_1/new/control.v
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114
riscv-ac.srcs/sources_1/new/control.v
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@@ -0,0 +1,114 @@
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`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 02/20/2026 09:21:52 AM
|
||||
// Design Name:
|
||||
// Module Name: control
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
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||||
//////////////////////////////////////////////////////////////////////////////////
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||||
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module control(
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input [6:0] opcode,
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input [2:0] funct3,
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input [6:0] funct7,
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output reg we_reg,
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output reg we_mem,
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output reg mem_to_reg,
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output reg alu_src,
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output reg [3:0] alu_op,
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output reg branch
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);
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localparam OP_R = 7'b0110011;
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localparam OP_I = 7'b0010011;
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localparam OP_LOAD= 7'b0000011;
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localparam OP_STORE=7'b0100011;
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localparam OP_BRANCH=7'b1100011;
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localparam OP_JAL = 7'b1101111;
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always @(*) begin
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we_reg = 0;
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we_mem = 0;
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mem_to_reg = 0;
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alu_src = 0;
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alu_op = 4'b0000;
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branch = 0;
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case(opcode)
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OP_R: begin
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we_reg = 1;
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alu_src = 0;
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case({funct7,funct3})
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10'b0000000000: alu_op = 4'b0000; // ADD
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10'b0100000000: alu_op = 4'b0001; // SUB
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10'b0000000111: alu_op = 4'b0010; // AND
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10'b0000000110: alu_op = 4'b0011; // OR
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10'b0000000100: alu_op = 4'b0100; // XOR
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10'b0000000001: alu_op = 4'b0101; // SLL
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10'b0000000101: alu_op = 4'b0110; // SRL
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10'b0100000101: alu_op = 4'b0111; // SRA
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10'b0000000010: alu_op = 4'b1000; // SLT
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10'b0000000011: alu_op = 4'b1001; // SLTU
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endcase
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end
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OP_I: begin
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we_reg = 1;
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alu_src = 1;
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case(funct3)
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3'b000: alu_op = 4'b0000; // ADDI
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3'b111: alu_op = 4'b0010; // ANDI
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3'b110: alu_op = 4'b0011; // ORI
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3'b100: alu_op = 4'b0100; // XORI
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3'b001: alu_op = 4'b0101; // SLLI
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3'b101: alu_op = (funct7==7'b0000000)?4'b0110:4'b0111; // SRLI/SRAI
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3'b010: alu_op = 4'b1000; // SLTI
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3'b011: alu_op = 4'b1001; // SLTIU
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endcase
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end
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OP_LOAD: begin
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we_reg = 1;
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we_mem = 0;
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mem_to_reg = 1;
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alu_src = 1; // addr = rs1 + immediate
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alu_op = 4'b0000;
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end
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OP_STORE: begin
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we_mem = 1;
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alu_src = 1; // addr = rs1 + immediate
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alu_op = 4'b0000;
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end
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OP_BRANCH: begin
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branch = 1;
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alu_src = 0;
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alu_op = 4'b0001;
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end
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OP_JAL: begin
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we_reg = 1; // rd <- PC+4
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alu_src = 1;
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alu_op = 4'b0000;
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end
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default: begin end
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endcase
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end
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endmodule
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40
riscv-ac.srcs/sources_1/new/dmem.v
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40
riscv-ac.srcs/sources_1/new/dmem.v
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@@ -0,0 +1,40 @@
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`timescale 1ns / 1ps
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||||
//////////////////////////////////////////////////////////////////////////////////
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||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 02/20/2026 09:21:52 AM
|
||||
// Design Name:
|
||||
// Module Name: dmem
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
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||||
// Additional Comments:
|
||||
//
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||||
//////////////////////////////////////////////////////////////////////////////////
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||||
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||||
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||||
module dmem(
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input clk,
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input we,
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input [31:0] address,
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input [31:0] write_data,
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output [31:0] read_data
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||||
);
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reg [31:0] memory[0:255];
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always @(posedge clk) begin
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if (we)
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memory[address[9:2]] <= write_data;
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end
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||||
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||||
assign read_data = memory[address[9:2]];
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||||
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||||
endmodule
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||||
40
riscv-ac.srcs/sources_1/new/imem.v
Normal file
40
riscv-ac.srcs/sources_1/new/imem.v
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@@ -0,0 +1,40 @@
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||||
`timescale 1ns / 1ps
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||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 02/20/2026 09:21:52 AM
|
||||
// Design Name:
|
||||
// Module Name: imem
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module imem(
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||||
input clk,
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input [31:0] address,
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input we,
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input [31:0] write_data,
|
||||
input [7:0] write_addr,
|
||||
output [31:0] instruction
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||||
);
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||||
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||||
reg [31:0] memory[0:255];
|
||||
|
||||
always @(posedge clk) begin
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||||
if(we)
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||||
memory[write_addr] <= write_data;
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||||
end
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||||
|
||||
assign instruction = memory[address[9:2]];
|
||||
|
||||
endmodule
|
||||
40
riscv-ac.srcs/sources_1/new/imm_gen.v
Normal file
40
riscv-ac.srcs/sources_1/new/imm_gen.v
Normal file
@@ -0,0 +1,40 @@
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||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 02/20/2026 09:21:52 AM
|
||||
// Design Name:
|
||||
// Module Name: imm_gen
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module imm_gen(
|
||||
input [31:0] instr,
|
||||
output reg [31:0] imm_out
|
||||
);
|
||||
|
||||
always @(*) begin
|
||||
case(instr[6:0])
|
||||
7'b0010011,
|
||||
7'b0000011:
|
||||
imm_out = {{20{instr[31]}}, instr[31:20]};
|
||||
7'b1101111:
|
||||
imm_out = {{11{instr[31]}}, instr[31], instr[19:12], instr[20], instr[30:21], 1'b0};
|
||||
default:
|
||||
imm_out = 32'b0;
|
||||
endcase
|
||||
end
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||||
|
||||
endmodule
|
||||
34
riscv-ac.srcs/sources_1/new/pc.v
Normal file
34
riscv-ac.srcs/sources_1/new/pc.v
Normal file
@@ -0,0 +1,34 @@
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||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 02/20/2026 09:21:52 AM
|
||||
// Design Name:
|
||||
// Module Name: pc
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module pc(
|
||||
input clk, rst,
|
||||
input [31:0] next_pc,
|
||||
output reg [31:0] imem_addr
|
||||
);
|
||||
|
||||
always @(posedge clk or posedge rst) begin
|
||||
if (rst) imem_addr <= 0;
|
||||
else imem_addr <= next_pc;
|
||||
end
|
||||
|
||||
endmodule
|
||||
39
riscv-ac.srcs/sources_1/new/regfile.v
Normal file
39
riscv-ac.srcs/sources_1/new/regfile.v
Normal file
@@ -0,0 +1,39 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 02/20/2026 09:21:52 AM
|
||||
// Design Name:
|
||||
// Module Name: regfile
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module regfile(
|
||||
input clk, regwrite,
|
||||
input [4:0] rs1, rs2, rd,
|
||||
input [31:0] write_data,
|
||||
output [31:0] read_data_1, read_data_2
|
||||
);
|
||||
|
||||
reg [31:0] regs[0:31];
|
||||
|
||||
assign read_data_1 = (rs1 == 0) ? 0 : regs[rs1];
|
||||
assign read_data_2 = (rs2 == 0) ? 0 : regs[rs2];
|
||||
|
||||
always @(posedge clk) begin
|
||||
if (regwrite && rd != 0) regs[rd] <= write_data;
|
||||
end
|
||||
|
||||
endmodule
|
||||
135
riscv-ac.srcs/sources_1/new/top.v
Normal file
135
riscv-ac.srcs/sources_1/new/top.v
Normal file
@@ -0,0 +1,135 @@
|
||||
`timescale 1ns / 1ps
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
// Company:
|
||||
// Engineer:
|
||||
//
|
||||
// Create Date: 02/20/2026 09:21:52 AM
|
||||
// Design Name:
|
||||
// Module Name: top
|
||||
// Project Name:
|
||||
// Target Devices:
|
||||
// Tool Versions:
|
||||
// Description:
|
||||
//
|
||||
// Dependencies:
|
||||
//
|
||||
// Revision:
|
||||
// Revision 0.01 - File Created
|
||||
// Additional Comments:
|
||||
//
|
||||
//////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
|
||||
module top(
|
||||
input clk, rst,
|
||||
input [31:0] uart_data,
|
||||
output [31:0] pc_out, alu_out, mem_data
|
||||
);
|
||||
|
||||
// = PC ===================================
|
||||
wire [31:0] pc_next, pc;
|
||||
wire branch_taken;
|
||||
|
||||
pc pc_inst(
|
||||
.clk(clk),
|
||||
.rst(rst),
|
||||
.next_pc(pc_next),
|
||||
.imem_addr(pc_curr)
|
||||
);
|
||||
|
||||
assign pc_out = pc_curr;
|
||||
// ========================================
|
||||
|
||||
// = IMEM =================================
|
||||
wire [31:0] instr;
|
||||
|
||||
imem imem_inst(
|
||||
.address(pc_curr),
|
||||
.instruction(instr)
|
||||
);
|
||||
// ========================================
|
||||
|
||||
// = DECODE ===============================
|
||||
wire [6:0] opcode = instr[6:0];
|
||||
wire [4:0] rd = instr[11:7];
|
||||
wire [2:0] funct3 = instr[14:12];
|
||||
wire [4:0] rs1 = instr[19:15];
|
||||
wire [4:0] rs2 = instr[24:20];
|
||||
wire [6:0] funct7 = instr[31:25];
|
||||
// ========================================
|
||||
|
||||
// regfile mux
|
||||
wire [31:0] reg_write_data;
|
||||
assign reg_write_data = mem_to_reg ? dmem_read_data : alu_out;
|
||||
|
||||
// = REGFILE ===============================
|
||||
wire [31:0] reg_r1, reg_r2;
|
||||
wire we_reg;
|
||||
|
||||
regfile regfile_inst(
|
||||
.clk(clk),
|
||||
.regwrite(we_reg),
|
||||
.rs1(rs1),
|
||||
.rs2(rs2),
|
||||
.rd(rd),
|
||||
.write_data(reg_write_data),
|
||||
.read_data_1(reg_r1),
|
||||
.read_data_2(reg_r2)
|
||||
);
|
||||
// ========================================
|
||||
|
||||
// = IMMGEN ===============================
|
||||
wire [31:0] imm_out;
|
||||
|
||||
imm_gen imm_gen_inst(
|
||||
.instr(instr),
|
||||
.imm_out(imm_out)
|
||||
);
|
||||
// ========================================
|
||||
|
||||
// = CONTROL ===============================
|
||||
wire we_mem, mem_to_reg, alu_src;
|
||||
wire [3:0] alu_op;
|
||||
|
||||
control control_inst(
|
||||
.opcode(opcode),
|
||||
.funct3(funct3),
|
||||
.funct7(funct7),
|
||||
.we_reg(we_reg),
|
||||
.we_mem(we_mem),
|
||||
.mem_to_reg(mem_to_reg),
|
||||
.alu_src(alu_src),
|
||||
.alu_op(alu_op),
|
||||
.branch(branch_taken)
|
||||
);
|
||||
// ========================================
|
||||
|
||||
// = ALU ==================================
|
||||
wire [31:0] alu_b = alu_src ? imm_out : reg_r2;
|
||||
|
||||
alu alu_inst(
|
||||
.A(reg_r1),
|
||||
.B(alu_b),
|
||||
.sel(alu_op),
|
||||
.R(alu_out)
|
||||
);
|
||||
// ========================================
|
||||
|
||||
// = DMEM =================================
|
||||
wire [31:0] dmem_read_data;
|
||||
|
||||
dmem dmem_inst(
|
||||
.clk(clk),
|
||||
.we(we_mem),
|
||||
.address(alu_out),
|
||||
.write_data(reg_r2),
|
||||
.read_data(dmem_read_data)
|
||||
);
|
||||
|
||||
assign mem_data = dmem_read_data;
|
||||
// ========================================
|
||||
|
||||
// PC increment
|
||||
assign pc_next = branch_taken ? (pc_curr + imm_out) : (pc_curr + 4);
|
||||
|
||||
endmodule
|
||||
282
riscv-ac.xpr
Normal file
282
riscv-ac.xpr
Normal file
@@ -0,0 +1,282 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- Product Version: Vivado v2025.2 (64-bit) -->
|
||||
<!-- -->
|
||||
<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
|
||||
<!-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. -->
|
||||
|
||||
<Project Product="Vivado" Version="7" Minor="71" Path="/home/jomaa/Projects/vivado/riscv-ac/riscv-ac.xpr">
|
||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="2041d6f4559245b6ae163170cfe36c08"/>
|
||||
<Option Name="Part" Val="xc7a35tcpg236-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
|
||||
<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
|
||||
<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
|
||||
<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
|
||||
<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
|
||||
<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
|
||||
<Option Name="SimulatorInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirVCS" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
|
||||
<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
|
||||
<Option Name="SimulatorVersionXsim" Val="2025.2"/>
|
||||
<Option Name="SimulatorVersionModelSim" Val="2025.2"/>
|
||||
<Option Name="SimulatorVersionQuesta" Val="2025.2"/>
|
||||
<Option Name="SimulatorVersionXcelium" Val="25.03.002"/>
|
||||
<Option Name="SimulatorVersionVCS" Val="X-2025.06"/>
|
||||
<Option Name="SimulatorVersionRiviera" Val="2024.10"/>
|
||||
<Option Name="SimulatorVersionActiveHdl" Val="15.0"/>
|
||||
<Option Name="SimulatorGccVersionXsim" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
|
||||
<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
|
||||
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
|
||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
|
||||
<Option Name="BoardPart" Val="digilentinc.com:cmod_a7-35t:part0:1.2"/>
|
||||
<Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../.Xilinx/Vivado/2025.2/xhub/board_store/xilinx_board_store"/>
|
||||
<Option Name="ActiveSimSet" Val="sim_1"/>
|
||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
||||
<Option Name="ProjectType" Val="Default"/>
|
||||
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
|
||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="EnableResourceEstimation" Val="FALSE"/>
|
||||
<Option Name="SimCompileState" Val="TRUE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="DSABoardId" Val="cmod_a7-35t"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="0"/>
|
||||
<Option Name="WTModelSimExportSim" Val="0"/>
|
||||
<Option Name="WTQuestaExportSim" Val="0"/>
|
||||
<Option Name="WTIesExportSim" Val="0"/>
|
||||
<Option Name="WTVcsExportSim" Val="0"/>
|
||||
<Option Name="WTRivieraExportSim" Val="0"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="0"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
|
||||
<Option Name="SimTypes" Val="bfm"/>
|
||||
<Option Name="SimTypes" Val="tlm"/>
|
||||
<Option Name="SimTypes" Val="tlm_dpi"/>
|
||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
|
||||
<Option Name="UseInlineHdlIP" Val="TRUE"/>
|
||||
<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
|
||||
</Configuration>
|
||||
<FileSets Version="1" Minor="32">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PSRCDIR/sources_1/new/alu.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/control.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/dmem.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/imem.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/imm_gen.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/pc.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/regfile.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<File Path="$PSRCDIR/sources_1/new/top.v">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
|
||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="top"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
|
||||
<Filter Type="Constrs"/>
|
||||
<Config>
|
||||
<Option Name="ConstrsType" Val="XDC"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="top"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="PamDesignTestbench" Val=""/>
|
||||
<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
|
||||
<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
|
||||
<Option Name="PamPseudoTop" Val="pseudo_tb"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
<Option Name="CosimPdi" Val=""/>
|
||||
<Option Name="CosimPlatform" Val=""/>
|
||||
<Option Name="CosimElf" Val=""/>
|
||||
<Option Name="CosimRootfs" Val=""/>
|
||||
<Option Name="CosimSDfile" Val=""/>
|
||||
<Option Name="CosimSDDir" Val=""/>
|
||||
<Option Name="CosimOutDir" Val=""/>
|
||||
<Option Name="CosimXsa" Val=""/>
|
||||
<Option Name="CosimAIKernel" Val=""/>
|
||||
<Option Name="LogicalNoCTop" Val=""/>
|
||||
<Option Name="LogicalNoCTopLib" Val=""/>
|
||||
<Option Name="Dmv" Val=""/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
|
||||
<Filter Type="Utils"/>
|
||||
<Config>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
</FileSets>
|
||||
<Simulators>
|
||||
<Simulator Name="XSim">
|
||||
<Option Name="Description" Val="Vivado Simulator"/>
|
||||
<Option Name="CompiledLib" Val="0"/>
|
||||
</Simulator>
|
||||
<Simulator Name="ModelSim">
|
||||
<Option Name="Description" Val="ModelSim Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Questa">
|
||||
<Option Name="Description" Val="Questa Advanced Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Xcelium">
|
||||
<Option Name="Description" Val="Xcelium Parallel Simulator"/>
|
||||
</Simulator>
|
||||
<Simulator Name="VCS">
|
||||
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
||||
</Simulator>
|
||||
<Simulator Name="Riviera">
|
||||
<Option Name="Description" Val="Riviera-PRO Simulator"/>
|
||||
</Simulator>
|
||||
</Simulators>
|
||||
<Runs Version="1" Minor="22">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2025">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2025"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2025">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2025"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
</Runs>
|
||||
<Board>
|
||||
<Jumpers/>
|
||||
</Board>
|
||||
<DashboardSummary Version="1" Minor="0">
|
||||
<Dashboards>
|
||||
<Dashboard Name="default_dashboard">
|
||||
<Gadgets>
|
||||
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
|
||||
<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
|
||||
<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
|
||||
</Gadget>
|
||||
<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
|
||||
<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
|
||||
</Gadget>
|
||||
</Gadgets>
|
||||
</Dashboard>
|
||||
<CurrentDashboard>default_dashboard</CurrentDashboard>
|
||||
</Dashboards>
|
||||
</DashboardSummary>
|
||||
</Project>
|
||||
Reference in New Issue
Block a user