41 lines
873 B
Verilog
41 lines
873 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 02/20/2026 09:21:52 AM
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// Design Name:
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// Module Name: imm_gen
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module imm_gen(
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input [31:0] instr,
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output reg [31:0] imm_out
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);
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always @(*) begin
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case(instr[6:0])
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7'b0010011,
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7'b0000011:
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imm_out = {{20{instr[31]}}, instr[31:20]};
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7'b1101111:
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imm_out = {{11{instr[31]}}, instr[31], instr[19:12], instr[20], instr[30:21], 1'b0};
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default:
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imm_out = 32'b0;
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endcase
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end
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endmodule
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