41 lines
795 B
Verilog
41 lines
795 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 02/20/2026 09:21:52 AM
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// Design Name:
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// Module Name: imem
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module imem(
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input clk,
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input [31:0] address,
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input we,
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input [31:0] write_data,
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input [7:0] write_addr,
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output [31:0] instruction
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);
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reg [31:0] memory[0:255];
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always @(posedge clk) begin
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if(we)
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memory[write_addr] <= write_data;
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end
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assign instruction = memory[address[9:2]];
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endmodule
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