40 lines
841 B
Verilog
40 lines
841 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 02/20/2026 09:21:52 AM
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// Design Name:
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// Module Name: regfile
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module regfile(
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input clk, regwrite,
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input [4:0] rs1, rs2, rd,
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input [31:0] write_data,
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output [31:0] read_data_1, read_data_2
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);
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reg [31:0] regs[0:31];
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assign read_data_1 = (rs1 == 0) ? 0 : regs[rs1];
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assign read_data_2 = (rs2 == 0) ? 0 : regs[rs2];
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always @(posedge clk) begin
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if (regwrite && rd != 0) regs[rd] <= write_data;
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end
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endmodule
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