35 lines
680 B
Verilog
35 lines
680 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 02/20/2026 09:21:52 AM
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// Design Name:
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// Module Name: pc
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module pc(
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input clk, rst,
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input [31:0] next_pc,
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output reg [31:0] imem_addr
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);
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always @(posedge clk or posedge rst) begin
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if (rst) imem_addr <= 0;
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else imem_addr <= next_pc;
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end
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endmodule
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