49 lines
981 B
Verilog
49 lines
981 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: nope
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// Engineer: Jose
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//
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// Create Date: 02/20/2026 09:21:52 AM
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// Design Name: Data Memory
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// Module Name: dmem
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// Project Name: riscv-ac
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// Target Devices: Artix 7
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// Tool Versions: 2025.2
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// Description: Stores data
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//
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// Dependencies:
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//
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// Revision: 1.0
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module dmem(
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input clk,
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input we,
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input [31:0] address,
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input [31:0] write_data,
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output [31:0] mem_data_out
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);
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reg [31:0] memory[0:255];
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reg [31:0] data_reg;
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integer i;
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initial begin
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for (i = 0; i < 256; i = i + 1) begin
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memory[i] = 32'b0;
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end
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end
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always @(posedge clk) begin
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if (we)
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memory[address[9:2]] <= write_data;
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data_reg <= memory[address[9:2]];
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end
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assign mem_data_out = data_reg;
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endmodule |