50 lines
1.5 KiB
Verilog
50 lines
1.5 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: nope
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// Engineer: Jose
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//
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// Create Date: 02/20/2026 09:21:52 AM
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// Design Name: Arithmetic-Logic Unit
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// Module Name: alu
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// Project Name: riscv-ac
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// Target Devices: Artix 7
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// Tool Versions: 2025.2
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// Description: Main functional unit of the EX stage
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//
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// Dependencies:
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//
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// Revision: 1.0
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module alu(
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input [31:0] A, B,
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input [3:0] sel,
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output reg [31:0] R,
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output zero
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);
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always @(*) begin
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case(sel)
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4'b0000: R = A + B; // add
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4'b0001: R = A - B; // sub
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4'b0010: R = A & B; // and
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4'b0011: R = A | B; // or
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4'b0100: R = A ^ B; // xor
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4'b0101: R = A << B[4:0]; // sll
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4'b0110: R = A >> B[4:0]; // srl
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4'b0111: R = ($signed(A) < $signed(B)) ? 1 : 0; // slt
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4'b1000: R = (A < B) ? 1 : 0; // sltu
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4'b1001: R = $signed(A) >>> B[4:0]; // sra
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4'b1010: R = 32'b0; // nop
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default: R = 32'b0; // default: nop
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endcase
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end
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assign zero = (R == 0);
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endmodule
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