Gallardo7761/riscv-ac
1
1
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
7 Commits 1 Branch 0 Tags
d7e166ca6f7326bd23905dbf16cf91637a180e4b
Go to file
Clone
Open with VS Code Open with VSCodium Open with Intellij IDEA
Download ZIP Download TAR.GZ Download BUNDLE
Jose d7e166ca6f refactor: renamed top.v to riscv.v
2026-03-03 04:05:49 +01:00
riscv-ac.runs
refactor: renamed top.v to riscv.v
2026-03-03 04:05:49 +01:00
riscv-ac.sim/sim_1/behav/xsim
refactor: renamed top.v to riscv.v
2026-03-03 04:05:49 +01:00
riscv-ac.srcs
refactor: renamed top.v to riscv.v
2026-03-03 04:05:49 +01:00
.gitignore
Initial commit
2026-02-20 11:32:16 +01:00
LICENSE
Initial commit
2026-02-20 11:32:16 +01:00
README.md
Initial commit
2026-02-20 11:32:16 +01:00
riscv-ac.xpr
refactor: renamed top.v to riscv.v
2026-03-03 04:05:49 +01:00
schematic.pdf
refactor: renamed top.v to riscv.v
2026-03-03 04:05:49 +01:00
tb_top_behav.wcfg
prototype works
2026-03-02 23:20:54 +01:00

README.md

riscv-ac

FPGA playground for implementing RISC-V (AC version). This is for learning purposes.

Reference in New Issue View Git Blame Copy Permalink
Description
FPGA playground for implementing RISC-V (AC version). This is for learning purposes.
Readme GPL-3.0 6.4 MiB
Languages
Verilog 69.9%
Tcl 24.7%
Shell 5.4%