`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: nope
// Engineer: Jose
// 
// Create Date: 02/20/2026 09:21:52 AM
// Design Name: Program Counter
// Module Name: pc
// Project Name: riscv-ac
// Target Devices: Artix 7
// Tool Versions: 2025.2
// Description: Points to the next instruction
// 
// Dependencies: 
// 
// Revision: 1.0
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module pc(
    input clk, rst,
    input [31:0] next_pc,
    output reg [31:0] pc_out
);

always @(posedge clk or posedge rst) begin
    if (rst) pc_out <= 0; 
    else pc_out <= next_pc;
end

endmodule
