61 lines
1.3 KiB
Verilog
61 lines
1.3 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: nope
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// Engineer: Jose
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//
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// Create Date: 02/20/2026 09:21:52 AM
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// Design Name: RISCV AC Processor Simulation
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// Module Name: tb_top
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// Project Name: riscv-ac
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// Target Devices: Artix 7
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// Tool Versions: 2025.2
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// Description: Testbench for simulation + MMIO
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//
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// Dependencies:
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//
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// Revision: 2.0 - MMIO
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// Revision: 1.0 - Basic structure
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// Revision: 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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module tb_top();
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reg clk;
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reg rst;
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wire [1:0] leds;
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wire [31:0] uart_tx_data;
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wire uart_tx_en;
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top uut (
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.clk(clk),
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.rst(rst),
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.leds(leds),
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.uart_tx_data(uart_tx_data),
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.uart_tx_en(uart_tx_en)
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);
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// T_CLK = 10ns
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always #5 clk = ~clk;
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initial begin
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// inicializamos señales
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clk = 0;
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rst = 1;
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// cargamos programa
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$readmemh("/home/jomaa/git/riscv-ac/riscv-ac.srcs/sim_1/new/program.mem", uut.u_imem.memory);
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// activamos reset 20ns
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#20;
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rst = 0;
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// ejecución de 100 ciclos
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#150;
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$finish;
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end
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endmodule |