136 lines
2.8 KiB
Verilog
136 lines
2.8 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 02/20/2026 09:21:52 AM
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// Design Name:
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// Module Name: top
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module top(
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input clk, rst,
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input [31:0] uart_data,
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output [31:0] pc_out, alu_out, mem_data
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);
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// = PC ===================================
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wire [31:0] pc_next, pc;
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wire branch_taken;
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pc pc_inst(
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.clk(clk),
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.rst(rst),
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.next_pc(pc_next),
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.imem_addr(pc_curr)
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);
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assign pc_out = pc_curr;
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// ========================================
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// = IMEM =================================
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wire [31:0] instr;
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imem imem_inst(
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.address(pc_curr),
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.instruction(instr)
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);
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// ========================================
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// = DECODE ===============================
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wire [6:0] opcode = instr[6:0];
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wire [4:0] rd = instr[11:7];
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wire [2:0] funct3 = instr[14:12];
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wire [4:0] rs1 = instr[19:15];
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wire [4:0] rs2 = instr[24:20];
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wire [6:0] funct7 = instr[31:25];
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// ========================================
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// regfile mux
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wire [31:0] reg_write_data;
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assign reg_write_data = mem_to_reg ? dmem_read_data : alu_out;
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// = REGFILE ===============================
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wire [31:0] reg_r1, reg_r2;
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wire we_reg;
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regfile regfile_inst(
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.clk(clk),
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.regwrite(we_reg),
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.rs1(rs1),
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.rs2(rs2),
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.rd(rd),
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.write_data(reg_write_data),
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.read_data_1(reg_r1),
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.read_data_2(reg_r2)
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);
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// ========================================
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// = IMMGEN ===============================
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wire [31:0] imm_out;
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imm_gen imm_gen_inst(
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.instr(instr),
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.imm_out(imm_out)
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);
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// ========================================
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// = CONTROL ===============================
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wire we_mem, mem_to_reg, alu_src;
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wire [3:0] alu_op;
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control control_inst(
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.opcode(opcode),
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.funct3(funct3),
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.funct7(funct7),
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.we_reg(we_reg),
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.we_mem(we_mem),
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.mem_to_reg(mem_to_reg),
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.alu_src(alu_src),
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.alu_op(alu_op),
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.branch(branch_taken)
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);
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// ========================================
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// = ALU ==================================
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wire [31:0] alu_b = alu_src ? imm_out : reg_r2;
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alu alu_inst(
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.A(reg_r1),
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.B(alu_b),
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.sel(alu_op),
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.R(alu_out)
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);
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// ========================================
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// = DMEM =================================
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wire [31:0] dmem_read_data;
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dmem dmem_inst(
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.clk(clk),
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.we(we_mem),
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.address(alu_out),
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.write_data(reg_r2),
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.read_data(dmem_read_data)
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);
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assign mem_data = dmem_read_data;
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// ========================================
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// PC increment
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assign pc_next = branch_taken ? (pc_curr + imm_out) : (pc_curr + 4);
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endmodule
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