`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 02/20/2026 09:21:52 AM
// Design Name: 
// Module Name: pc
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module pc(
    input clk, rst,
    input [31:0] next_pc,
    output reg [31:0] imem_addr
);

always @(posedge clk or posedge rst) begin
    if (rst) imem_addr <= 0; 
    else imem_addr <= next_pc;
end

endmodule