115 lines
2.9 KiB
Verilog
115 lines
2.9 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 02/20/2026 09:21:52 AM
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// Design Name:
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// Module Name: control
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module control(
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input [6:0] opcode,
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input [2:0] funct3,
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input [6:0] funct7,
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output reg we_reg,
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output reg we_mem,
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output reg mem_to_reg,
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output reg alu_src,
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output reg [3:0] alu_op,
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output reg branch
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);
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localparam OP_R = 7'b0110011;
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localparam OP_I = 7'b0010011;
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localparam OP_LOAD= 7'b0000011;
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localparam OP_STORE=7'b0100011;
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localparam OP_BRANCH=7'b1100011;
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localparam OP_JAL = 7'b1101111;
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always @(*) begin
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we_reg = 0;
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we_mem = 0;
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mem_to_reg = 0;
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alu_src = 0;
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alu_op = 4'b0000;
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branch = 0;
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case(opcode)
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OP_R: begin
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we_reg = 1;
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alu_src = 0;
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case({funct7,funct3})
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10'b0000000000: alu_op = 4'b0000; // ADD
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10'b0100000000: alu_op = 4'b0001; // SUB
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10'b0000000111: alu_op = 4'b0010; // AND
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10'b0000000110: alu_op = 4'b0011; // OR
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10'b0000000100: alu_op = 4'b0100; // XOR
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10'b0000000001: alu_op = 4'b0101; // SLL
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10'b0000000101: alu_op = 4'b0110; // SRL
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10'b0100000101: alu_op = 4'b0111; // SRA
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10'b0000000010: alu_op = 4'b1000; // SLT
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10'b0000000011: alu_op = 4'b1001; // SLTU
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endcase
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end
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OP_I: begin
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we_reg = 1;
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alu_src = 1;
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case(funct3)
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3'b000: alu_op = 4'b0000; // ADDI
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3'b111: alu_op = 4'b0010; // ANDI
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3'b110: alu_op = 4'b0011; // ORI
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3'b100: alu_op = 4'b0100; // XORI
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3'b001: alu_op = 4'b0101; // SLLI
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3'b101: alu_op = (funct7==7'b0000000)?4'b0110:4'b0111; // SRLI/SRAI
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3'b010: alu_op = 4'b1000; // SLTI
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3'b011: alu_op = 4'b1001; // SLTIU
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endcase
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end
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OP_LOAD: begin
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we_reg = 1;
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we_mem = 0;
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mem_to_reg = 1;
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alu_src = 1; // addr = rs1 + immediate
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alu_op = 4'b0000;
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end
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OP_STORE: begin
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we_mem = 1;
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alu_src = 1; // addr = rs1 + immediate
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alu_op = 4'b0000;
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end
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OP_BRANCH: begin
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branch = 1;
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alu_src = 0;
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alu_op = 4'b0001;
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end
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OP_JAL: begin
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we_reg = 1; // rd <- PC+4
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alu_src = 1;
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alu_op = 4'b0000;
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end
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default: begin end
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endcase
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end
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endmodule
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