133 lines
4.0 KiB
Verilog
133 lines
4.0 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: nope
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// Engineer: Jose
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//
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// Create Date: 03/03/2026 02:40:56 AM
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// Design Name: Bootloader
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// Module Name: uart_bootloader
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// Project Name: riscv-ac
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// Target Devices: Artix 7
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// Tool Versions: 2025.2
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// Description: Allows dynamic program burning
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//
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// Dependencies:
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//
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// Revision: 1.0
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module uart_bootloader (
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input wire clk, // reloj de la placa (12 MHz)
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input wire rx, // cable de entrada de datos desde el USB
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output reg [31:0] prog_data = 0, // instrucción completa de 32 bits
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output reg [31:0] prog_addr = 0, // dirección donde vamos a guardarla
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output reg prog_we, // señal para escribir en la imem
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output wire cpu_rst // mantiene el CPU en reset mientras programamos
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);
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// parámetros para 12 MHz y 115200 de baudrate
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// 12e6 / 115200 = 104 ciclos por bit
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// 1 segundo de timeout a 12 MHz para soltar el reset
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localparam CLKS_PER_BIT = 868; // 104;
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localparam TIMEOUT_LIMIT = 50000; // 12_000_000;
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localparam S_IDLE = 2'b00;
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localparam S_START = 2'b01;
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localparam S_DATA = 2'b10;
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localparam S_STOP = 2'b11;
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reg [1:0] state = S_IDLE;
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reg [15:0] clk_count = 0;
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reg [2:0] bit_index = 0;
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reg [7:0] rx_byte = 0;
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reg rx_done = 0;
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reg [1:0] byte_count = 0;
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reg [23:0] timeout_counter = 0;
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reg is_programming = 1;
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// FSM de la UART
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always @(posedge clk) begin
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rx_done <= 0;
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case (state)
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S_IDLE: begin
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clk_count <= 0;
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bit_index <= 0;
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if (rx == 1'b0)
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state <= S_START;
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end
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S_START: begin
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if (clk_count == (CLKS_PER_BIT / 2)) begin
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if (rx == 1'b0) begin
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clk_count <= 0;
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state <= S_DATA;
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end else
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state <= S_IDLE;
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end else
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clk_count <= clk_count + 1;
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end
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S_DATA: begin
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if (clk_count == CLKS_PER_BIT - 1) begin
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clk_count <= 0;
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rx_byte[bit_index] <= rx;
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if (bit_index == 7) begin
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bit_index <= 0;
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state <= S_STOP;
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end else
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bit_index <= bit_index + 1;
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end else
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clk_count <= clk_count + 1;
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end
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S_STOP: begin
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if (clk_count == CLKS_PER_BIT - 1) begin
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rx_done <= 1; // byte recibido
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state <= S_IDLE;
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end else
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clk_count <= clk_count + 1;
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end
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endcase
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end
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assign cpu_rst = is_programming;
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always @(posedge clk) begin
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prog_we <= 0;
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if (rx_done) begin
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// byte nuevo
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timeout_counter <= 0;
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is_programming <= 1;
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// little-endian
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prog_data <= {rx_byte, prog_data[31:8]};
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if (byte_count == 3) begin
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byte_count <= 0;
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prog_we <= 1; // 32b han llegado, escribimos
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end else begin
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byte_count <= byte_count + 1;
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end
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end else begin
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if (prog_we) begin
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prog_addr <= prog_addr + 4;
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end
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if (is_programming) begin
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if (timeout_counter == TIMEOUT_LIMIT) begin
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is_programming <= 0; // timeout excedido, soltamos CPU
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prog_addr <= 0; // reset al puntero
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byte_count <= 0;
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end else begin
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timeout_counter <= timeout_counter + 1;
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end
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end
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end
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end
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endmodule |