89 lines
2.4 KiB
Verilog
89 lines
2.4 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: nope
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// Engineer: Jose
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//
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// Create Date: 03/03/2026 03:02:49 AM
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// Design Name: UART TX Module
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// Module Name: uart_tx
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// Project Name: riscv-ac
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// Target Devices: Artix 7
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// Tool Versions: 2025.2
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// Description: Allows UART transmission
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//
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// Dependencies:
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//
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// Revision: 1.0
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module uart_tx (
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input wire clk,
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input wire [7:0] data_in,
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input wire tx_en,
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output reg tx = 1
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);
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// 12e6 / 115200 = 104 ciclos
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localparam CLKS_PER_BIT = 868; // 104;
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localparam S_IDLE = 2'b00;
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localparam S_START = 2'b01;
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localparam S_DATA = 2'b10;
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localparam S_STOP = 2'b11;
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reg [1:0] state = S_IDLE;
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reg [15:0] clk_count = 0;
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reg [2:0] bit_index = 0;
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reg [7:0] tx_data = 0;
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always @(posedge clk) begin
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case (state)
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S_IDLE: begin
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tx <= 1;
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clk_count <= 0;
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bit_index <= 0;
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if (tx_en) begin
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tx_data <= data_in;
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state <= S_START;
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end
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end
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S_START: begin
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tx <= 0;
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if (clk_count < CLKS_PER_BIT - 1) begin
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clk_count <= clk_count + 1;
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end else begin
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clk_count <= 0;
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state <= S_DATA;
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end
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end
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S_DATA: begin
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tx <= tx_data[bit_index];
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if (clk_count < CLKS_PER_BIT - 1) begin
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clk_count <= clk_count + 1;
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end else begin
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clk_count <= 0;
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if (bit_index == 7) begin
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state <= S_STOP;
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end else begin
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bit_index <= bit_index + 1;
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end
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end
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end
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S_STOP: begin
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tx <= 1;
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if (clk_count < CLKS_PER_BIT - 1) begin
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clk_count <= clk_count + 1;
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end else begin
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state <= S_IDLE;
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end
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end
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endcase
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end
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endmodule |