47 lines
1013 B
Verilog
47 lines
1013 B
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: nope
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// Engineer: Jose
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//
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// Create Date: 02/20/2026 09:21:52 AM
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// Design Name: Register File
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// Module Name: regfile
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// Project Name: riscv-ac
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// Target Devices: Artix 7
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// Tool Versions: 2025.2
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// Description: Stores temporal values
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//
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// Dependencies:
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//
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// Revision: 1.0
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module regfile(
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input clk, regwrite,
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input [4:0] rs1, rs2, rd,
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input [31:0] write_data,
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output [31:0] read_data_1, read_data_2
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);
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reg [31:0] regs[0:31];
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integer i;
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initial begin
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for (i = 0; i < 32; i = i + 1) begin
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regs[i] = 32'b0;
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end
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end
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assign read_data_1 = (rs1 == 0) ? 0 : regs[rs1];
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assign read_data_2 = (rs2 == 0) ? 0 : regs[rs2];
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always @(posedge clk) begin
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if (regwrite && rd != 0) regs[rd] <= write_data;
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end
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endmodule
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