51 lines
1.2 KiB
Verilog
51 lines
1.2 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: nope
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// Engineer: Jose
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//
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// Create Date: 02/20/2026 09:21:52 AM
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// Design Name: IF/ID register
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// Module Name: if_id
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// Project Name: riscv-ac
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// Target Devices: Artix 7
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// Tool Versions: 2025.2
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// Description: Register between IF/ID stages
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//
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// Dependencies:
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//
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// Revision: 1.0
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module if_id (
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input clk,
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input rst,
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input en,
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input clr,
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input [31:0] pc_in,
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input [31:0] pc4_in,
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input [31:0] inst_in,
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output reg [31:0] pc_out,
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output reg [31:0] pc4_out,
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output reg [31:0] inst_out
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);
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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pc_out <= 32'b0;
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pc4_out <= 32'b0;
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inst_out <= 32'b0;
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end else if (clr) begin
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pc_out <= 32'b0;
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pc4_out <= 32'b0;
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inst_out <= 32'b0;
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end else if (en) begin
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pc_out <= pc_in;
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pc4_out <= pc4_in;
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inst_out <= inst_in;
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end
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end
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endmodule |