Gallardo7761/riscv-ac
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refactor: renamed all signals for consistency

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This commit is contained in:
Jose
2026-03-02 23:34:31 +01:00
parent e7cd451e7e
commit 98f948ab18
36 changed files with 58 additions and 58 deletions
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12
riscv-ac.srcs/sources_1/new/top.v
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@@ -22,12 +22,12 @@ module top (
.clk(clk),
.rst(rst),
.next_pc(pc_stall),
.imem_addr(npc_IF)
.pc_out(npc_IF)
);
imem u_imem (
.clk(clk), .address(npc_IF), .we(1'b0),
.write_data(32'b0), .write_addr(8'b0), .instruction(ir_IF)
.write_data(32'b0), .write_addr(8'b0), .inst_out(ir_IF)
);
// ==========================================
@@ -37,8 +37,8 @@ module top (
if_id u_if_id (
.clk(clk), .rst(rst), .en(IF_ID_En), .clr(IF_ID_Clr),
.npc_in(npc_IF), .pc4_in(pc4_IF), .ir_in(ir_IF),
.npc_out(npc_ID), .pc4_out(pc4_ID), .ir_out(ir_ID)
.pc_in(npc_IF), .pc4_in(pc4_IF), .inst_in(ir_IF),
.pc_out(npc_ID), .pc4_out(pc4_ID), .inst_out(ir_ID)
);
// ==========================================
@@ -70,7 +70,7 @@ module top (
);
imm_gen u_imm_gen (
.instr(ir_ID), .imm_out(imm_ID)
.inst_in(ir_ID), .imm_out(imm_ID)
);
wire [1:0] ID_ForwardA, ID_ForwardB;
@@ -164,7 +164,7 @@ module top (
wire [31:0] mem_data_ME;
dmem u_dmem (
.clk(clk), .we(we_mem_ME), .address(alu_res_ME),
.write_data(regB_ME), .read_data(mem_data_ME)
.write_data(regB_ME), .mem_data_out(mem_data_ME)
);
wire [31:0] alu_res_WB, mem_data_WB, pc4_WB;