diff --git a/riscv-ac.sim/sim_1/behav/xsim/compile.sh b/riscv-ac.sim/sim_1/behav/xsim/compile.sh index b388302..d93bf08 100755 --- a/riscv-ac.sim/sim_1/behav/xsim/compile.sh +++ b/riscv-ac.sim/sim_1/behav/xsim/compile.sh @@ -6,7 +6,7 @@ # Simulator : AMD Vivado Simulator # Description : Script for compiling the simulation design source files # -# Generated by Vivado on Mon Mar 02 22:22:56 CET 2026 +# Generated by Vivado on Mon Mar 02 23:30:40 CET 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/riscv-ac.sim/sim_1/behav/xsim/elaborate.sh b/riscv-ac.sim/sim_1/behav/xsim/elaborate.sh index a912f99..5b325c1 100755 --- a/riscv-ac.sim/sim_1/behav/xsim/elaborate.sh +++ b/riscv-ac.sim/sim_1/behav/xsim/elaborate.sh @@ -6,7 +6,7 @@ # Simulator : AMD Vivado Simulator # Description : Script for elaborating the compiled design # -# Generated by Vivado on Mon Mar 02 22:22:58 CET 2026 +# Generated by Vivado on Mon Mar 02 23:30:41 CET 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/riscv-ac.sim/sim_1/behav/xsim/simulate.sh b/riscv-ac.sim/sim_1/behav/xsim/simulate.sh index 782e214..2bd0207 100755 --- a/riscv-ac.sim/sim_1/behav/xsim/simulate.sh +++ b/riscv-ac.sim/sim_1/behav/xsim/simulate.sh @@ -6,7 +6,7 @@ # Simulator : AMD Vivado Simulator # Description : Script for simulating the design by launching the simulator # -# Generated by Vivado on Mon Mar 02 22:16:52 CET 2026 +# Generated by Vivado on Mon Mar 02 23:30:42 CET 2026 # SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 # # Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. diff --git a/riscv-ac.sim/sim_1/behav/xsim/tb_top_behav.wdb b/riscv-ac.sim/sim_1/behav/xsim/tb_top_behav.wdb index 95b798b..e14a2cb 100644 Binary files a/riscv-ac.sim/sim_1/behav/xsim/tb_top_behav.wdb and b/riscv-ac.sim/sim_1/behav/xsim/tb_top_behav.wdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/obj/xsim_0.lnx64.o b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/obj/xsim_0.lnx64.o index 37ddb81..eeca82b 100644 Binary files a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/obj/xsim_0.lnx64.o and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/obj/xsim_0.lnx64.o differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.dbg b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.dbg index d7a88f0..5e8e182 100644 Binary files a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.dbg and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.dbg differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.mem b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.mem index 1806ff8..72de886 100644 Binary files a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.mem and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.mem differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.rlx b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.rlx index 5e00684..1cccd46 100644 --- a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.rlx +++ b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.rlx @@ -1,6 +1,6 @@ { - crc : 1048859293793588504 , + crc : 5732162227090726530 , ccp_crc : 0 , cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_top_behav xil_defaultlib.tb_top xil_defaultlib.glbl" , buildDate : "Nov 14 2025" , diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.rtti 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a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/id_ex.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/id_ex.sdb index f01e2c4..963d5ad 100644 Binary files a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/id_ex.sdb and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/id_ex.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/if_id.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/if_id.sdb index 835d2f8..e948bc6 100644 Binary files a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/if_id.sdb and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/if_id.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/imem.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/imem.sdb index d385a6c..fa2b35c 100644 Binary files a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/imem.sdb and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/imem.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/imm_gen.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/imm_gen.sdb index 505461a..87ec1be 100644 Binary files a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/imm_gen.sdb and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/imm_gen.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/me_wb.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/me_wb.sdb index 82e8b99..79c8222 100644 Binary files a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/me_wb.sdb and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/me_wb.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pc.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pc.sdb index 694fb9a..92582d2 100644 Binary files a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pc.sdb and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pc.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/regfile.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/regfile.sdb index bbb8c2f..be5532a 100644 Binary files a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/regfile.sdb and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/regfile.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_top.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_top.sdb index 7ac098f..e91c0b0 100644 Binary files a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_top.sdb and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_top.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/top.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/top.sdb index 1cea5ad..6ccbee6 100644 Binary files a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/top.sdb and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/top.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx index c5d7a2b..ba3c676 100644 --- a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx +++ b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -4,14 +4,14 @@ Nov 14 2025 12:36:23 /home/jomaa/git/riscv-ac/riscv-ac.sim/sim_1/behav/xsim/glbl.v,1756381829,verilog,,,,glbl,,,,,,,, /home/jomaa/git/riscv-ac/riscv-ac.srcs/sim_1/new/tb_top.v,1772486573,verilog,,,,tb_top,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, -/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/alu.v,1772483312,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/control.v,,alu,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, -/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/control.v,1772483371,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/dmem.v,,control,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, -/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/dmem.v,1772485582,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/ex_me.v,,dmem,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, -/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/ex_me.v,1772468735,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/forwarding.v,,ex_me,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, +/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/alu.v,1772490502,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/control.v,,alu,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, +/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/control.v,1772486779,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/dmem.v,,control,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, +/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/dmem.v,1772490163,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/ex_me.v,,dmem,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, +/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/ex_me.v,1772490593,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/forwarding.v,,ex_me,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/forwarding.v,1772467332,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/hazard.v,,forwarding,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/hazard.v,1772467244,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/id_ex.v,,hazard,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, -/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/id_ex.v,1772472446,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/if_id.v,,id_ex,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, -/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/if_id.v,1772468688,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imem.v,,if_id,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, +/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/id_ex.v,1772490462,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/if_id.v,,id_ex,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, +/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/if_id.v,1772490110,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imem.v,,if_id,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imem.v,1772485445,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imm_gen.v,,imem,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imm_gen.v,1772470571,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/me_wb.v,,imm_gen,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, /home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/me_wb.v,1772468767,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/pc.v,,me_wb,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, diff --git a/riscv-ac.srcs/sources_1/new/alu.v b/riscv-ac.srcs/sources_1/new/alu.v index a7257b0..72cb11c 100644 --- a/riscv-ac.srcs/sources_1/new/alu.v +++ b/riscv-ac.srcs/sources_1/new/alu.v @@ -29,18 +29,18 @@ module alu( always @(*) begin case(sel) - 4'b0000: R = A + B; // add - 4'b0001: R = A - B; // sub - 4'b0010: R = A & B; // and - 4'b0011: R = A | B; // or - 4'b0100: R = A ^ B; // xor - 4'b0101: R = A << B[4:0]; // sll - 4'b0110: R = A >> B[4:0]; // srl - 4'b0111: R = ($signed(A) < $signed(B)) ? 1 : 0; // slt (shift if less than signed) - 4'b1000: R = (A < B) ? 1 : 0; // sltu (shift if less than unsigned) - 4'b1001: R = $signed(A) >>> B[4:0]; // sra (shift right arithmetic) - 4'b1010: R = 32'b0; // nop - default: R = 32'b0; // default: nop + 4'b0000: R = A + B; // add + 4'b0001: R = A - B; // sub + 4'b0010: R = A & B; // and + 4'b0011: R = A | B; // or + 4'b0100: R = A ^ B; // xor + 4'b0101: R = A << B[4:0]; // sll + 4'b0110: R = A >> B[4:0]; // srl + 4'b0111: R = ($signed(A) < $signed(B)) ? 1 : 0; // slt + 4'b1000: R = (A < B) ? 1 : 0; // sltu + 4'b1001: R = $signed(A) >>> B[4:0]; // sra + 4'b1010: R = 32'b0; // nop + default: R = 32'b0; // default: nop endcase end diff --git a/riscv-ac.srcs/sources_1/new/dmem.v b/riscv-ac.srcs/sources_1/new/dmem.v index 06ae330..9ec9e9d 100644 --- a/riscv-ac.srcs/sources_1/new/dmem.v +++ b/riscv-ac.srcs/sources_1/new/dmem.v @@ -25,11 +25,11 @@ module dmem( input we, input [31:0] address, input [31:0] write_data, - output [31:0] read_data + output [31:0] mem_data_out ); reg [31:0] memory[0:255]; -reg [31:0] data; +reg [31:0] data_reg; integer i; initial begin @@ -41,9 +41,9 @@ end always @(posedge clk) begin if (we) memory[address[9:2]] <= write_data; - data <= memory[address[9:2]]; + data_reg <= memory[address[9:2]]; end -assign read_data = data; +assign mem_data_out = data_reg; endmodule \ No newline at end of file diff --git a/riscv-ac.srcs/sources_1/new/id_ex.v b/riscv-ac.srcs/sources_1/new/id_ex.v index 2d99b23..68a7789 100644 --- a/riscv-ac.srcs/sources_1/new/id_ex.v +++ b/riscv-ac.srcs/sources_1/new/id_ex.v @@ -30,7 +30,7 @@ module id_ex ( output reg we_reg_out, we_mem_out, mem_to_reg_out, alu_src_out, branch_out, jump_out, output reg [3:0] alu_op_out, - // PC4, A, B, C, Rd + // PC4, A, B, Inmediato, Regs input [31:0] pc4_in, regA_in, regB_in, regC_in, input [4:0] rs1_in, rs2_in, rd_in, diff --git a/riscv-ac.srcs/sources_1/new/if_id.v b/riscv-ac.srcs/sources_1/new/if_id.v index a54ab48..e87c184 100644 --- a/riscv-ac.srcs/sources_1/new/if_id.v +++ b/riscv-ac.srcs/sources_1/new/if_id.v @@ -25,27 +25,27 @@ module if_id ( input rst, input en, input clr, - input [31:0] npc_in, + input [31:0] pc_in, input [31:0] pc4_in, - input [31:0] ir_in, - output reg [31:0] npc_out, + input [31:0] inst_in, + output reg [31:0] pc_out, output reg [31:0] pc4_out, - output reg [31:0] ir_out + output reg [31:0] inst_out ); always @(posedge clk or posedge rst) begin if (rst) begin - npc_out <= 32'b0; + pc_out <= 32'b0; pc4_out <= 32'b0; - ir_out <= 32'b0; + inst_out <= 32'b0; end else if (clr) begin - npc_out <= 32'b0; + pc_out <= 32'b0; pc4_out <= 32'b0; - ir_out <= 32'b0; + inst_out <= 32'b0; end else if (en) begin - npc_out <= npc_in; + pc_out <= pc_in; pc4_out <= pc4_in; - ir_out <= ir_in; + inst_out <= inst_in; end end endmodule \ No newline at end of file diff --git a/riscv-ac.srcs/sources_1/new/imem.v b/riscv-ac.srcs/sources_1/new/imem.v index 1fba927..7bc58aa 100644 --- a/riscv-ac.srcs/sources_1/new/imem.v +++ b/riscv-ac.srcs/sources_1/new/imem.v @@ -25,11 +25,11 @@ module imem( input we, input [31:0] write_data, input [7:0] write_addr, - output [31:0] instruction + output [31:0] inst_out ); reg [31:0] memory[0:255]; -reg [31:0] ir; +reg [31:0] inst_reg; integer i; initial begin @@ -41,9 +41,9 @@ end always @(posedge clk) begin if(we) memory[write_addr] <= write_data; - ir <= memory[address[9:2]]; + inst_reg <= memory[address[9:2]]; end -assign instruction = ir; +assign inst_out = inst_reg; endmodule diff --git a/riscv-ac.srcs/sources_1/new/imm_gen.v b/riscv-ac.srcs/sources_1/new/imm_gen.v index 2be97c0..399932c 100644 --- a/riscv-ac.srcs/sources_1/new/imm_gen.v +++ b/riscv-ac.srcs/sources_1/new/imm_gen.v @@ -20,34 +20,34 @@ ////////////////////////////////////////////////////////////////////////////////// module imm_gen( - input [31:0] instr, + input [31:0] inst_in, output reg [31:0] imm_out ); always @(*) begin - case(instr[6:0]) + case(inst_in[6:0]) // Formato I 7'b0010011, 7'b0000011, 7'b1100111: - imm_out = {{20{instr[31]}}, instr[31:20]}; + imm_out = {{20{inst_in[31]}}, inst_in[31:20]}; // Formato S 7'b0100011: - imm_out = {{20{instr[31]}}, instr[31:25], instr[11:7]}; + imm_out = {{20{inst_in[31]}}, inst_in[31:25], inst_in[11:7]}; // Formato B 7'b1100011: - imm_out = {{19{instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0}; + imm_out = {{19{inst_in[31]}}, inst_in[31], inst_in[7], inst_in[30:25], inst_in[11:8], 1'b0}; // Formato J 7'b1101111: - imm_out = {{11{instr[31]}}, instr[31], instr[19:12], instr[20], instr[30:21], 1'b0}; + imm_out = {{11{inst_in[31]}}, inst_in[31], inst_in[19:12], inst_in[20], inst_in[30:21], 1'b0}; // Formato U 7'b0110111, 7'b0010111: - imm_out = {instr[31:12], 12'b0}; + imm_out = {inst_in[31:12], 12'b0}; default: imm_out = 32'b0; diff --git a/riscv-ac.srcs/sources_1/new/pc.v b/riscv-ac.srcs/sources_1/new/pc.v index c42e336..0774c38 100644 --- a/riscv-ac.srcs/sources_1/new/pc.v +++ b/riscv-ac.srcs/sources_1/new/pc.v @@ -23,12 +23,12 @@ module pc( input clk, rst, input [31:0] next_pc, - output reg [31:0] imem_addr + output reg [31:0] pc_out ); always @(posedge clk or posedge rst) begin - if (rst) imem_addr <= 0; - else imem_addr <= next_pc; + if (rst) pc_out <= 0; + else pc_out <= next_pc; end endmodule diff --git a/riscv-ac.srcs/sources_1/new/top.v b/riscv-ac.srcs/sources_1/new/top.v index fa8a752..3efa593 100644 --- a/riscv-ac.srcs/sources_1/new/top.v +++ b/riscv-ac.srcs/sources_1/new/top.v @@ -22,12 +22,12 @@ module top ( .clk(clk), .rst(rst), .next_pc(pc_stall), - .imem_addr(npc_IF) + .pc_out(npc_IF) ); imem u_imem ( .clk(clk), .address(npc_IF), .we(1'b0), - .write_data(32'b0), .write_addr(8'b0), .instruction(ir_IF) + .write_data(32'b0), .write_addr(8'b0), .inst_out(ir_IF) ); // ========================================== @@ -37,8 +37,8 @@ module top ( if_id u_if_id ( .clk(clk), .rst(rst), .en(IF_ID_En), .clr(IF_ID_Clr), - .npc_in(npc_IF), .pc4_in(pc4_IF), .ir_in(ir_IF), - .npc_out(npc_ID), .pc4_out(pc4_ID), .ir_out(ir_ID) + .pc_in(npc_IF), .pc4_in(pc4_IF), .inst_in(ir_IF), + .pc_out(npc_ID), .pc4_out(pc4_ID), .inst_out(ir_ID) ); // ========================================== @@ -70,7 +70,7 @@ module top ( ); imm_gen u_imm_gen ( - .instr(ir_ID), .imm_out(imm_ID) + .inst_in(ir_ID), .imm_out(imm_ID) ); wire [1:0] ID_ForwardA, ID_ForwardB; @@ -164,7 +164,7 @@ module top ( wire [31:0] mem_data_ME; dmem u_dmem ( .clk(clk), .we(we_mem_ME), .address(alu_res_ME), - .write_data(regB_ME), .read_data(mem_data_ME) + .write_data(regB_ME), .mem_data_out(mem_data_ME) ); wire [31:0] alu_res_WB, mem_data_WB, pc4_WB; diff --git a/riscv-ac.xpr b/riscv-ac.xpr index 0157eac..0b30c65 100644 --- a/riscv-ac.xpr +++ b/riscv-ac.xpr @@ -61,7 +61,7 @@