refactor: renamed all signals for consistency

2026-03-02 23:34:31 +01:00
parent e7cd451e7e
commit 98f948ab18
36 changed files with 58 additions and 58 deletions
--- a/riscv-ac.srcs/sources_1/new/pc.v
+++ b/riscv-ac.srcs/sources_1/new/pc.v
@@ -23,12 +23,12 @@
 module pc(
    input clk, rst,
    input [31:0] next_pc,
-    output reg [31:0] imem_addr
+    output reg [31:0] pc_out
 );

 always @(posedge clk or posedge rst) begin
-    if (rst) imem_addr <= 0; 
-    else imem_addr <= next_pc;
+    if (rst) pc_out <= 0; 
+    else pc_out <= next_pc;
 end

 endmodule