refactor: renamed all signals for consistency

riscv-ac.srcs/sources_1/new/imm_gen.v

@@ -20,34 +20,34 @@
 //////////////////////////////////////////////////////////////////////////////////
 
 module imm_gen(
-    input  [31:0] instr,
+    input  [31:0] inst_in,
     output reg [31:0] imm_out
 );
 
 always @(*) begin 
-    case(instr[6:0]) 
+    case(inst_in[6:0]) 
         // Formato I
         7'b0010011, 
         7'b0000011,
         7'b1100111:
-            imm_out = {{20{instr[31]}}, instr[31:20]};
+            imm_out = {{20{inst_in[31]}}, inst_in[31:20]};
 
         // Formato S
         7'b0100011:
-            imm_out = {{20{instr[31]}}, instr[31:25], instr[11:7]};
+            imm_out = {{20{inst_in[31]}}, inst_in[31:25], inst_in[11:7]};
 
         // Formato B
         7'b1100011:
-            imm_out = {{19{instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0};
+            imm_out = {{19{inst_in[31]}}, inst_in[31], inst_in[7], inst_in[30:25], inst_in[11:8], 1'b0};
 
         // Formato J
         7'b1101111:
-            imm_out = {{11{instr[31]}}, instr[31], instr[19:12], instr[20], instr[30:21], 1'b0};
+            imm_out = {{11{inst_in[31]}}, inst_in[31], inst_in[19:12], inst_in[20], inst_in[30:21], 1'b0};
 
         // Formato U
         7'b0110111, 
         7'b0010111:
-            imm_out = {instr[31:12], 12'b0};
+            imm_out = {inst_in[31:12], 12'b0};
 
         default:
             imm_out = 32'b0;