refactor: renamed all signals for consistency

riscv-ac.srcs/sources_1/new/imem.v

@@ -25,11 +25,11 @@ module imem(
     input we,
     input [31:0] write_data,
     input [7:0] write_addr,
-    output [31:0] instruction
+    output [31:0] inst_out
 );
 
 reg [31:0] memory[0:255];
-reg [31:0] ir;
+reg [31:0] inst_reg;
 
 integer i;
 initial begin
@@ -41,9 +41,9 @@ end
 always @(posedge clk) begin
     if(we)
         memory[write_addr] <= write_data;
-    ir <= memory[address[9:2]];
+    inst_reg <= memory[address[9:2]];
 end
 
-assign instruction = ir;
+assign inst_out = inst_reg;
 
 endmodule