refactor: renamed all signals for consistency

riscv-ac.srcs/sources_1/new/if_id.v

@@ -25,27 +25,27 @@ module if_id (
     input rst,
     input en,
     input clr,
-    input [31:0] npc_in,
+    input [31:0] pc_in,
     input [31:0] pc4_in,
-    input [31:0] ir_in,
-    output reg [31:0] npc_out,
+    input [31:0] inst_in,
+    output reg [31:0] pc_out,
     output reg [31:0] pc4_out,
-    output reg [31:0] ir_out
+    output reg [31:0] inst_out
 );
 
     always @(posedge clk or posedge rst) begin
         if (rst) begin
-            npc_out <= 32'b0;
+            pc_out <= 32'b0;
             pc4_out <= 32'b0;
-            ir_out  <= 32'b0;
+            inst_out  <= 32'b0;
         end else if (clr) begin
-            npc_out <= 32'b0;
+            pc_out <= 32'b0;
             pc4_out <= 32'b0;
-            ir_out  <= 32'b0; 
+            inst_out  <= 32'b0; 
         end else if (en) begin
-            npc_out <= npc_in;
+            pc_out <= pc_in;
             pc4_out <= pc4_in;
-            ir_out  <= ir_in;
+            inst_out  <= inst_in;
         end
     end
 endmodule