refactor: renamed all signals for consistency

2026-03-02 23:34:31 +01:00
parent e7cd451e7e
commit 98f948ab18
36 changed files with 58 additions and 58 deletions
--- a/riscv-ac.srcs/sources_1/new/id_ex.v
+++ b/riscv-ac.srcs/sources_1/new/id_ex.v
@@ -30,7 +30,7 @@ module id_ex (
    output reg we_reg_out, we_mem_out, mem_to_reg_out, alu_src_out, branch_out, jump_out,
    output reg [3:0] alu_op_out,

-    // PC4, A, B, C, Rd
+    // PC4, A, B, Inmediato, Regs
    input [31:0] pc4_in, regA_in, regB_in, regC_in,
    input [4:0] rs1_in, rs2_in, rd_in,