refactor: renamed all signals for consistency

riscv-ac.srcs/sources_1/new/dmem.v

@@ -25,11 +25,11 @@ module dmem(
     input we,
     input [31:0] address,
     input [31:0] write_data,
-    output [31:0] read_data
+    output [31:0] mem_data_out
 );
 
 reg [31:0] memory[0:255];
-reg [31:0] data;
+reg [31:0] data_reg;
 
 integer i;
 initial begin
@@ -41,9 +41,9 @@ end
 always @(posedge clk) begin
     if (we)
         memory[address[9:2]] <= write_data;
-    data <= memory[address[9:2]];
+    data_reg <= memory[address[9:2]];
 end
 
-assign read_data = data;
+assign mem_data_out = data_reg;
 
 endmodule