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refactor: renamed all signals for consistency

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Jose
2026-03-02 23:34:31 +01:00
parent e7cd451e7e
commit 98f948ab18
36 changed files with 58 additions and 58 deletions
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24
riscv-ac.srcs/sources_1/new/alu.v
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@@ -29,18 +29,18 @@ module alu(
always @(*) begin
case(sel)
4'b0000: R = A + B; // add
4'b0001: R = A - B; // sub
4'b0010: R = A & B; // and
4'b0011: R = A | B; // or
4'b0100: R = A ^ B; // xor
4'b0101: R = A << B[4:0]; // sll
4'b0110: R = A >> B[4:0]; // srl
4'b0111: R = ($signed(A) < $signed(B)) ? 1 : 0; // slt (shift if less than signed)
4'b1000: R = (A < B) ? 1 : 0; // sltu (shift if less than unsigned)
4'b1001: R = $signed(A) >>> B[4:0]; // sra (shift right arithmetic)
4'b1010: R = 32'b0; // nop
default: R = 32'b0; // default: nop
4'b0000: R = A + B; // add
4'b0001: R = A - B; // sub
4'b0010: R = A & B; // and
4'b0011: R = A | B; // or
4'b0100: R = A ^ B; // xor
4'b0101: R = A << B[4:0]; // sll
4'b0110: R = A >> B[4:0]; // srl
4'b0111: R = ($signed(A) < $signed(B)) ? 1 : 0; // slt
4'b1000: R = (A < B) ? 1 : 0; // sltu
4'b1001: R = $signed(A) >>> B[4:0]; // sra
4'b1010: R = 32'b0; // nop
default: R = 32'b0; // default: nop
endcase
end