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refactor: renamed all signals for consistency

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This commit is contained in:
Jose
2026-03-02 23:34:31 +01:00
parent e7cd451e7e
commit 98f948ab18
36 changed files with 58 additions and 58 deletions
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24
riscv-ac.srcs/sources_1/new/alu.v
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@@ -29,18 +29,18 @@ module alu(
always @(*) begin
case(sel)
4'b0000: R = A + B; // add
4'b0001: R = A - B; // sub
4'b0010: R = A & B; // and
4'b0011: R = A | B; // or
4'b0100: R = A ^ B; // xor
4'b0101: R = A << B[4:0]; // sll
4'b0110: R = A >> B[4:0]; // srl
4'b0111: R = ($signed(A) < $signed(B)) ? 1 : 0; // slt (shift if less than signed)
4'b1000: R = (A < B) ? 1 : 0; // sltu (shift if less than unsigned)
4'b1001: R = $signed(A) >>> B[4:0]; // sra (shift right arithmetic)
4'b1010: R = 32'b0; // nop
default: R = 32'b0; // default: nop
4'b0000: R = A + B; // add
4'b0001: R = A - B; // sub
4'b0010: R = A & B; // and
4'b0011: R = A | B; // or
4'b0100: R = A ^ B; // xor
4'b0101: R = A << B[4:0]; // sll
4'b0110: R = A >> B[4:0]; // srl
4'b0111: R = ($signed(A) < $signed(B)) ? 1 : 0; // slt
4'b1000: R = (A < B) ? 1 : 0; // sltu
4'b1001: R = $signed(A) >>> B[4:0]; // sra
4'b1010: R = 32'b0; // nop
default: R = 32'b0; // default: nop
endcase
end

8
riscv-ac.srcs/sources_1/new/dmem.v
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@@ -25,11 +25,11 @@ module dmem(
input we,
input [31:0] address,
input [31:0] write_data,
output [31:0] read_data
output [31:0] mem_data_out
);
reg [31:0] memory[0:255];
reg [31:0] data;
reg [31:0] data_reg;
integer i;
initial begin
@@ -41,9 +41,9 @@ end
always @(posedge clk) begin
if (we)
memory[address[9:2]] <= write_data;
data <= memory[address[9:2]];
data_reg <= memory[address[9:2]];
end
assign read_data = data;
assign mem_data_out = data_reg;
endmodule

2
riscv-ac.srcs/sources_1/new/id_ex.v
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@@ -30,7 +30,7 @@ module id_ex (
output reg we_reg_out, we_mem_out, mem_to_reg_out, alu_src_out, branch_out, jump_out,
output reg [3:0] alu_op_out,
// PC4, A, B, C, Rd
// PC4, A, B, Inmediato, Regs
input [31:0] pc4_in, regA_in, regB_in, regC_in,
input [4:0] rs1_in, rs2_in, rd_in,

20
riscv-ac.srcs/sources_1/new/if_id.v
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@@ -25,27 +25,27 @@ module if_id (
input rst,
input en,
input clr,
input [31:0] npc_in,
input [31:0] pc_in,
input [31:0] pc4_in,
input [31:0] ir_in,
output reg [31:0] npc_out,
input [31:0] inst_in,
output reg [31:0] pc_out,
output reg [31:0] pc4_out,
output reg [31:0] ir_out
output reg [31:0] inst_out
);
always @(posedge clk or posedge rst) begin
if (rst) begin
npc_out <= 32'b0;
pc_out <= 32'b0;
pc4_out <= 32'b0;
ir_out <= 32'b0;
inst_out <= 32'b0;
end else if (clr) begin
npc_out <= 32'b0;
pc_out <= 32'b0;
pc4_out <= 32'b0;
ir_out <= 32'b0;
inst_out <= 32'b0;
end else if (en) begin
npc_out <= npc_in;
pc_out <= pc_in;
pc4_out <= pc4_in;
ir_out <= ir_in;
inst_out <= inst_in;
end
end
endmodule

8
riscv-ac.srcs/sources_1/new/imem.v
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@@ -25,11 +25,11 @@ module imem(
input we,
input [31:0] write_data,
input [7:0] write_addr,
output [31:0] instruction
output [31:0] inst_out
);
reg [31:0] memory[0:255];
reg [31:0] ir;
reg [31:0] inst_reg;
integer i;
initial begin
@@ -41,9 +41,9 @@ end
always @(posedge clk) begin
if(we)
memory[write_addr] <= write_data;
ir <= memory[address[9:2]];
inst_reg <= memory[address[9:2]];
end
assign instruction = ir;
assign inst_out = inst_reg;
endmodule

14
riscv-ac.srcs/sources_1/new/imm_gen.v
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@@ -20,34 +20,34 @@
//////////////////////////////////////////////////////////////////////////////////
module imm_gen(
input [31:0] instr,
input [31:0] inst_in,
output reg [31:0] imm_out
);
always @(*) begin
case(instr[6:0])
case(inst_in[6:0])
// Formato I
7'b0010011,
7'b0000011,
7'b1100111:
imm_out = {{20{instr[31]}}, instr[31:20]};
imm_out = {{20{inst_in[31]}}, inst_in[31:20]};
// Formato S
7'b0100011:
imm_out = {{20{instr[31]}}, instr[31:25], instr[11:7]};
imm_out = {{20{inst_in[31]}}, inst_in[31:25], inst_in[11:7]};
// Formato B
7'b1100011:
imm_out = {{19{instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0};
imm_out = {{19{inst_in[31]}}, inst_in[31], inst_in[7], inst_in[30:25], inst_in[11:8], 1'b0};
// Formato J
7'b1101111:
imm_out = {{11{instr[31]}}, instr[31], instr[19:12], instr[20], instr[30:21], 1'b0};
imm_out = {{11{inst_in[31]}}, inst_in[31], inst_in[19:12], inst_in[20], inst_in[30:21], 1'b0};
// Formato U
7'b0110111,
7'b0010111:
imm_out = {instr[31:12], 12'b0};
imm_out = {inst_in[31:12], 12'b0};
default:
imm_out = 32'b0;

6
riscv-ac.srcs/sources_1/new/pc.v
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@@ -23,12 +23,12 @@
module pc(
input clk, rst,
input [31:0] next_pc,
output reg [31:0] imem_addr
output reg [31:0] pc_out
);
always @(posedge clk or posedge rst) begin
if (rst) imem_addr <= 0;
else imem_addr <= next_pc;
if (rst) pc_out <= 0;
else pc_out <= next_pc;
end
endmodule

12
riscv-ac.srcs/sources_1/new/top.v
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@@ -22,12 +22,12 @@ module top (
.clk(clk),
.rst(rst),
.next_pc(pc_stall),
.imem_addr(npc_IF)
.pc_out(npc_IF)
);
imem u_imem (
.clk(clk), .address(npc_IF), .we(1'b0),
.write_data(32'b0), .write_addr(8'b0), .instruction(ir_IF)
.write_data(32'b0), .write_addr(8'b0), .inst_out(ir_IF)
);
// ==========================================
@@ -37,8 +37,8 @@ module top (
if_id u_if_id (
.clk(clk), .rst(rst), .en(IF_ID_En), .clr(IF_ID_Clr),
.npc_in(npc_IF), .pc4_in(pc4_IF), .ir_in(ir_IF),
.npc_out(npc_ID), .pc4_out(pc4_ID), .ir_out(ir_ID)
.pc_in(npc_IF), .pc4_in(pc4_IF), .inst_in(ir_IF),
.pc_out(npc_ID), .pc4_out(pc4_ID), .inst_out(ir_ID)
);
// ==========================================
@@ -70,7 +70,7 @@ module top (
);
imm_gen u_imm_gen (
.instr(ir_ID), .imm_out(imm_ID)
.inst_in(ir_ID), .imm_out(imm_ID)
);
wire [1:0] ID_ForwardA, ID_ForwardB;
@@ -164,7 +164,7 @@ module top (
wire [31:0] mem_data_ME;
dmem u_dmem (
.clk(clk), .we(we_mem_ME), .address(alu_res_ME),
.write_data(regB_ME), .read_data(mem_data_ME)
.write_data(regB_ME), .mem_data_out(mem_data_ME)
);
wire [31:0] alu_res_WB, mem_data_WB, pc4_WB;