refactor: renamed all signals for consistency

riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx

@@ -4,14 +4,14 @@ Nov 14 2025
 12:36:23
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-/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/id_ex.v,1772472446,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/if_id.v,,id_ex,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
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