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refactor: renamed all signals for consistency

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Jose
2026-03-02 23:34:31 +01:00
parent e7cd451e7e
commit 98f948ab18
36 changed files with 58 additions and 58 deletions
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riscv-ac.sim/sim_1/behav/xsim/compile.sh
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@@ -6,7 +6,7 @@
# Simulator : AMD Vivado Simulator
# Description : Script for compiling the simulation design source files
#
# Generated by Vivado on Mon Mar 02 22:22:56 CET 2026
# Generated by Vivado on Mon Mar 02 23:30:40 CET 2026
# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
#
# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.