Initial commit

riscv-ac.srcs/sources_1/new/regfile.v

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+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 02/20/2026 09:21:52 AM
+// Design Name: 
+// Module Name: regfile
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module regfile(
+    input clk, regwrite,
+    input [4:0] rs1, rs2, rd,
+    input [31:0] write_data,
+    output [31:0] read_data_1, read_data_2 
+);
+
+reg [31:0] regs[0:31];
+
+assign read_data_1 = (rs1 == 0) ? 0 : regs[rs1];
+assign read_data_2 = (rs2 == 0) ? 0 : regs[rs2];
+
+always @(posedge clk) begin 
+    if (regwrite && rd != 0) regs[rd] <= write_data;
+end
+
+endmodule