Initial commit

riscv-ac.srcs/sources_1/new/imm_gen.v

@@ -0,0 +1,40 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 02/20/2026 09:21:52 AM
+// Design Name: 
+// Module Name: imm_gen
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module imm_gen(
+    input [31:0] instr,
+    output reg [31:0] imm_out
+);
+
+always @(*) begin 
+    case(instr[6:0]) 
+        7'b0010011,
+        7'b0000011:
+            imm_out = {{20{instr[31]}}, instr[31:20]};
+        7'b1101111:
+            imm_out = {{11{instr[31]}}, instr[31], instr[19:12], instr[20], instr[30:21], 1'b0};
+        default:
+            imm_out = 32'b0;
+    endcase
+end
+
+endmodule