307 lines
9.1 KiB
C
307 lines
9.1 KiB
C
/**
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******************************************************************************
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* @file l3gd20.h
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* @author MCD Application Team
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* @brief This file contains all the functions prototypes for the l3gd20.c driver.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) 2015 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __L3GD20_H
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#define __L3GD20_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "../Common/gyro.h"
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/** @addtogroup BSP
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* @{
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*/
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/** @addtogroup Components
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* @{
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*/
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/** @addtogroup L3GD20
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* @{
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*/
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/** @defgroup L3GD20_Exported_Constants
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* @{
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*/
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/******************************************************************************/
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/*************************** START REGISTER MAPPING **************************/
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/******************************************************************************/
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#define L3GD20_WHO_AM_I_ADDR 0x0F /* device identification register */
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#define L3GD20_CTRL_REG1_ADDR 0x20 /* Control register 1 */
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#define L3GD20_CTRL_REG2_ADDR 0x21 /* Control register 2 */
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#define L3GD20_CTRL_REG3_ADDR 0x22 /* Control register 3 */
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#define L3GD20_CTRL_REG4_ADDR 0x23 /* Control register 4 */
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#define L3GD20_CTRL_REG5_ADDR 0x24 /* Control register 5 */
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#define L3GD20_REFERENCE_REG_ADDR 0x25 /* Reference register */
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#define L3GD20_OUT_TEMP_ADDR 0x26 /* Out temp register */
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#define L3GD20_STATUS_REG_ADDR 0x27 /* Status register */
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#define L3GD20_OUT_X_L_ADDR 0x28 /* Output Register X */
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#define L3GD20_OUT_X_H_ADDR 0x29 /* Output Register X */
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#define L3GD20_OUT_Y_L_ADDR 0x2A /* Output Register Y */
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#define L3GD20_OUT_Y_H_ADDR 0x2B /* Output Register Y */
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#define L3GD20_OUT_Z_L_ADDR 0x2C /* Output Register Z */
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#define L3GD20_OUT_Z_H_ADDR 0x2D /* Output Register Z */
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#define L3GD20_FIFO_CTRL_REG_ADDR 0x2E /* Fifo control Register */
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#define L3GD20_FIFO_SRC_REG_ADDR 0x2F /* Fifo src Register */
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#define L3GD20_INT1_CFG_ADDR 0x30 /* Interrupt 1 configuration Register */
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#define L3GD20_INT1_SRC_ADDR 0x31 /* Interrupt 1 source Register */
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#define L3GD20_INT1_TSH_XH_ADDR 0x32 /* Interrupt 1 Threshold X register */
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#define L3GD20_INT1_TSH_XL_ADDR 0x33 /* Interrupt 1 Threshold X register */
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#define L3GD20_INT1_TSH_YH_ADDR 0x34 /* Interrupt 1 Threshold Y register */
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#define L3GD20_INT1_TSH_YL_ADDR 0x35 /* Interrupt 1 Threshold Y register */
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#define L3GD20_INT1_TSH_ZH_ADDR 0x36 /* Interrupt 1 Threshold Z register */
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#define L3GD20_INT1_TSH_ZL_ADDR 0x37 /* Interrupt 1 Threshold Z register */
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#define L3GD20_INT1_DURATION_ADDR 0x38 /* Interrupt 1 DURATION register */
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/******************************************************************************/
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/**************************** END REGISTER MAPPING ***************************/
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/******************************************************************************/
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#define I_AM_L3GD20 ((uint8_t)0xD4)
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#define I_AM_L3GD20_TR ((uint8_t)0xD5)
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/** @defgroup Power_Mode_selection
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* @{
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*/
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#define L3GD20_MODE_POWERDOWN ((uint8_t)0x00)
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#define L3GD20_MODE_ACTIVE ((uint8_t)0x08)
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/**
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* @}
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*/
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/** @defgroup OutPut_DataRate_Selection
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* @{
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*/
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#define L3GD20_OUTPUT_DATARATE_1 ((uint8_t)0x00)
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#define L3GD20_OUTPUT_DATARATE_2 ((uint8_t)0x40)
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#define L3GD20_OUTPUT_DATARATE_3 ((uint8_t)0x80)
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#define L3GD20_OUTPUT_DATARATE_4 ((uint8_t)0xC0)
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/**
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* @}
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*/
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/** @defgroup Axes_Selection
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* @{
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*/
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#define L3GD20_X_ENABLE ((uint8_t)0x02)
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#define L3GD20_Y_ENABLE ((uint8_t)0x01)
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#define L3GD20_Z_ENABLE ((uint8_t)0x04)
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#define L3GD20_AXES_ENABLE ((uint8_t)0x07)
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#define L3GD20_AXES_DISABLE ((uint8_t)0x00)
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/**
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* @}
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*/
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/** @defgroup Bandwidth_Selection
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* @{
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*/
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#define L3GD20_BANDWIDTH_1 ((uint8_t)0x00)
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#define L3GD20_BANDWIDTH_2 ((uint8_t)0x10)
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#define L3GD20_BANDWIDTH_3 ((uint8_t)0x20)
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#define L3GD20_BANDWIDTH_4 ((uint8_t)0x30)
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/**
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* @}
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*/
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/** @defgroup Full_Scale_Selection
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* @{
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*/
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#define L3GD20_FULLSCALE_250 ((uint8_t)0x00)
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#define L3GD20_FULLSCALE_500 ((uint8_t)0x10)
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#define L3GD20_FULLSCALE_2000 ((uint8_t)0x20)
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#define L3GD20_FULLSCALE_SELECTION ((uint8_t)0x30)
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/**
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* @}
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*/
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/** @defgroup Full_Scale_Sensitivity
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* @{
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*/
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#define L3GD20_SENSITIVITY_250DPS ((float)8.75f) /*!< gyroscope sensitivity with 250 dps full scale [DPS/LSB] */
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#define L3GD20_SENSITIVITY_500DPS ((float)17.50f) /*!< gyroscope sensitivity with 500 dps full scale [DPS/LSB] */
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#define L3GD20_SENSITIVITY_2000DPS ((float)70.00f) /*!< gyroscope sensitivity with 2000 dps full scale [DPS/LSB] */
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/**
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* @}
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*/
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/** @defgroup Block_Data_Update
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* @{
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*/
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#define L3GD20_BlockDataUpdate_Continous ((uint8_t)0x00)
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#define L3GD20_BlockDataUpdate_Single ((uint8_t)0x80)
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/**
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* @}
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*/
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/** @defgroup Endian_Data_selection
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* @{
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*/
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#define L3GD20_BLE_LSB ((uint8_t)0x00)
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#define L3GD20_BLE_MSB ((uint8_t)0x40)
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/**
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* @}
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*/
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/** @defgroup High_Pass_Filter_status
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* @{
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*/
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#define L3GD20_HIGHPASSFILTER_DISABLE ((uint8_t)0x00)
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#define L3GD20_HIGHPASSFILTER_ENABLE ((uint8_t)0x10)
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/**
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* @}
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*/
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/** @defgroup INT1_INT2_selection
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* @{
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*/
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#define L3GD20_INT1 ((uint8_t)0x00)
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#define L3GD20_INT2 ((uint8_t)0x01)
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/**
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* @}
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*/
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/** @defgroup INT1_Interrupt_status
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* @{
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*/
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#define L3GD20_INT1INTERRUPT_DISABLE ((uint8_t)0x00)
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#define L3GD20_INT1INTERRUPT_ENABLE ((uint8_t)0x80)
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/**
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* @}
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*/
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/** @defgroup INT2_Interrupt_status
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* @{
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*/
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#define L3GD20_INT2INTERRUPT_DISABLE ((uint8_t)0x00)
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#define L3GD20_INT2INTERRUPT_ENABLE ((uint8_t)0x08)
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/**
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* @}
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*/
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/** @defgroup INT1_Interrupt_ActiveEdge
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* @{
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*/
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#define L3GD20_INT1INTERRUPT_LOW_EDGE ((uint8_t)0x20)
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#define L3GD20_INT1INTERRUPT_HIGH_EDGE ((uint8_t)0x00)
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/**
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* @}
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*/
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/** @defgroup Boot_Mode_selection
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* @{
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*/
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#define L3GD20_BOOT_NORMALMODE ((uint8_t)0x00)
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#define L3GD20_BOOT_REBOOTMEMORY ((uint8_t)0x80)
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/**
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* @}
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*/
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/** @defgroup High_Pass_Filter_Mode
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* @{
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*/
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#define L3GD20_HPM_NORMAL_MODE_RES ((uint8_t)0x00)
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#define L3GD20_HPM_REF_SIGNAL ((uint8_t)0x10)
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#define L3GD20_HPM_NORMAL_MODE ((uint8_t)0x20)
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#define L3GD20_HPM_AUTORESET_INT ((uint8_t)0x30)
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/**
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* @}
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*/
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/** @defgroup High_Pass_CUT OFF_Frequency
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* @{
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*/
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#define L3GD20_HPFCF_0 0x00
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#define L3GD20_HPFCF_1 0x01
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#define L3GD20_HPFCF_2 0x02
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#define L3GD20_HPFCF_3 0x03
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#define L3GD20_HPFCF_4 0x04
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#define L3GD20_HPFCF_5 0x05
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#define L3GD20_HPFCF_6 0x06
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#define L3GD20_HPFCF_7 0x07
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#define L3GD20_HPFCF_8 0x08
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#define L3GD20_HPFCF_9 0x09
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/**
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* @}
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*/
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/**
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* @}
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*/
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/** @defgroup L3GD20_Exported_Functions
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* @{
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*/
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/* Sensor Configuration Functions */
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void L3GD20_Init(uint16_t InitStruct);
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void L3GD20_DeInit(void);
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void L3GD20_LowPower(uint16_t InitStruct);
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uint8_t L3GD20_ReadID(void);
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void L3GD20_RebootCmd(void);
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/* Interrupt Configuration Functions */
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void L3GD20_INT1InterruptConfig(uint16_t Int1Config);
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void L3GD20_EnableIT(uint8_t IntSel);
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void L3GD20_DisableIT(uint8_t IntSel);
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/* High Pass Filter Configuration Functions */
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void L3GD20_FilterConfig(uint8_t FilterStruct);
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void L3GD20_FilterCmd(uint8_t HighPassFilterState);
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void L3GD20_ReadXYZAngRate(float *pfData);
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uint8_t L3GD20_GetDataStatus(void);
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/* Gyroscope IO functions */
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void GYRO_IO_Init(void);
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void GYRO_IO_DeInit(void);
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void GYRO_IO_Write(uint8_t *pBuffer, uint8_t WriteAddr, uint16_t NumByteToWrite);
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void GYRO_IO_Read(uint8_t *pBuffer, uint8_t ReadAddr, uint16_t NumByteToRead);
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/* Gyroscope driver structure */
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extern GYRO_DrvTypeDef L3gd20Drv;
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __L3GD20_H */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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