20712 lines
790 KiB
Plaintext
Executable File
20712 lines
790 KiB
Plaintext
Executable File
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P3_SETR1.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 00000188 08000000 08000000 00001000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 00009104 08000190 08000190 00001190 2**4
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 0000041c 08009298 08009298 0000a298 2**3
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM.extab 00000000 080096b4 080096b4 0000b1e8 2**0
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CONTENTS, READONLY
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4 .ARM 00000008 080096b4 080096b4 0000a6b4 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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5 .preinit_array 00000000 080096bc 080096bc 0000b1e8 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 080096bc 080096bc 0000a6bc 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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7 .fini_array 00000004 080096c0 080096c0 0000a6c0 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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8 .data 000001e8 20000000 080096c4 0000b000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .bss 00000290 200001e8 080098ac 0000b1e8 2**2
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ALLOC
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10 ._user_heap_stack 00000600 20000478 080098ac 0000b478 2**0
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ALLOC
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11 .ARM.attributes 00000030 00000000 00000000 0000b1e8 2**0
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CONTENTS, READONLY
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12 .debug_info 00010c30 00000000 00000000 0000b218 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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13 .debug_abbrev 00002938 00000000 00000000 0001be48 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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14 .debug_aranges 00000e38 00000000 00000000 0001e780 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_rnglists 00000af2 00000000 00000000 0001f5b8 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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16 .debug_macro 00027508 00000000 00000000 000200aa 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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17 .debug_line 00011a61 00000000 00000000 000475b2 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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18 .debug_str 000eb848 00000000 00000000 00059013 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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19 .comment 00000043 00000000 00000000 0014485b 2**0
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CONTENTS, READONLY
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20 .debug_frame 00004b7c 00000000 00000000 001448a0 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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21 .debug_line_str 00000047 00000000 00000000 0014941c 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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08000190 <__do_global_dtors_aux>:
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8000190: b510 push {r4, lr}
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8000192: 4c05 ldr r4, [pc, #20] @ (80001a8 <__do_global_dtors_aux+0x18>)
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8000194: 7823 ldrb r3, [r4, #0]
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8000196: b933 cbnz r3, 80001a6 <__do_global_dtors_aux+0x16>
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8000198: 4b04 ldr r3, [pc, #16] @ (80001ac <__do_global_dtors_aux+0x1c>)
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800019a: b113 cbz r3, 80001a2 <__do_global_dtors_aux+0x12>
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800019c: 4804 ldr r0, [pc, #16] @ (80001b0 <__do_global_dtors_aux+0x20>)
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800019e: f3af 8000 nop.w
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80001a2: 2301 movs r3, #1
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80001a4: 7023 strb r3, [r4, #0]
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80001a6: bd10 pop {r4, pc}
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80001a8: 200001e8 .word 0x200001e8
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80001ac: 00000000 .word 0x00000000
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80001b0: 0800927c .word 0x0800927c
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080001b4 <frame_dummy>:
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80001b4: b508 push {r3, lr}
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80001b6: 4b03 ldr r3, [pc, #12] @ (80001c4 <frame_dummy+0x10>)
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80001b8: b11b cbz r3, 80001c2 <frame_dummy+0xe>
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80001ba: 4903 ldr r1, [pc, #12] @ (80001c8 <frame_dummy+0x14>)
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80001bc: 4803 ldr r0, [pc, #12] @ (80001cc <frame_dummy+0x18>)
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80001be: f3af 8000 nop.w
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80001c2: bd08 pop {r3, pc}
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80001c4: 00000000 .word 0x00000000
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80001c8: 200001ec .word 0x200001ec
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80001cc: 0800927c .word 0x0800927c
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080001d0 <memchr>:
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80001d0: f001 01ff and.w r1, r1, #255 @ 0xff
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80001d4: 2a10 cmp r2, #16
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80001d6: db2b blt.n 8000230 <memchr+0x60>
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80001d8: f010 0f07 tst.w r0, #7
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80001dc: d008 beq.n 80001f0 <memchr+0x20>
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80001de: f810 3b01 ldrb.w r3, [r0], #1
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80001e2: 3a01 subs r2, #1
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80001e4: 428b cmp r3, r1
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80001e6: d02d beq.n 8000244 <memchr+0x74>
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80001e8: f010 0f07 tst.w r0, #7
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80001ec: b342 cbz r2, 8000240 <memchr+0x70>
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80001ee: d1f6 bne.n 80001de <memchr+0xe>
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80001f0: b4f0 push {r4, r5, r6, r7}
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80001f2: ea41 2101 orr.w r1, r1, r1, lsl #8
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80001f6: ea41 4101 orr.w r1, r1, r1, lsl #16
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80001fa: f022 0407 bic.w r4, r2, #7
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80001fe: f07f 0700 mvns.w r7, #0
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8000202: 2300 movs r3, #0
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8000204: e8f0 5602 ldrd r5, r6, [r0], #8
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8000208: 3c08 subs r4, #8
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800020a: ea85 0501 eor.w r5, r5, r1
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800020e: ea86 0601 eor.w r6, r6, r1
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8000212: fa85 f547 uadd8 r5, r5, r7
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8000216: faa3 f587 sel r5, r3, r7
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800021a: fa86 f647 uadd8 r6, r6, r7
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800021e: faa5 f687 sel r6, r5, r7
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8000222: b98e cbnz r6, 8000248 <memchr+0x78>
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8000224: d1ee bne.n 8000204 <memchr+0x34>
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8000226: bcf0 pop {r4, r5, r6, r7}
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8000228: f001 01ff and.w r1, r1, #255 @ 0xff
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800022c: f002 0207 and.w r2, r2, #7
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8000230: b132 cbz r2, 8000240 <memchr+0x70>
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8000232: f810 3b01 ldrb.w r3, [r0], #1
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8000236: 3a01 subs r2, #1
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8000238: ea83 0301 eor.w r3, r3, r1
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800023c: b113 cbz r3, 8000244 <memchr+0x74>
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800023e: d1f8 bne.n 8000232 <memchr+0x62>
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8000240: 2000 movs r0, #0
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8000242: 4770 bx lr
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8000244: 3801 subs r0, #1
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8000246: 4770 bx lr
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8000248: 2d00 cmp r5, #0
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800024a: bf06 itte eq
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800024c: 4635 moveq r5, r6
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800024e: 3803 subeq r0, #3
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8000250: 3807 subne r0, #7
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8000252: f015 0f01 tst.w r5, #1
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8000256: d107 bne.n 8000268 <memchr+0x98>
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8000258: 3001 adds r0, #1
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800025a: f415 7f80 tst.w r5, #256 @ 0x100
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800025e: bf02 ittt eq
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8000260: 3001 addeq r0, #1
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8000262: f415 3fc0 tsteq.w r5, #98304 @ 0x18000
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8000266: 3001 addeq r0, #1
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8000268: bcf0 pop {r4, r5, r6, r7}
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800026a: 3801 subs r0, #1
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800026c: 4770 bx lr
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800026e: bf00 nop
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08000270 <strlen>:
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8000270: 4603 mov r3, r0
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8000272: f813 2b01 ldrb.w r2, [r3], #1
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8000276: 2a00 cmp r2, #0
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8000278: d1fb bne.n 8000272 <strlen+0x2>
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800027a: 1a18 subs r0, r3, r0
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800027c: 3801 subs r0, #1
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800027e: 4770 bx lr
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08000280 <__aeabi_drsub>:
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8000280: f081 4100 eor.w r1, r1, #2147483648 @ 0x80000000
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8000284: e002 b.n 800028c <__adddf3>
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8000286: bf00 nop
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08000288 <__aeabi_dsub>:
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8000288: f083 4300 eor.w r3, r3, #2147483648 @ 0x80000000
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0800028c <__adddf3>:
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800028c: b530 push {r4, r5, lr}
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800028e: ea4f 0441 mov.w r4, r1, lsl #1
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8000292: ea4f 0543 mov.w r5, r3, lsl #1
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8000296: ea94 0f05 teq r4, r5
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800029a: bf08 it eq
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800029c: ea90 0f02 teqeq r0, r2
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80002a0: bf1f itttt ne
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80002a2: ea54 0c00 orrsne.w ip, r4, r0
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80002a6: ea55 0c02 orrsne.w ip, r5, r2
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80002aa: ea7f 5c64 mvnsne.w ip, r4, asr #21
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80002ae: ea7f 5c65 mvnsne.w ip, r5, asr #21
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80002b2: f000 80e2 beq.w 800047a <__adddf3+0x1ee>
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80002b6: ea4f 5454 mov.w r4, r4, lsr #21
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80002ba: ebd4 5555 rsbs r5, r4, r5, lsr #21
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80002be: bfb8 it lt
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80002c0: 426d neglt r5, r5
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80002c2: dd0c ble.n 80002de <__adddf3+0x52>
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80002c4: 442c add r4, r5
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80002c6: ea80 0202 eor.w r2, r0, r2
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80002ca: ea81 0303 eor.w r3, r1, r3
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80002ce: ea82 0000 eor.w r0, r2, r0
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80002d2: ea83 0101 eor.w r1, r3, r1
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80002d6: ea80 0202 eor.w r2, r0, r2
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80002da: ea81 0303 eor.w r3, r1, r3
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80002de: 2d36 cmp r5, #54 @ 0x36
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80002e0: bf88 it hi
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80002e2: bd30 pophi {r4, r5, pc}
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80002e4: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
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80002e8: ea4f 3101 mov.w r1, r1, lsl #12
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80002ec: f44f 1c80 mov.w ip, #1048576 @ 0x100000
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80002f0: ea4c 3111 orr.w r1, ip, r1, lsr #12
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80002f4: d002 beq.n 80002fc <__adddf3+0x70>
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80002f6: 4240 negs r0, r0
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80002f8: eb61 0141 sbc.w r1, r1, r1, lsl #1
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80002fc: f013 4f00 tst.w r3, #2147483648 @ 0x80000000
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8000300: ea4f 3303 mov.w r3, r3, lsl #12
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8000304: ea4c 3313 orr.w r3, ip, r3, lsr #12
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8000308: d002 beq.n 8000310 <__adddf3+0x84>
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800030a: 4252 negs r2, r2
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800030c: eb63 0343 sbc.w r3, r3, r3, lsl #1
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8000310: ea94 0f05 teq r4, r5
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8000314: f000 80a7 beq.w 8000466 <__adddf3+0x1da>
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8000318: f1a4 0401 sub.w r4, r4, #1
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800031c: f1d5 0e20 rsbs lr, r5, #32
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8000320: db0d blt.n 800033e <__adddf3+0xb2>
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8000322: fa02 fc0e lsl.w ip, r2, lr
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8000326: fa22 f205 lsr.w r2, r2, r5
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800032a: 1880 adds r0, r0, r2
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800032c: f141 0100 adc.w r1, r1, #0
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8000330: fa03 f20e lsl.w r2, r3, lr
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8000334: 1880 adds r0, r0, r2
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8000336: fa43 f305 asr.w r3, r3, r5
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800033a: 4159 adcs r1, r3
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800033c: e00e b.n 800035c <__adddf3+0xd0>
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800033e: f1a5 0520 sub.w r5, r5, #32
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8000342: f10e 0e20 add.w lr, lr, #32
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8000346: 2a01 cmp r2, #1
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8000348: fa03 fc0e lsl.w ip, r3, lr
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800034c: bf28 it cs
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800034e: f04c 0c02 orrcs.w ip, ip, #2
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8000352: fa43 f305 asr.w r3, r3, r5
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8000356: 18c0 adds r0, r0, r3
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8000358: eb51 71e3 adcs.w r1, r1, r3, asr #31
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800035c: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
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8000360: d507 bpl.n 8000372 <__adddf3+0xe6>
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8000362: f04f 0e00 mov.w lr, #0
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8000366: f1dc 0c00 rsbs ip, ip, #0
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800036a: eb7e 0000 sbcs.w r0, lr, r0
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800036e: eb6e 0101 sbc.w r1, lr, r1
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8000372: f5b1 1f80 cmp.w r1, #1048576 @ 0x100000
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8000376: d31b bcc.n 80003b0 <__adddf3+0x124>
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8000378: f5b1 1f00 cmp.w r1, #2097152 @ 0x200000
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800037c: d30c bcc.n 8000398 <__adddf3+0x10c>
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800037e: 0849 lsrs r1, r1, #1
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8000380: ea5f 0030 movs.w r0, r0, rrx
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8000384: ea4f 0c3c mov.w ip, ip, rrx
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8000388: f104 0401 add.w r4, r4, #1
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800038c: ea4f 5244 mov.w r2, r4, lsl #21
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8000390: f512 0f80 cmn.w r2, #4194304 @ 0x400000
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8000394: f080 809a bcs.w 80004cc <__adddf3+0x240>
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8000398: f1bc 4f00 cmp.w ip, #2147483648 @ 0x80000000
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800039c: bf08 it eq
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800039e: ea5f 0c50 movseq.w ip, r0, lsr #1
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80003a2: f150 0000 adcs.w r0, r0, #0
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80003a6: eb41 5104 adc.w r1, r1, r4, lsl #20
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80003aa: ea41 0105 orr.w r1, r1, r5
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80003ae: bd30 pop {r4, r5, pc}
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80003b0: ea5f 0c4c movs.w ip, ip, lsl #1
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80003b4: 4140 adcs r0, r0
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80003b6: eb41 0101 adc.w r1, r1, r1
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80003ba: 3c01 subs r4, #1
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80003bc: bf28 it cs
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80003be: f5b1 1f80 cmpcs.w r1, #1048576 @ 0x100000
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80003c2: d2e9 bcs.n 8000398 <__adddf3+0x10c>
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80003c4: f091 0f00 teq r1, #0
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80003c8: bf04 itt eq
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80003ca: 4601 moveq r1, r0
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80003cc: 2000 moveq r0, #0
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80003ce: fab1 f381 clz r3, r1
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80003d2: bf08 it eq
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80003d4: 3320 addeq r3, #32
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80003d6: f1a3 030b sub.w r3, r3, #11
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80003da: f1b3 0220 subs.w r2, r3, #32
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80003de: da0c bge.n 80003fa <__adddf3+0x16e>
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80003e0: 320c adds r2, #12
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80003e2: dd08 ble.n 80003f6 <__adddf3+0x16a>
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80003e4: f102 0c14 add.w ip, r2, #20
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80003e8: f1c2 020c rsb r2, r2, #12
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80003ec: fa01 f00c lsl.w r0, r1, ip
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80003f0: fa21 f102 lsr.w r1, r1, r2
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80003f4: e00c b.n 8000410 <__adddf3+0x184>
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80003f6: f102 0214 add.w r2, r2, #20
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80003fa: bfd8 it le
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80003fc: f1c2 0c20 rsble ip, r2, #32
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8000400: fa01 f102 lsl.w r1, r1, r2
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8000404: fa20 fc0c lsr.w ip, r0, ip
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8000408: bfdc itt le
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800040a: ea41 010c orrle.w r1, r1, ip
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800040e: 4090 lslle r0, r2
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8000410: 1ae4 subs r4, r4, r3
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8000412: bfa2 ittt ge
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8000414: eb01 5104 addge.w r1, r1, r4, lsl #20
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8000418: 4329 orrge r1, r5
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800041a: bd30 popge {r4, r5, pc}
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800041c: ea6f 0404 mvn.w r4, r4
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8000420: 3c1f subs r4, #31
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8000422: da1c bge.n 800045e <__adddf3+0x1d2>
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8000424: 340c adds r4, #12
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8000426: dc0e bgt.n 8000446 <__adddf3+0x1ba>
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8000428: f104 0414 add.w r4, r4, #20
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800042c: f1c4 0220 rsb r2, r4, #32
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8000430: fa20 f004 lsr.w r0, r0, r4
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8000434: fa01 f302 lsl.w r3, r1, r2
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8000438: ea40 0003 orr.w r0, r0, r3
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800043c: fa21 f304 lsr.w r3, r1, r4
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8000440: ea45 0103 orr.w r1, r5, r3
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8000444: bd30 pop {r4, r5, pc}
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8000446: f1c4 040c rsb r4, r4, #12
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800044a: f1c4 0220 rsb r2, r4, #32
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800044e: fa20 f002 lsr.w r0, r0, r2
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8000452: fa01 f304 lsl.w r3, r1, r4
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8000456: ea40 0003 orr.w r0, r0, r3
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800045a: 4629 mov r1, r5
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800045c: bd30 pop {r4, r5, pc}
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800045e: fa21 f004 lsr.w r0, r1, r4
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8000462: 4629 mov r1, r5
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8000464: bd30 pop {r4, r5, pc}
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8000466: f094 0f00 teq r4, #0
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800046a: f483 1380 eor.w r3, r3, #1048576 @ 0x100000
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800046e: bf06 itte eq
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8000470: f481 1180 eoreq.w r1, r1, #1048576 @ 0x100000
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8000474: 3401 addeq r4, #1
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8000476: 3d01 subne r5, #1
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8000478: e74e b.n 8000318 <__adddf3+0x8c>
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800047a: ea7f 5c64 mvns.w ip, r4, asr #21
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800047e: bf18 it ne
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8000480: ea7f 5c65 mvnsne.w ip, r5, asr #21
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8000484: d029 beq.n 80004da <__adddf3+0x24e>
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8000486: ea94 0f05 teq r4, r5
|
|
800048a: bf08 it eq
|
|
800048c: ea90 0f02 teqeq r0, r2
|
|
8000490: d005 beq.n 800049e <__adddf3+0x212>
|
|
8000492: ea54 0c00 orrs.w ip, r4, r0
|
|
8000496: bf04 itt eq
|
|
8000498: 4619 moveq r1, r3
|
|
800049a: 4610 moveq r0, r2
|
|
800049c: bd30 pop {r4, r5, pc}
|
|
800049e: ea91 0f03 teq r1, r3
|
|
80004a2: bf1e ittt ne
|
|
80004a4: 2100 movne r1, #0
|
|
80004a6: 2000 movne r0, #0
|
|
80004a8: bd30 popne {r4, r5, pc}
|
|
80004aa: ea5f 5c54 movs.w ip, r4, lsr #21
|
|
80004ae: d105 bne.n 80004bc <__adddf3+0x230>
|
|
80004b0: 0040 lsls r0, r0, #1
|
|
80004b2: 4149 adcs r1, r1
|
|
80004b4: bf28 it cs
|
|
80004b6: f041 4100 orrcs.w r1, r1, #2147483648 @ 0x80000000
|
|
80004ba: bd30 pop {r4, r5, pc}
|
|
80004bc: f514 0480 adds.w r4, r4, #4194304 @ 0x400000
|
|
80004c0: bf3c itt cc
|
|
80004c2: f501 1180 addcc.w r1, r1, #1048576 @ 0x100000
|
|
80004c6: bd30 popcc {r4, r5, pc}
|
|
80004c8: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
|
|
80004cc: f045 41fe orr.w r1, r5, #2130706432 @ 0x7f000000
|
|
80004d0: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
|
|
80004d4: f04f 0000 mov.w r0, #0
|
|
80004d8: bd30 pop {r4, r5, pc}
|
|
80004da: ea7f 5c64 mvns.w ip, r4, asr #21
|
|
80004de: bf1a itte ne
|
|
80004e0: 4619 movne r1, r3
|
|
80004e2: 4610 movne r0, r2
|
|
80004e4: ea7f 5c65 mvnseq.w ip, r5, asr #21
|
|
80004e8: bf1c itt ne
|
|
80004ea: 460b movne r3, r1
|
|
80004ec: 4602 movne r2, r0
|
|
80004ee: ea50 3401 orrs.w r4, r0, r1, lsl #12
|
|
80004f2: bf06 itte eq
|
|
80004f4: ea52 3503 orrseq.w r5, r2, r3, lsl #12
|
|
80004f8: ea91 0f03 teqeq r1, r3
|
|
80004fc: f441 2100 orrne.w r1, r1, #524288 @ 0x80000
|
|
8000500: bd30 pop {r4, r5, pc}
|
|
8000502: bf00 nop
|
|
|
|
08000504 <__aeabi_ui2d>:
|
|
8000504: f090 0f00 teq r0, #0
|
|
8000508: bf04 itt eq
|
|
800050a: 2100 moveq r1, #0
|
|
800050c: 4770 bxeq lr
|
|
800050e: b530 push {r4, r5, lr}
|
|
8000510: f44f 6480 mov.w r4, #1024 @ 0x400
|
|
8000514: f104 0432 add.w r4, r4, #50 @ 0x32
|
|
8000518: f04f 0500 mov.w r5, #0
|
|
800051c: f04f 0100 mov.w r1, #0
|
|
8000520: e750 b.n 80003c4 <__adddf3+0x138>
|
|
8000522: bf00 nop
|
|
|
|
08000524 <__aeabi_i2d>:
|
|
8000524: f090 0f00 teq r0, #0
|
|
8000528: bf04 itt eq
|
|
800052a: 2100 moveq r1, #0
|
|
800052c: 4770 bxeq lr
|
|
800052e: b530 push {r4, r5, lr}
|
|
8000530: f44f 6480 mov.w r4, #1024 @ 0x400
|
|
8000534: f104 0432 add.w r4, r4, #50 @ 0x32
|
|
8000538: f010 4500 ands.w r5, r0, #2147483648 @ 0x80000000
|
|
800053c: bf48 it mi
|
|
800053e: 4240 negmi r0, r0
|
|
8000540: f04f 0100 mov.w r1, #0
|
|
8000544: e73e b.n 80003c4 <__adddf3+0x138>
|
|
8000546: bf00 nop
|
|
|
|
08000548 <__aeabi_f2d>:
|
|
8000548: 0042 lsls r2, r0, #1
|
|
800054a: ea4f 01e2 mov.w r1, r2, asr #3
|
|
800054e: ea4f 0131 mov.w r1, r1, rrx
|
|
8000552: ea4f 7002 mov.w r0, r2, lsl #28
|
|
8000556: bf1f itttt ne
|
|
8000558: f012 437f andsne.w r3, r2, #4278190080 @ 0xff000000
|
|
800055c: f093 4f7f teqne r3, #4278190080 @ 0xff000000
|
|
8000560: f081 5160 eorne.w r1, r1, #939524096 @ 0x38000000
|
|
8000564: 4770 bxne lr
|
|
8000566: f032 427f bics.w r2, r2, #4278190080 @ 0xff000000
|
|
800056a: bf08 it eq
|
|
800056c: 4770 bxeq lr
|
|
800056e: f093 4f7f teq r3, #4278190080 @ 0xff000000
|
|
8000572: bf04 itt eq
|
|
8000574: f441 2100 orreq.w r1, r1, #524288 @ 0x80000
|
|
8000578: 4770 bxeq lr
|
|
800057a: b530 push {r4, r5, lr}
|
|
800057c: f44f 7460 mov.w r4, #896 @ 0x380
|
|
8000580: f001 4500 and.w r5, r1, #2147483648 @ 0x80000000
|
|
8000584: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
|
|
8000588: e71c b.n 80003c4 <__adddf3+0x138>
|
|
800058a: bf00 nop
|
|
|
|
0800058c <__aeabi_ul2d>:
|
|
800058c: ea50 0201 orrs.w r2, r0, r1
|
|
8000590: bf08 it eq
|
|
8000592: 4770 bxeq lr
|
|
8000594: b530 push {r4, r5, lr}
|
|
8000596: f04f 0500 mov.w r5, #0
|
|
800059a: e00a b.n 80005b2 <__aeabi_l2d+0x16>
|
|
|
|
0800059c <__aeabi_l2d>:
|
|
800059c: ea50 0201 orrs.w r2, r0, r1
|
|
80005a0: bf08 it eq
|
|
80005a2: 4770 bxeq lr
|
|
80005a4: b530 push {r4, r5, lr}
|
|
80005a6: f011 4500 ands.w r5, r1, #2147483648 @ 0x80000000
|
|
80005aa: d502 bpl.n 80005b2 <__aeabi_l2d+0x16>
|
|
80005ac: 4240 negs r0, r0
|
|
80005ae: eb61 0141 sbc.w r1, r1, r1, lsl #1
|
|
80005b2: f44f 6480 mov.w r4, #1024 @ 0x400
|
|
80005b6: f104 0432 add.w r4, r4, #50 @ 0x32
|
|
80005ba: ea5f 5c91 movs.w ip, r1, lsr #22
|
|
80005be: f43f aed8 beq.w 8000372 <__adddf3+0xe6>
|
|
80005c2: f04f 0203 mov.w r2, #3
|
|
80005c6: ea5f 0cdc movs.w ip, ip, lsr #3
|
|
80005ca: bf18 it ne
|
|
80005cc: 3203 addne r2, #3
|
|
80005ce: ea5f 0cdc movs.w ip, ip, lsr #3
|
|
80005d2: bf18 it ne
|
|
80005d4: 3203 addne r2, #3
|
|
80005d6: eb02 02dc add.w r2, r2, ip, lsr #3
|
|
80005da: f1c2 0320 rsb r3, r2, #32
|
|
80005de: fa00 fc03 lsl.w ip, r0, r3
|
|
80005e2: fa20 f002 lsr.w r0, r0, r2
|
|
80005e6: fa01 fe03 lsl.w lr, r1, r3
|
|
80005ea: ea40 000e orr.w r0, r0, lr
|
|
80005ee: fa21 f102 lsr.w r1, r1, r2
|
|
80005f2: 4414 add r4, r2
|
|
80005f4: e6bd b.n 8000372 <__adddf3+0xe6>
|
|
80005f6: bf00 nop
|
|
|
|
080005f8 <__aeabi_dmul>:
|
|
80005f8: b570 push {r4, r5, r6, lr}
|
|
80005fa: f04f 0cff mov.w ip, #255 @ 0xff
|
|
80005fe: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700
|
|
8000602: ea1c 5411 ands.w r4, ip, r1, lsr #20
|
|
8000606: bf1d ittte ne
|
|
8000608: ea1c 5513 andsne.w r5, ip, r3, lsr #20
|
|
800060c: ea94 0f0c teqne r4, ip
|
|
8000610: ea95 0f0c teqne r5, ip
|
|
8000614: f000 f8de bleq 80007d4 <__aeabi_dmul+0x1dc>
|
|
8000618: 442c add r4, r5
|
|
800061a: ea81 0603 eor.w r6, r1, r3
|
|
800061e: ea21 514c bic.w r1, r1, ip, lsl #21
|
|
8000622: ea23 534c bic.w r3, r3, ip, lsl #21
|
|
8000626: ea50 3501 orrs.w r5, r0, r1, lsl #12
|
|
800062a: bf18 it ne
|
|
800062c: ea52 3503 orrsne.w r5, r2, r3, lsl #12
|
|
8000630: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
|
|
8000634: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
8000638: d038 beq.n 80006ac <__aeabi_dmul+0xb4>
|
|
800063a: fba0 ce02 umull ip, lr, r0, r2
|
|
800063e: f04f 0500 mov.w r5, #0
|
|
8000642: fbe1 e502 umlal lr, r5, r1, r2
|
|
8000646: f006 4200 and.w r2, r6, #2147483648 @ 0x80000000
|
|
800064a: fbe0 e503 umlal lr, r5, r0, r3
|
|
800064e: f04f 0600 mov.w r6, #0
|
|
8000652: fbe1 5603 umlal r5, r6, r1, r3
|
|
8000656: f09c 0f00 teq ip, #0
|
|
800065a: bf18 it ne
|
|
800065c: f04e 0e01 orrne.w lr, lr, #1
|
|
8000660: f1a4 04ff sub.w r4, r4, #255 @ 0xff
|
|
8000664: f5b6 7f00 cmp.w r6, #512 @ 0x200
|
|
8000668: f564 7440 sbc.w r4, r4, #768 @ 0x300
|
|
800066c: d204 bcs.n 8000678 <__aeabi_dmul+0x80>
|
|
800066e: ea5f 0e4e movs.w lr, lr, lsl #1
|
|
8000672: 416d adcs r5, r5
|
|
8000674: eb46 0606 adc.w r6, r6, r6
|
|
8000678: ea42 21c6 orr.w r1, r2, r6, lsl #11
|
|
800067c: ea41 5155 orr.w r1, r1, r5, lsr #21
|
|
8000680: ea4f 20c5 mov.w r0, r5, lsl #11
|
|
8000684: ea40 505e orr.w r0, r0, lr, lsr #21
|
|
8000688: ea4f 2ece mov.w lr, lr, lsl #11
|
|
800068c: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd
|
|
8000690: bf88 it hi
|
|
8000692: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700
|
|
8000696: d81e bhi.n 80006d6 <__aeabi_dmul+0xde>
|
|
8000698: f1be 4f00 cmp.w lr, #2147483648 @ 0x80000000
|
|
800069c: bf08 it eq
|
|
800069e: ea5f 0e50 movseq.w lr, r0, lsr #1
|
|
80006a2: f150 0000 adcs.w r0, r0, #0
|
|
80006a6: eb41 5104 adc.w r1, r1, r4, lsl #20
|
|
80006aa: bd70 pop {r4, r5, r6, pc}
|
|
80006ac: f006 4600 and.w r6, r6, #2147483648 @ 0x80000000
|
|
80006b0: ea46 0101 orr.w r1, r6, r1
|
|
80006b4: ea40 0002 orr.w r0, r0, r2
|
|
80006b8: ea81 0103 eor.w r1, r1, r3
|
|
80006bc: ebb4 045c subs.w r4, r4, ip, lsr #1
|
|
80006c0: bfc2 ittt gt
|
|
80006c2: ebd4 050c rsbsgt r5, r4, ip
|
|
80006c6: ea41 5104 orrgt.w r1, r1, r4, lsl #20
|
|
80006ca: bd70 popgt {r4, r5, r6, pc}
|
|
80006cc: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
|
|
80006d0: f04f 0e00 mov.w lr, #0
|
|
80006d4: 3c01 subs r4, #1
|
|
80006d6: f300 80ab bgt.w 8000830 <__aeabi_dmul+0x238>
|
|
80006da: f114 0f36 cmn.w r4, #54 @ 0x36
|
|
80006de: bfde ittt le
|
|
80006e0: 2000 movle r0, #0
|
|
80006e2: f001 4100 andle.w r1, r1, #2147483648 @ 0x80000000
|
|
80006e6: bd70 pople {r4, r5, r6, pc}
|
|
80006e8: f1c4 0400 rsb r4, r4, #0
|
|
80006ec: 3c20 subs r4, #32
|
|
80006ee: da35 bge.n 800075c <__aeabi_dmul+0x164>
|
|
80006f0: 340c adds r4, #12
|
|
80006f2: dc1b bgt.n 800072c <__aeabi_dmul+0x134>
|
|
80006f4: f104 0414 add.w r4, r4, #20
|
|
80006f8: f1c4 0520 rsb r5, r4, #32
|
|
80006fc: fa00 f305 lsl.w r3, r0, r5
|
|
8000700: fa20 f004 lsr.w r0, r0, r4
|
|
8000704: fa01 f205 lsl.w r2, r1, r5
|
|
8000708: ea40 0002 orr.w r0, r0, r2
|
|
800070c: f001 4200 and.w r2, r1, #2147483648 @ 0x80000000
|
|
8000710: f021 4100 bic.w r1, r1, #2147483648 @ 0x80000000
|
|
8000714: eb10 70d3 adds.w r0, r0, r3, lsr #31
|
|
8000718: fa21 f604 lsr.w r6, r1, r4
|
|
800071c: eb42 0106 adc.w r1, r2, r6
|
|
8000720: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
|
|
8000724: bf08 it eq
|
|
8000726: ea20 70d3 biceq.w r0, r0, r3, lsr #31
|
|
800072a: bd70 pop {r4, r5, r6, pc}
|
|
800072c: f1c4 040c rsb r4, r4, #12
|
|
8000730: f1c4 0520 rsb r5, r4, #32
|
|
8000734: fa00 f304 lsl.w r3, r0, r4
|
|
8000738: fa20 f005 lsr.w r0, r0, r5
|
|
800073c: fa01 f204 lsl.w r2, r1, r4
|
|
8000740: ea40 0002 orr.w r0, r0, r2
|
|
8000744: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
|
|
8000748: eb10 70d3 adds.w r0, r0, r3, lsr #31
|
|
800074c: f141 0100 adc.w r1, r1, #0
|
|
8000750: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
|
|
8000754: bf08 it eq
|
|
8000756: ea20 70d3 biceq.w r0, r0, r3, lsr #31
|
|
800075a: bd70 pop {r4, r5, r6, pc}
|
|
800075c: f1c4 0520 rsb r5, r4, #32
|
|
8000760: fa00 f205 lsl.w r2, r0, r5
|
|
8000764: ea4e 0e02 orr.w lr, lr, r2
|
|
8000768: fa20 f304 lsr.w r3, r0, r4
|
|
800076c: fa01 f205 lsl.w r2, r1, r5
|
|
8000770: ea43 0302 orr.w r3, r3, r2
|
|
8000774: fa21 f004 lsr.w r0, r1, r4
|
|
8000778: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
|
|
800077c: fa21 f204 lsr.w r2, r1, r4
|
|
8000780: ea20 0002 bic.w r0, r0, r2
|
|
8000784: eb00 70d3 add.w r0, r0, r3, lsr #31
|
|
8000788: ea5e 0e43 orrs.w lr, lr, r3, lsl #1
|
|
800078c: bf08 it eq
|
|
800078e: ea20 70d3 biceq.w r0, r0, r3, lsr #31
|
|
8000792: bd70 pop {r4, r5, r6, pc}
|
|
8000794: f094 0f00 teq r4, #0
|
|
8000798: d10f bne.n 80007ba <__aeabi_dmul+0x1c2>
|
|
800079a: f001 4600 and.w r6, r1, #2147483648 @ 0x80000000
|
|
800079e: 0040 lsls r0, r0, #1
|
|
80007a0: eb41 0101 adc.w r1, r1, r1
|
|
80007a4: f411 1f80 tst.w r1, #1048576 @ 0x100000
|
|
80007a8: bf08 it eq
|
|
80007aa: 3c01 subeq r4, #1
|
|
80007ac: d0f7 beq.n 800079e <__aeabi_dmul+0x1a6>
|
|
80007ae: ea41 0106 orr.w r1, r1, r6
|
|
80007b2: f095 0f00 teq r5, #0
|
|
80007b6: bf18 it ne
|
|
80007b8: 4770 bxne lr
|
|
80007ba: f003 4600 and.w r6, r3, #2147483648 @ 0x80000000
|
|
80007be: 0052 lsls r2, r2, #1
|
|
80007c0: eb43 0303 adc.w r3, r3, r3
|
|
80007c4: f413 1f80 tst.w r3, #1048576 @ 0x100000
|
|
80007c8: bf08 it eq
|
|
80007ca: 3d01 subeq r5, #1
|
|
80007cc: d0f7 beq.n 80007be <__aeabi_dmul+0x1c6>
|
|
80007ce: ea43 0306 orr.w r3, r3, r6
|
|
80007d2: 4770 bx lr
|
|
80007d4: ea94 0f0c teq r4, ip
|
|
80007d8: ea0c 5513 and.w r5, ip, r3, lsr #20
|
|
80007dc: bf18 it ne
|
|
80007de: ea95 0f0c teqne r5, ip
|
|
80007e2: d00c beq.n 80007fe <__aeabi_dmul+0x206>
|
|
80007e4: ea50 0641 orrs.w r6, r0, r1, lsl #1
|
|
80007e8: bf18 it ne
|
|
80007ea: ea52 0643 orrsne.w r6, r2, r3, lsl #1
|
|
80007ee: d1d1 bne.n 8000794 <__aeabi_dmul+0x19c>
|
|
80007f0: ea81 0103 eor.w r1, r1, r3
|
|
80007f4: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
|
|
80007f8: f04f 0000 mov.w r0, #0
|
|
80007fc: bd70 pop {r4, r5, r6, pc}
|
|
80007fe: ea50 0641 orrs.w r6, r0, r1, lsl #1
|
|
8000802: bf06 itte eq
|
|
8000804: 4610 moveq r0, r2
|
|
8000806: 4619 moveq r1, r3
|
|
8000808: ea52 0643 orrsne.w r6, r2, r3, lsl #1
|
|
800080c: d019 beq.n 8000842 <__aeabi_dmul+0x24a>
|
|
800080e: ea94 0f0c teq r4, ip
|
|
8000812: d102 bne.n 800081a <__aeabi_dmul+0x222>
|
|
8000814: ea50 3601 orrs.w r6, r0, r1, lsl #12
|
|
8000818: d113 bne.n 8000842 <__aeabi_dmul+0x24a>
|
|
800081a: ea95 0f0c teq r5, ip
|
|
800081e: d105 bne.n 800082c <__aeabi_dmul+0x234>
|
|
8000820: ea52 3603 orrs.w r6, r2, r3, lsl #12
|
|
8000824: bf1c itt ne
|
|
8000826: 4610 movne r0, r2
|
|
8000828: 4619 movne r1, r3
|
|
800082a: d10a bne.n 8000842 <__aeabi_dmul+0x24a>
|
|
800082c: ea81 0103 eor.w r1, r1, r3
|
|
8000830: f001 4100 and.w r1, r1, #2147483648 @ 0x80000000
|
|
8000834: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
|
|
8000838: f441 0170 orr.w r1, r1, #15728640 @ 0xf00000
|
|
800083c: f04f 0000 mov.w r0, #0
|
|
8000840: bd70 pop {r4, r5, r6, pc}
|
|
8000842: f041 41fe orr.w r1, r1, #2130706432 @ 0x7f000000
|
|
8000846: f441 0178 orr.w r1, r1, #16252928 @ 0xf80000
|
|
800084a: bd70 pop {r4, r5, r6, pc}
|
|
|
|
0800084c <__aeabi_ddiv>:
|
|
800084c: b570 push {r4, r5, r6, lr}
|
|
800084e: f04f 0cff mov.w ip, #255 @ 0xff
|
|
8000852: f44c 6ce0 orr.w ip, ip, #1792 @ 0x700
|
|
8000856: ea1c 5411 ands.w r4, ip, r1, lsr #20
|
|
800085a: bf1d ittte ne
|
|
800085c: ea1c 5513 andsne.w r5, ip, r3, lsr #20
|
|
8000860: ea94 0f0c teqne r4, ip
|
|
8000864: ea95 0f0c teqne r5, ip
|
|
8000868: f000 f8a7 bleq 80009ba <__aeabi_ddiv+0x16e>
|
|
800086c: eba4 0405 sub.w r4, r4, r5
|
|
8000870: ea81 0e03 eor.w lr, r1, r3
|
|
8000874: ea52 3503 orrs.w r5, r2, r3, lsl #12
|
|
8000878: ea4f 3101 mov.w r1, r1, lsl #12
|
|
800087c: f000 8088 beq.w 8000990 <__aeabi_ddiv+0x144>
|
|
8000880: ea4f 3303 mov.w r3, r3, lsl #12
|
|
8000884: f04f 5580 mov.w r5, #268435456 @ 0x10000000
|
|
8000888: ea45 1313 orr.w r3, r5, r3, lsr #4
|
|
800088c: ea43 6312 orr.w r3, r3, r2, lsr #24
|
|
8000890: ea4f 2202 mov.w r2, r2, lsl #8
|
|
8000894: ea45 1511 orr.w r5, r5, r1, lsr #4
|
|
8000898: ea45 6510 orr.w r5, r5, r0, lsr #24
|
|
800089c: ea4f 2600 mov.w r6, r0, lsl #8
|
|
80008a0: f00e 4100 and.w r1, lr, #2147483648 @ 0x80000000
|
|
80008a4: 429d cmp r5, r3
|
|
80008a6: bf08 it eq
|
|
80008a8: 4296 cmpeq r6, r2
|
|
80008aa: f144 04fd adc.w r4, r4, #253 @ 0xfd
|
|
80008ae: f504 7440 add.w r4, r4, #768 @ 0x300
|
|
80008b2: d202 bcs.n 80008ba <__aeabi_ddiv+0x6e>
|
|
80008b4: 085b lsrs r3, r3, #1
|
|
80008b6: ea4f 0232 mov.w r2, r2, rrx
|
|
80008ba: 1ab6 subs r6, r6, r2
|
|
80008bc: eb65 0503 sbc.w r5, r5, r3
|
|
80008c0: 085b lsrs r3, r3, #1
|
|
80008c2: ea4f 0232 mov.w r2, r2, rrx
|
|
80008c6: f44f 1080 mov.w r0, #1048576 @ 0x100000
|
|
80008ca: f44f 2c00 mov.w ip, #524288 @ 0x80000
|
|
80008ce: ebb6 0e02 subs.w lr, r6, r2
|
|
80008d2: eb75 0e03 sbcs.w lr, r5, r3
|
|
80008d6: bf22 ittt cs
|
|
80008d8: 1ab6 subcs r6, r6, r2
|
|
80008da: 4675 movcs r5, lr
|
|
80008dc: ea40 000c orrcs.w r0, r0, ip
|
|
80008e0: 085b lsrs r3, r3, #1
|
|
80008e2: ea4f 0232 mov.w r2, r2, rrx
|
|
80008e6: ebb6 0e02 subs.w lr, r6, r2
|
|
80008ea: eb75 0e03 sbcs.w lr, r5, r3
|
|
80008ee: bf22 ittt cs
|
|
80008f0: 1ab6 subcs r6, r6, r2
|
|
80008f2: 4675 movcs r5, lr
|
|
80008f4: ea40 005c orrcs.w r0, r0, ip, lsr #1
|
|
80008f8: 085b lsrs r3, r3, #1
|
|
80008fa: ea4f 0232 mov.w r2, r2, rrx
|
|
80008fe: ebb6 0e02 subs.w lr, r6, r2
|
|
8000902: eb75 0e03 sbcs.w lr, r5, r3
|
|
8000906: bf22 ittt cs
|
|
8000908: 1ab6 subcs r6, r6, r2
|
|
800090a: 4675 movcs r5, lr
|
|
800090c: ea40 009c orrcs.w r0, r0, ip, lsr #2
|
|
8000910: 085b lsrs r3, r3, #1
|
|
8000912: ea4f 0232 mov.w r2, r2, rrx
|
|
8000916: ebb6 0e02 subs.w lr, r6, r2
|
|
800091a: eb75 0e03 sbcs.w lr, r5, r3
|
|
800091e: bf22 ittt cs
|
|
8000920: 1ab6 subcs r6, r6, r2
|
|
8000922: 4675 movcs r5, lr
|
|
8000924: ea40 00dc orrcs.w r0, r0, ip, lsr #3
|
|
8000928: ea55 0e06 orrs.w lr, r5, r6
|
|
800092c: d018 beq.n 8000960 <__aeabi_ddiv+0x114>
|
|
800092e: ea4f 1505 mov.w r5, r5, lsl #4
|
|
8000932: ea45 7516 orr.w r5, r5, r6, lsr #28
|
|
8000936: ea4f 1606 mov.w r6, r6, lsl #4
|
|
800093a: ea4f 03c3 mov.w r3, r3, lsl #3
|
|
800093e: ea43 7352 orr.w r3, r3, r2, lsr #29
|
|
8000942: ea4f 02c2 mov.w r2, r2, lsl #3
|
|
8000946: ea5f 1c1c movs.w ip, ip, lsr #4
|
|
800094a: d1c0 bne.n 80008ce <__aeabi_ddiv+0x82>
|
|
800094c: f411 1f80 tst.w r1, #1048576 @ 0x100000
|
|
8000950: d10b bne.n 800096a <__aeabi_ddiv+0x11e>
|
|
8000952: ea41 0100 orr.w r1, r1, r0
|
|
8000956: f04f 0000 mov.w r0, #0
|
|
800095a: f04f 4c00 mov.w ip, #2147483648 @ 0x80000000
|
|
800095e: e7b6 b.n 80008ce <__aeabi_ddiv+0x82>
|
|
8000960: f411 1f80 tst.w r1, #1048576 @ 0x100000
|
|
8000964: bf04 itt eq
|
|
8000966: 4301 orreq r1, r0
|
|
8000968: 2000 moveq r0, #0
|
|
800096a: f1b4 0cfd subs.w ip, r4, #253 @ 0xfd
|
|
800096e: bf88 it hi
|
|
8000970: f5bc 6fe0 cmphi.w ip, #1792 @ 0x700
|
|
8000974: f63f aeaf bhi.w 80006d6 <__aeabi_dmul+0xde>
|
|
8000978: ebb5 0c03 subs.w ip, r5, r3
|
|
800097c: bf04 itt eq
|
|
800097e: ebb6 0c02 subseq.w ip, r6, r2
|
|
8000982: ea5f 0c50 movseq.w ip, r0, lsr #1
|
|
8000986: f150 0000 adcs.w r0, r0, #0
|
|
800098a: eb41 5104 adc.w r1, r1, r4, lsl #20
|
|
800098e: bd70 pop {r4, r5, r6, pc}
|
|
8000990: f00e 4e00 and.w lr, lr, #2147483648 @ 0x80000000
|
|
8000994: ea4e 3111 orr.w r1, lr, r1, lsr #12
|
|
8000998: eb14 045c adds.w r4, r4, ip, lsr #1
|
|
800099c: bfc2 ittt gt
|
|
800099e: ebd4 050c rsbsgt r5, r4, ip
|
|
80009a2: ea41 5104 orrgt.w r1, r1, r4, lsl #20
|
|
80009a6: bd70 popgt {r4, r5, r6, pc}
|
|
80009a8: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
|
|
80009ac: f04f 0e00 mov.w lr, #0
|
|
80009b0: 3c01 subs r4, #1
|
|
80009b2: e690 b.n 80006d6 <__aeabi_dmul+0xde>
|
|
80009b4: ea45 0e06 orr.w lr, r5, r6
|
|
80009b8: e68d b.n 80006d6 <__aeabi_dmul+0xde>
|
|
80009ba: ea0c 5513 and.w r5, ip, r3, lsr #20
|
|
80009be: ea94 0f0c teq r4, ip
|
|
80009c2: bf08 it eq
|
|
80009c4: ea95 0f0c teqeq r5, ip
|
|
80009c8: f43f af3b beq.w 8000842 <__aeabi_dmul+0x24a>
|
|
80009cc: ea94 0f0c teq r4, ip
|
|
80009d0: d10a bne.n 80009e8 <__aeabi_ddiv+0x19c>
|
|
80009d2: ea50 3401 orrs.w r4, r0, r1, lsl #12
|
|
80009d6: f47f af34 bne.w 8000842 <__aeabi_dmul+0x24a>
|
|
80009da: ea95 0f0c teq r5, ip
|
|
80009de: f47f af25 bne.w 800082c <__aeabi_dmul+0x234>
|
|
80009e2: 4610 mov r0, r2
|
|
80009e4: 4619 mov r1, r3
|
|
80009e6: e72c b.n 8000842 <__aeabi_dmul+0x24a>
|
|
80009e8: ea95 0f0c teq r5, ip
|
|
80009ec: d106 bne.n 80009fc <__aeabi_ddiv+0x1b0>
|
|
80009ee: ea52 3503 orrs.w r5, r2, r3, lsl #12
|
|
80009f2: f43f aefd beq.w 80007f0 <__aeabi_dmul+0x1f8>
|
|
80009f6: 4610 mov r0, r2
|
|
80009f8: 4619 mov r1, r3
|
|
80009fa: e722 b.n 8000842 <__aeabi_dmul+0x24a>
|
|
80009fc: ea50 0641 orrs.w r6, r0, r1, lsl #1
|
|
8000a00: bf18 it ne
|
|
8000a02: ea52 0643 orrsne.w r6, r2, r3, lsl #1
|
|
8000a06: f47f aec5 bne.w 8000794 <__aeabi_dmul+0x19c>
|
|
8000a0a: ea50 0441 orrs.w r4, r0, r1, lsl #1
|
|
8000a0e: f47f af0d bne.w 800082c <__aeabi_dmul+0x234>
|
|
8000a12: ea52 0543 orrs.w r5, r2, r3, lsl #1
|
|
8000a16: f47f aeeb bne.w 80007f0 <__aeabi_dmul+0x1f8>
|
|
8000a1a: e712 b.n 8000842 <__aeabi_dmul+0x24a>
|
|
|
|
08000a1c <__gedf2>:
|
|
8000a1c: f04f 3cff mov.w ip, #4294967295 @ 0xffffffff
|
|
8000a20: e006 b.n 8000a30 <__cmpdf2+0x4>
|
|
8000a22: bf00 nop
|
|
|
|
08000a24 <__ledf2>:
|
|
8000a24: f04f 0c01 mov.w ip, #1
|
|
8000a28: e002 b.n 8000a30 <__cmpdf2+0x4>
|
|
8000a2a: bf00 nop
|
|
|
|
08000a2c <__cmpdf2>:
|
|
8000a2c: f04f 0c01 mov.w ip, #1
|
|
8000a30: f84d cd04 str.w ip, [sp, #-4]!
|
|
8000a34: ea4f 0c41 mov.w ip, r1, lsl #1
|
|
8000a38: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000a3c: ea4f 0c43 mov.w ip, r3, lsl #1
|
|
8000a40: bf18 it ne
|
|
8000a42: ea7f 5c6c mvnsne.w ip, ip, asr #21
|
|
8000a46: d01b beq.n 8000a80 <__cmpdf2+0x54>
|
|
8000a48: b001 add sp, #4
|
|
8000a4a: ea50 0c41 orrs.w ip, r0, r1, lsl #1
|
|
8000a4e: bf0c ite eq
|
|
8000a50: ea52 0c43 orrseq.w ip, r2, r3, lsl #1
|
|
8000a54: ea91 0f03 teqne r1, r3
|
|
8000a58: bf02 ittt eq
|
|
8000a5a: ea90 0f02 teqeq r0, r2
|
|
8000a5e: 2000 moveq r0, #0
|
|
8000a60: 4770 bxeq lr
|
|
8000a62: f110 0f00 cmn.w r0, #0
|
|
8000a66: ea91 0f03 teq r1, r3
|
|
8000a6a: bf58 it pl
|
|
8000a6c: 4299 cmppl r1, r3
|
|
8000a6e: bf08 it eq
|
|
8000a70: 4290 cmpeq r0, r2
|
|
8000a72: bf2c ite cs
|
|
8000a74: 17d8 asrcs r0, r3, #31
|
|
8000a76: ea6f 70e3 mvncc.w r0, r3, asr #31
|
|
8000a7a: f040 0001 orr.w r0, r0, #1
|
|
8000a7e: 4770 bx lr
|
|
8000a80: ea4f 0c41 mov.w ip, r1, lsl #1
|
|
8000a84: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000a88: d102 bne.n 8000a90 <__cmpdf2+0x64>
|
|
8000a8a: ea50 3c01 orrs.w ip, r0, r1, lsl #12
|
|
8000a8e: d107 bne.n 8000aa0 <__cmpdf2+0x74>
|
|
8000a90: ea4f 0c43 mov.w ip, r3, lsl #1
|
|
8000a94: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000a98: d1d6 bne.n 8000a48 <__cmpdf2+0x1c>
|
|
8000a9a: ea52 3c03 orrs.w ip, r2, r3, lsl #12
|
|
8000a9e: d0d3 beq.n 8000a48 <__cmpdf2+0x1c>
|
|
8000aa0: f85d 0b04 ldr.w r0, [sp], #4
|
|
8000aa4: 4770 bx lr
|
|
8000aa6: bf00 nop
|
|
|
|
08000aa8 <__aeabi_cdrcmple>:
|
|
8000aa8: 4684 mov ip, r0
|
|
8000aaa: 4610 mov r0, r2
|
|
8000aac: 4662 mov r2, ip
|
|
8000aae: 468c mov ip, r1
|
|
8000ab0: 4619 mov r1, r3
|
|
8000ab2: 4663 mov r3, ip
|
|
8000ab4: e000 b.n 8000ab8 <__aeabi_cdcmpeq>
|
|
8000ab6: bf00 nop
|
|
|
|
08000ab8 <__aeabi_cdcmpeq>:
|
|
8000ab8: b501 push {r0, lr}
|
|
8000aba: f7ff ffb7 bl 8000a2c <__cmpdf2>
|
|
8000abe: 2800 cmp r0, #0
|
|
8000ac0: bf48 it mi
|
|
8000ac2: f110 0f00 cmnmi.w r0, #0
|
|
8000ac6: bd01 pop {r0, pc}
|
|
|
|
08000ac8 <__aeabi_dcmpeq>:
|
|
8000ac8: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000acc: f7ff fff4 bl 8000ab8 <__aeabi_cdcmpeq>
|
|
8000ad0: bf0c ite eq
|
|
8000ad2: 2001 moveq r0, #1
|
|
8000ad4: 2000 movne r0, #0
|
|
8000ad6: f85d fb08 ldr.w pc, [sp], #8
|
|
8000ada: bf00 nop
|
|
|
|
08000adc <__aeabi_dcmplt>:
|
|
8000adc: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000ae0: f7ff ffea bl 8000ab8 <__aeabi_cdcmpeq>
|
|
8000ae4: bf34 ite cc
|
|
8000ae6: 2001 movcc r0, #1
|
|
8000ae8: 2000 movcs r0, #0
|
|
8000aea: f85d fb08 ldr.w pc, [sp], #8
|
|
8000aee: bf00 nop
|
|
|
|
08000af0 <__aeabi_dcmple>:
|
|
8000af0: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000af4: f7ff ffe0 bl 8000ab8 <__aeabi_cdcmpeq>
|
|
8000af8: bf94 ite ls
|
|
8000afa: 2001 movls r0, #1
|
|
8000afc: 2000 movhi r0, #0
|
|
8000afe: f85d fb08 ldr.w pc, [sp], #8
|
|
8000b02: bf00 nop
|
|
|
|
08000b04 <__aeabi_dcmpge>:
|
|
8000b04: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000b08: f7ff ffce bl 8000aa8 <__aeabi_cdrcmple>
|
|
8000b0c: bf94 ite ls
|
|
8000b0e: 2001 movls r0, #1
|
|
8000b10: 2000 movhi r0, #0
|
|
8000b12: f85d fb08 ldr.w pc, [sp], #8
|
|
8000b16: bf00 nop
|
|
|
|
08000b18 <__aeabi_dcmpgt>:
|
|
8000b18: f84d ed08 str.w lr, [sp, #-8]!
|
|
8000b1c: f7ff ffc4 bl 8000aa8 <__aeabi_cdrcmple>
|
|
8000b20: bf34 ite cc
|
|
8000b22: 2001 movcc r0, #1
|
|
8000b24: 2000 movcs r0, #0
|
|
8000b26: f85d fb08 ldr.w pc, [sp], #8
|
|
8000b2a: bf00 nop
|
|
|
|
08000b2c <__aeabi_dcmpun>:
|
|
8000b2c: ea4f 0c41 mov.w ip, r1, lsl #1
|
|
8000b30: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000b34: d102 bne.n 8000b3c <__aeabi_dcmpun+0x10>
|
|
8000b36: ea50 3c01 orrs.w ip, r0, r1, lsl #12
|
|
8000b3a: d10a bne.n 8000b52 <__aeabi_dcmpun+0x26>
|
|
8000b3c: ea4f 0c43 mov.w ip, r3, lsl #1
|
|
8000b40: ea7f 5c6c mvns.w ip, ip, asr #21
|
|
8000b44: d102 bne.n 8000b4c <__aeabi_dcmpun+0x20>
|
|
8000b46: ea52 3c03 orrs.w ip, r2, r3, lsl #12
|
|
8000b4a: d102 bne.n 8000b52 <__aeabi_dcmpun+0x26>
|
|
8000b4c: f04f 0000 mov.w r0, #0
|
|
8000b50: 4770 bx lr
|
|
8000b52: f04f 0001 mov.w r0, #1
|
|
8000b56: 4770 bx lr
|
|
|
|
08000b58 <__aeabi_d2iz>:
|
|
8000b58: ea4f 0241 mov.w r2, r1, lsl #1
|
|
8000b5c: f512 1200 adds.w r2, r2, #2097152 @ 0x200000
|
|
8000b60: d215 bcs.n 8000b8e <__aeabi_d2iz+0x36>
|
|
8000b62: d511 bpl.n 8000b88 <__aeabi_d2iz+0x30>
|
|
8000b64: f46f 7378 mvn.w r3, #992 @ 0x3e0
|
|
8000b68: ebb3 5262 subs.w r2, r3, r2, asr #21
|
|
8000b6c: d912 bls.n 8000b94 <__aeabi_d2iz+0x3c>
|
|
8000b6e: ea4f 23c1 mov.w r3, r1, lsl #11
|
|
8000b72: f043 4300 orr.w r3, r3, #2147483648 @ 0x80000000
|
|
8000b76: ea43 5350 orr.w r3, r3, r0, lsr #21
|
|
8000b7a: f011 4f00 tst.w r1, #2147483648 @ 0x80000000
|
|
8000b7e: fa23 f002 lsr.w r0, r3, r2
|
|
8000b82: bf18 it ne
|
|
8000b84: 4240 negne r0, r0
|
|
8000b86: 4770 bx lr
|
|
8000b88: f04f 0000 mov.w r0, #0
|
|
8000b8c: 4770 bx lr
|
|
8000b8e: ea50 3001 orrs.w r0, r0, r1, lsl #12
|
|
8000b92: d105 bne.n 8000ba0 <__aeabi_d2iz+0x48>
|
|
8000b94: f011 4000 ands.w r0, r1, #2147483648 @ 0x80000000
|
|
8000b98: bf08 it eq
|
|
8000b9a: f06f 4000 mvneq.w r0, #2147483648 @ 0x80000000
|
|
8000b9e: 4770 bx lr
|
|
8000ba0: f04f 0000 mov.w r0, #0
|
|
8000ba4: 4770 bx lr
|
|
8000ba6: bf00 nop
|
|
|
|
08000ba8 <__aeabi_d2f>:
|
|
8000ba8: ea4f 0241 mov.w r2, r1, lsl #1
|
|
8000bac: f1b2 43e0 subs.w r3, r2, #1879048192 @ 0x70000000
|
|
8000bb0: bf24 itt cs
|
|
8000bb2: f5b3 1c00 subscs.w ip, r3, #2097152 @ 0x200000
|
|
8000bb6: f1dc 5cfe rsbscs ip, ip, #532676608 @ 0x1fc00000
|
|
8000bba: d90d bls.n 8000bd8 <__aeabi_d2f+0x30>
|
|
8000bbc: f001 4c00 and.w ip, r1, #2147483648 @ 0x80000000
|
|
8000bc0: ea4f 02c0 mov.w r2, r0, lsl #3
|
|
8000bc4: ea4c 7050 orr.w r0, ip, r0, lsr #29
|
|
8000bc8: f1b2 4f00 cmp.w r2, #2147483648 @ 0x80000000
|
|
8000bcc: eb40 0083 adc.w r0, r0, r3, lsl #2
|
|
8000bd0: bf08 it eq
|
|
8000bd2: f020 0001 biceq.w r0, r0, #1
|
|
8000bd6: 4770 bx lr
|
|
8000bd8: f011 4f80 tst.w r1, #1073741824 @ 0x40000000
|
|
8000bdc: d121 bne.n 8000c22 <__aeabi_d2f+0x7a>
|
|
8000bde: f113 7238 adds.w r2, r3, #48234496 @ 0x2e00000
|
|
8000be2: bfbc itt lt
|
|
8000be4: f001 4000 andlt.w r0, r1, #2147483648 @ 0x80000000
|
|
8000be8: 4770 bxlt lr
|
|
8000bea: f441 1180 orr.w r1, r1, #1048576 @ 0x100000
|
|
8000bee: ea4f 5252 mov.w r2, r2, lsr #21
|
|
8000bf2: f1c2 0218 rsb r2, r2, #24
|
|
8000bf6: f1c2 0c20 rsb ip, r2, #32
|
|
8000bfa: fa10 f30c lsls.w r3, r0, ip
|
|
8000bfe: fa20 f002 lsr.w r0, r0, r2
|
|
8000c02: bf18 it ne
|
|
8000c04: f040 0001 orrne.w r0, r0, #1
|
|
8000c08: ea4f 23c1 mov.w r3, r1, lsl #11
|
|
8000c0c: ea4f 23d3 mov.w r3, r3, lsr #11
|
|
8000c10: fa03 fc0c lsl.w ip, r3, ip
|
|
8000c14: ea40 000c orr.w r0, r0, ip
|
|
8000c18: fa23 f302 lsr.w r3, r3, r2
|
|
8000c1c: ea4f 0343 mov.w r3, r3, lsl #1
|
|
8000c20: e7cc b.n 8000bbc <__aeabi_d2f+0x14>
|
|
8000c22: ea7f 5362 mvns.w r3, r2, asr #21
|
|
8000c26: d107 bne.n 8000c38 <__aeabi_d2f+0x90>
|
|
8000c28: ea50 3301 orrs.w r3, r0, r1, lsl #12
|
|
8000c2c: bf1e ittt ne
|
|
8000c2e: f04f 40fe movne.w r0, #2130706432 @ 0x7f000000
|
|
8000c32: f440 0040 orrne.w r0, r0, #12582912 @ 0xc00000
|
|
8000c36: 4770 bxne lr
|
|
8000c38: f001 4000 and.w r0, r1, #2147483648 @ 0x80000000
|
|
8000c3c: f040 40fe orr.w r0, r0, #2130706432 @ 0x7f000000
|
|
8000c40: f440 0000 orr.w r0, r0, #8388608 @ 0x800000
|
|
8000c44: 4770 bx lr
|
|
8000c46: bf00 nop
|
|
|
|
08000c48 <__aeabi_uldivmod>:
|
|
8000c48: b953 cbnz r3, 8000c60 <__aeabi_uldivmod+0x18>
|
|
8000c4a: b94a cbnz r2, 8000c60 <__aeabi_uldivmod+0x18>
|
|
8000c4c: 2900 cmp r1, #0
|
|
8000c4e: bf08 it eq
|
|
8000c50: 2800 cmpeq r0, #0
|
|
8000c52: bf1c itt ne
|
|
8000c54: f04f 31ff movne.w r1, #4294967295 @ 0xffffffff
|
|
8000c58: f04f 30ff movne.w r0, #4294967295 @ 0xffffffff
|
|
8000c5c: f000 b988 b.w 8000f70 <__aeabi_idiv0>
|
|
8000c60: f1ad 0c08 sub.w ip, sp, #8
|
|
8000c64: e96d ce04 strd ip, lr, [sp, #-16]!
|
|
8000c68: f000 f806 bl 8000c78 <__udivmoddi4>
|
|
8000c6c: f8dd e004 ldr.w lr, [sp, #4]
|
|
8000c70: e9dd 2302 ldrd r2, r3, [sp, #8]
|
|
8000c74: b004 add sp, #16
|
|
8000c76: 4770 bx lr
|
|
|
|
08000c78 <__udivmoddi4>:
|
|
8000c78: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
8000c7c: 9d08 ldr r5, [sp, #32]
|
|
8000c7e: 468e mov lr, r1
|
|
8000c80: 4604 mov r4, r0
|
|
8000c82: 4688 mov r8, r1
|
|
8000c84: 2b00 cmp r3, #0
|
|
8000c86: d14a bne.n 8000d1e <__udivmoddi4+0xa6>
|
|
8000c88: 428a cmp r2, r1
|
|
8000c8a: 4617 mov r7, r2
|
|
8000c8c: d962 bls.n 8000d54 <__udivmoddi4+0xdc>
|
|
8000c8e: fab2 f682 clz r6, r2
|
|
8000c92: b14e cbz r6, 8000ca8 <__udivmoddi4+0x30>
|
|
8000c94: f1c6 0320 rsb r3, r6, #32
|
|
8000c98: fa01 f806 lsl.w r8, r1, r6
|
|
8000c9c: fa20 f303 lsr.w r3, r0, r3
|
|
8000ca0: 40b7 lsls r7, r6
|
|
8000ca2: ea43 0808 orr.w r8, r3, r8
|
|
8000ca6: 40b4 lsls r4, r6
|
|
8000ca8: ea4f 4e17 mov.w lr, r7, lsr #16
|
|
8000cac: fa1f fc87 uxth.w ip, r7
|
|
8000cb0: fbb8 f1fe udiv r1, r8, lr
|
|
8000cb4: 0c23 lsrs r3, r4, #16
|
|
8000cb6: fb0e 8811 mls r8, lr, r1, r8
|
|
8000cba: ea43 4308 orr.w r3, r3, r8, lsl #16
|
|
8000cbe: fb01 f20c mul.w r2, r1, ip
|
|
8000cc2: 429a cmp r2, r3
|
|
8000cc4: d909 bls.n 8000cda <__udivmoddi4+0x62>
|
|
8000cc6: 18fb adds r3, r7, r3
|
|
8000cc8: f101 30ff add.w r0, r1, #4294967295 @ 0xffffffff
|
|
8000ccc: f080 80ea bcs.w 8000ea4 <__udivmoddi4+0x22c>
|
|
8000cd0: 429a cmp r2, r3
|
|
8000cd2: f240 80e7 bls.w 8000ea4 <__udivmoddi4+0x22c>
|
|
8000cd6: 3902 subs r1, #2
|
|
8000cd8: 443b add r3, r7
|
|
8000cda: 1a9a subs r2, r3, r2
|
|
8000cdc: b2a3 uxth r3, r4
|
|
8000cde: fbb2 f0fe udiv r0, r2, lr
|
|
8000ce2: fb0e 2210 mls r2, lr, r0, r2
|
|
8000ce6: ea43 4302 orr.w r3, r3, r2, lsl #16
|
|
8000cea: fb00 fc0c mul.w ip, r0, ip
|
|
8000cee: 459c cmp ip, r3
|
|
8000cf0: d909 bls.n 8000d06 <__udivmoddi4+0x8e>
|
|
8000cf2: 18fb adds r3, r7, r3
|
|
8000cf4: f100 32ff add.w r2, r0, #4294967295 @ 0xffffffff
|
|
8000cf8: f080 80d6 bcs.w 8000ea8 <__udivmoddi4+0x230>
|
|
8000cfc: 459c cmp ip, r3
|
|
8000cfe: f240 80d3 bls.w 8000ea8 <__udivmoddi4+0x230>
|
|
8000d02: 443b add r3, r7
|
|
8000d04: 3802 subs r0, #2
|
|
8000d06: ea40 4001 orr.w r0, r0, r1, lsl #16
|
|
8000d0a: eba3 030c sub.w r3, r3, ip
|
|
8000d0e: 2100 movs r1, #0
|
|
8000d10: b11d cbz r5, 8000d1a <__udivmoddi4+0xa2>
|
|
8000d12: 40f3 lsrs r3, r6
|
|
8000d14: 2200 movs r2, #0
|
|
8000d16: e9c5 3200 strd r3, r2, [r5]
|
|
8000d1a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
8000d1e: 428b cmp r3, r1
|
|
8000d20: d905 bls.n 8000d2e <__udivmoddi4+0xb6>
|
|
8000d22: b10d cbz r5, 8000d28 <__udivmoddi4+0xb0>
|
|
8000d24: e9c5 0100 strd r0, r1, [r5]
|
|
8000d28: 2100 movs r1, #0
|
|
8000d2a: 4608 mov r0, r1
|
|
8000d2c: e7f5 b.n 8000d1a <__udivmoddi4+0xa2>
|
|
8000d2e: fab3 f183 clz r1, r3
|
|
8000d32: 2900 cmp r1, #0
|
|
8000d34: d146 bne.n 8000dc4 <__udivmoddi4+0x14c>
|
|
8000d36: 4573 cmp r3, lr
|
|
8000d38: d302 bcc.n 8000d40 <__udivmoddi4+0xc8>
|
|
8000d3a: 4282 cmp r2, r0
|
|
8000d3c: f200 8105 bhi.w 8000f4a <__udivmoddi4+0x2d2>
|
|
8000d40: 1a84 subs r4, r0, r2
|
|
8000d42: eb6e 0203 sbc.w r2, lr, r3
|
|
8000d46: 2001 movs r0, #1
|
|
8000d48: 4690 mov r8, r2
|
|
8000d4a: 2d00 cmp r5, #0
|
|
8000d4c: d0e5 beq.n 8000d1a <__udivmoddi4+0xa2>
|
|
8000d4e: e9c5 4800 strd r4, r8, [r5]
|
|
8000d52: e7e2 b.n 8000d1a <__udivmoddi4+0xa2>
|
|
8000d54: 2a00 cmp r2, #0
|
|
8000d56: f000 8090 beq.w 8000e7a <__udivmoddi4+0x202>
|
|
8000d5a: fab2 f682 clz r6, r2
|
|
8000d5e: 2e00 cmp r6, #0
|
|
8000d60: f040 80a4 bne.w 8000eac <__udivmoddi4+0x234>
|
|
8000d64: 1a8a subs r2, r1, r2
|
|
8000d66: 0c03 lsrs r3, r0, #16
|
|
8000d68: ea4f 4e17 mov.w lr, r7, lsr #16
|
|
8000d6c: b280 uxth r0, r0
|
|
8000d6e: b2bc uxth r4, r7
|
|
8000d70: 2101 movs r1, #1
|
|
8000d72: fbb2 fcfe udiv ip, r2, lr
|
|
8000d76: fb0e 221c mls r2, lr, ip, r2
|
|
8000d7a: ea43 4302 orr.w r3, r3, r2, lsl #16
|
|
8000d7e: fb04 f20c mul.w r2, r4, ip
|
|
8000d82: 429a cmp r2, r3
|
|
8000d84: d907 bls.n 8000d96 <__udivmoddi4+0x11e>
|
|
8000d86: 18fb adds r3, r7, r3
|
|
8000d88: f10c 38ff add.w r8, ip, #4294967295 @ 0xffffffff
|
|
8000d8c: d202 bcs.n 8000d94 <__udivmoddi4+0x11c>
|
|
8000d8e: 429a cmp r2, r3
|
|
8000d90: f200 80e0 bhi.w 8000f54 <__udivmoddi4+0x2dc>
|
|
8000d94: 46c4 mov ip, r8
|
|
8000d96: 1a9b subs r3, r3, r2
|
|
8000d98: fbb3 f2fe udiv r2, r3, lr
|
|
8000d9c: fb0e 3312 mls r3, lr, r2, r3
|
|
8000da0: ea40 4303 orr.w r3, r0, r3, lsl #16
|
|
8000da4: fb02 f404 mul.w r4, r2, r4
|
|
8000da8: 429c cmp r4, r3
|
|
8000daa: d907 bls.n 8000dbc <__udivmoddi4+0x144>
|
|
8000dac: 18fb adds r3, r7, r3
|
|
8000dae: f102 30ff add.w r0, r2, #4294967295 @ 0xffffffff
|
|
8000db2: d202 bcs.n 8000dba <__udivmoddi4+0x142>
|
|
8000db4: 429c cmp r4, r3
|
|
8000db6: f200 80ca bhi.w 8000f4e <__udivmoddi4+0x2d6>
|
|
8000dba: 4602 mov r2, r0
|
|
8000dbc: 1b1b subs r3, r3, r4
|
|
8000dbe: ea42 400c orr.w r0, r2, ip, lsl #16
|
|
8000dc2: e7a5 b.n 8000d10 <__udivmoddi4+0x98>
|
|
8000dc4: f1c1 0620 rsb r6, r1, #32
|
|
8000dc8: 408b lsls r3, r1
|
|
8000dca: fa22 f706 lsr.w r7, r2, r6
|
|
8000dce: 431f orrs r7, r3
|
|
8000dd0: fa0e f401 lsl.w r4, lr, r1
|
|
8000dd4: fa20 f306 lsr.w r3, r0, r6
|
|
8000dd8: fa2e fe06 lsr.w lr, lr, r6
|
|
8000ddc: ea4f 4917 mov.w r9, r7, lsr #16
|
|
8000de0: 4323 orrs r3, r4
|
|
8000de2: fa00 f801 lsl.w r8, r0, r1
|
|
8000de6: fa1f fc87 uxth.w ip, r7
|
|
8000dea: fbbe f0f9 udiv r0, lr, r9
|
|
8000dee: 0c1c lsrs r4, r3, #16
|
|
8000df0: fb09 ee10 mls lr, r9, r0, lr
|
|
8000df4: ea44 440e orr.w r4, r4, lr, lsl #16
|
|
8000df8: fb00 fe0c mul.w lr, r0, ip
|
|
8000dfc: 45a6 cmp lr, r4
|
|
8000dfe: fa02 f201 lsl.w r2, r2, r1
|
|
8000e02: d909 bls.n 8000e18 <__udivmoddi4+0x1a0>
|
|
8000e04: 193c adds r4, r7, r4
|
|
8000e06: f100 3aff add.w sl, r0, #4294967295 @ 0xffffffff
|
|
8000e0a: f080 809c bcs.w 8000f46 <__udivmoddi4+0x2ce>
|
|
8000e0e: 45a6 cmp lr, r4
|
|
8000e10: f240 8099 bls.w 8000f46 <__udivmoddi4+0x2ce>
|
|
8000e14: 3802 subs r0, #2
|
|
8000e16: 443c add r4, r7
|
|
8000e18: eba4 040e sub.w r4, r4, lr
|
|
8000e1c: fa1f fe83 uxth.w lr, r3
|
|
8000e20: fbb4 f3f9 udiv r3, r4, r9
|
|
8000e24: fb09 4413 mls r4, r9, r3, r4
|
|
8000e28: ea4e 4404 orr.w r4, lr, r4, lsl #16
|
|
8000e2c: fb03 fc0c mul.w ip, r3, ip
|
|
8000e30: 45a4 cmp ip, r4
|
|
8000e32: d908 bls.n 8000e46 <__udivmoddi4+0x1ce>
|
|
8000e34: 193c adds r4, r7, r4
|
|
8000e36: f103 3eff add.w lr, r3, #4294967295 @ 0xffffffff
|
|
8000e3a: f080 8082 bcs.w 8000f42 <__udivmoddi4+0x2ca>
|
|
8000e3e: 45a4 cmp ip, r4
|
|
8000e40: d97f bls.n 8000f42 <__udivmoddi4+0x2ca>
|
|
8000e42: 3b02 subs r3, #2
|
|
8000e44: 443c add r4, r7
|
|
8000e46: ea43 4000 orr.w r0, r3, r0, lsl #16
|
|
8000e4a: eba4 040c sub.w r4, r4, ip
|
|
8000e4e: fba0 ec02 umull lr, ip, r0, r2
|
|
8000e52: 4564 cmp r4, ip
|
|
8000e54: 4673 mov r3, lr
|
|
8000e56: 46e1 mov r9, ip
|
|
8000e58: d362 bcc.n 8000f20 <__udivmoddi4+0x2a8>
|
|
8000e5a: d05f beq.n 8000f1c <__udivmoddi4+0x2a4>
|
|
8000e5c: b15d cbz r5, 8000e76 <__udivmoddi4+0x1fe>
|
|
8000e5e: ebb8 0203 subs.w r2, r8, r3
|
|
8000e62: eb64 0409 sbc.w r4, r4, r9
|
|
8000e66: fa04 f606 lsl.w r6, r4, r6
|
|
8000e6a: fa22 f301 lsr.w r3, r2, r1
|
|
8000e6e: 431e orrs r6, r3
|
|
8000e70: 40cc lsrs r4, r1
|
|
8000e72: e9c5 6400 strd r6, r4, [r5]
|
|
8000e76: 2100 movs r1, #0
|
|
8000e78: e74f b.n 8000d1a <__udivmoddi4+0xa2>
|
|
8000e7a: fbb1 fcf2 udiv ip, r1, r2
|
|
8000e7e: 0c01 lsrs r1, r0, #16
|
|
8000e80: ea41 410e orr.w r1, r1, lr, lsl #16
|
|
8000e84: b280 uxth r0, r0
|
|
8000e86: ea40 4201 orr.w r2, r0, r1, lsl #16
|
|
8000e8a: 463b mov r3, r7
|
|
8000e8c: 4638 mov r0, r7
|
|
8000e8e: 463c mov r4, r7
|
|
8000e90: 46b8 mov r8, r7
|
|
8000e92: 46be mov lr, r7
|
|
8000e94: 2620 movs r6, #32
|
|
8000e96: fbb1 f1f7 udiv r1, r1, r7
|
|
8000e9a: eba2 0208 sub.w r2, r2, r8
|
|
8000e9e: ea41 410c orr.w r1, r1, ip, lsl #16
|
|
8000ea2: e766 b.n 8000d72 <__udivmoddi4+0xfa>
|
|
8000ea4: 4601 mov r1, r0
|
|
8000ea6: e718 b.n 8000cda <__udivmoddi4+0x62>
|
|
8000ea8: 4610 mov r0, r2
|
|
8000eaa: e72c b.n 8000d06 <__udivmoddi4+0x8e>
|
|
8000eac: f1c6 0220 rsb r2, r6, #32
|
|
8000eb0: fa2e f302 lsr.w r3, lr, r2
|
|
8000eb4: 40b7 lsls r7, r6
|
|
8000eb6: 40b1 lsls r1, r6
|
|
8000eb8: fa20 f202 lsr.w r2, r0, r2
|
|
8000ebc: ea4f 4e17 mov.w lr, r7, lsr #16
|
|
8000ec0: 430a orrs r2, r1
|
|
8000ec2: fbb3 f8fe udiv r8, r3, lr
|
|
8000ec6: b2bc uxth r4, r7
|
|
8000ec8: fb0e 3318 mls r3, lr, r8, r3
|
|
8000ecc: 0c11 lsrs r1, r2, #16
|
|
8000ece: ea41 4103 orr.w r1, r1, r3, lsl #16
|
|
8000ed2: fb08 f904 mul.w r9, r8, r4
|
|
8000ed6: 40b0 lsls r0, r6
|
|
8000ed8: 4589 cmp r9, r1
|
|
8000eda: ea4f 4310 mov.w r3, r0, lsr #16
|
|
8000ede: b280 uxth r0, r0
|
|
8000ee0: d93e bls.n 8000f60 <__udivmoddi4+0x2e8>
|
|
8000ee2: 1879 adds r1, r7, r1
|
|
8000ee4: f108 3cff add.w ip, r8, #4294967295 @ 0xffffffff
|
|
8000ee8: d201 bcs.n 8000eee <__udivmoddi4+0x276>
|
|
8000eea: 4589 cmp r9, r1
|
|
8000eec: d81f bhi.n 8000f2e <__udivmoddi4+0x2b6>
|
|
8000eee: eba1 0109 sub.w r1, r1, r9
|
|
8000ef2: fbb1 f9fe udiv r9, r1, lr
|
|
8000ef6: fb09 f804 mul.w r8, r9, r4
|
|
8000efa: fb0e 1119 mls r1, lr, r9, r1
|
|
8000efe: b292 uxth r2, r2
|
|
8000f00: ea42 4201 orr.w r2, r2, r1, lsl #16
|
|
8000f04: 4542 cmp r2, r8
|
|
8000f06: d229 bcs.n 8000f5c <__udivmoddi4+0x2e4>
|
|
8000f08: 18ba adds r2, r7, r2
|
|
8000f0a: f109 31ff add.w r1, r9, #4294967295 @ 0xffffffff
|
|
8000f0e: d2c4 bcs.n 8000e9a <__udivmoddi4+0x222>
|
|
8000f10: 4542 cmp r2, r8
|
|
8000f12: d2c2 bcs.n 8000e9a <__udivmoddi4+0x222>
|
|
8000f14: f1a9 0102 sub.w r1, r9, #2
|
|
8000f18: 443a add r2, r7
|
|
8000f1a: e7be b.n 8000e9a <__udivmoddi4+0x222>
|
|
8000f1c: 45f0 cmp r8, lr
|
|
8000f1e: d29d bcs.n 8000e5c <__udivmoddi4+0x1e4>
|
|
8000f20: ebbe 0302 subs.w r3, lr, r2
|
|
8000f24: eb6c 0c07 sbc.w ip, ip, r7
|
|
8000f28: 3801 subs r0, #1
|
|
8000f2a: 46e1 mov r9, ip
|
|
8000f2c: e796 b.n 8000e5c <__udivmoddi4+0x1e4>
|
|
8000f2e: eba7 0909 sub.w r9, r7, r9
|
|
8000f32: 4449 add r1, r9
|
|
8000f34: f1a8 0c02 sub.w ip, r8, #2
|
|
8000f38: fbb1 f9fe udiv r9, r1, lr
|
|
8000f3c: fb09 f804 mul.w r8, r9, r4
|
|
8000f40: e7db b.n 8000efa <__udivmoddi4+0x282>
|
|
8000f42: 4673 mov r3, lr
|
|
8000f44: e77f b.n 8000e46 <__udivmoddi4+0x1ce>
|
|
8000f46: 4650 mov r0, sl
|
|
8000f48: e766 b.n 8000e18 <__udivmoddi4+0x1a0>
|
|
8000f4a: 4608 mov r0, r1
|
|
8000f4c: e6fd b.n 8000d4a <__udivmoddi4+0xd2>
|
|
8000f4e: 443b add r3, r7
|
|
8000f50: 3a02 subs r2, #2
|
|
8000f52: e733 b.n 8000dbc <__udivmoddi4+0x144>
|
|
8000f54: f1ac 0c02 sub.w ip, ip, #2
|
|
8000f58: 443b add r3, r7
|
|
8000f5a: e71c b.n 8000d96 <__udivmoddi4+0x11e>
|
|
8000f5c: 4649 mov r1, r9
|
|
8000f5e: e79c b.n 8000e9a <__udivmoddi4+0x222>
|
|
8000f60: eba1 0109 sub.w r1, r1, r9
|
|
8000f64: 46c4 mov ip, r8
|
|
8000f66: fbb1 f9fe udiv r9, r1, lr
|
|
8000f6a: fb09 f804 mul.w r8, r9, r4
|
|
8000f6e: e7c4 b.n 8000efa <__udivmoddi4+0x282>
|
|
|
|
08000f70 <__aeabi_idiv0>:
|
|
8000f70: 4770 bx lr
|
|
8000f72: bf00 nop
|
|
|
|
08000f74 <HTS221_UpdateCalibration>:
|
|
|
|
#define HTS_T1_OUT_LSB 0x3E
|
|
#define HTS_T1_OUT_MSB 0x3F
|
|
|
|
|
|
void HTS221_UpdateCalibration(){
|
|
8000f74: b580 push {r7, lr}
|
|
8000f76: b086 sub sp, #24
|
|
8000f78: af04 add r7, sp, #16
|
|
uint8_t buffer;
|
|
uint8_t tempMSB;
|
|
|
|
|
|
HAL_I2C_Mem_Read(&hi2c2, I2C_TH, HTS_H0_rH_x2, I2C_MEMADD_SIZE_8BIT, &buffer, 1, 1000);
|
|
8000f7a: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
8000f7e: 9302 str r3, [sp, #8]
|
|
8000f80: 2301 movs r3, #1
|
|
8000f82: 9301 str r3, [sp, #4]
|
|
8000f84: 1dfb adds r3, r7, #7
|
|
8000f86: 9300 str r3, [sp, #0]
|
|
8000f88: 2301 movs r3, #1
|
|
8000f8a: 2230 movs r2, #48 @ 0x30
|
|
8000f8c: 21be movs r1, #190 @ 0xbe
|
|
8000f8e: 48af ldr r0, [pc, #700] @ (800124c <HTS221_UpdateCalibration+0x2d8>)
|
|
8000f90: f001 ff96 bl 8002ec0 <HAL_I2C_Mem_Read>
|
|
hts_cal.H0_rH_x2 = buffer / 2.0f;
|
|
8000f94: 79fb ldrb r3, [r7, #7]
|
|
8000f96: ee07 3a90 vmov s15, r3
|
|
8000f9a: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
8000f9e: eef0 6a00 vmov.f32 s13, #0 @ 0x40000000 2.0
|
|
8000fa2: eec7 7a26 vdiv.f32 s15, s14, s13
|
|
8000fa6: 4baa ldr r3, [pc, #680] @ (8001250 <HTS221_UpdateCalibration+0x2dc>)
|
|
8000fa8: edc3 7a00 vstr s15, [r3]
|
|
|
|
HAL_I2C_Mem_Read(&hi2c2, I2C_TH, HTS_H1_rH_x2, I2C_MEMADD_SIZE_8BIT, &buffer, 1, 1000);
|
|
8000fac: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
8000fb0: 9302 str r3, [sp, #8]
|
|
8000fb2: 2301 movs r3, #1
|
|
8000fb4: 9301 str r3, [sp, #4]
|
|
8000fb6: 1dfb adds r3, r7, #7
|
|
8000fb8: 9300 str r3, [sp, #0]
|
|
8000fba: 2301 movs r3, #1
|
|
8000fbc: 2231 movs r2, #49 @ 0x31
|
|
8000fbe: 21be movs r1, #190 @ 0xbe
|
|
8000fc0: 48a2 ldr r0, [pc, #648] @ (800124c <HTS221_UpdateCalibration+0x2d8>)
|
|
8000fc2: f001 ff7d bl 8002ec0 <HAL_I2C_Mem_Read>
|
|
hts_cal.H1_rH_x2 = buffer / 2.0f;
|
|
8000fc6: 79fb ldrb r3, [r7, #7]
|
|
8000fc8: ee07 3a90 vmov s15, r3
|
|
8000fcc: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
8000fd0: eef0 6a00 vmov.f32 s13, #0 @ 0x40000000 2.0
|
|
8000fd4: eec7 7a26 vdiv.f32 s15, s14, s13
|
|
8000fd8: 4b9d ldr r3, [pc, #628] @ (8001250 <HTS221_UpdateCalibration+0x2dc>)
|
|
8000fda: edc3 7a01 vstr s15, [r3, #4]
|
|
|
|
HAL_I2C_Mem_Read(&hi2c2, I2C_TH, HTS_T1_T0_MSB, I2C_MEMADD_SIZE_8BIT, &tempMSB, 1, 1000);
|
|
8000fde: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
8000fe2: 9302 str r3, [sp, #8]
|
|
8000fe4: 2301 movs r3, #1
|
|
8000fe6: 9301 str r3, [sp, #4]
|
|
8000fe8: 1dbb adds r3, r7, #6
|
|
8000fea: 9300 str r3, [sp, #0]
|
|
8000fec: 2301 movs r3, #1
|
|
8000fee: 2235 movs r2, #53 @ 0x35
|
|
8000ff0: 21be movs r1, #190 @ 0xbe
|
|
8000ff2: 4896 ldr r0, [pc, #600] @ (800124c <HTS221_UpdateCalibration+0x2d8>)
|
|
8000ff4: f001 ff64 bl 8002ec0 <HAL_I2C_Mem_Read>
|
|
|
|
HAL_I2C_Mem_Read(&hi2c2, I2C_TH, HTS_T0_degC_x8, I2C_MEMADD_SIZE_8BIT, &buffer, 1, 1000);
|
|
8000ff8: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
8000ffc: 9302 str r3, [sp, #8]
|
|
8000ffe: 2301 movs r3, #1
|
|
8001000: 9301 str r3, [sp, #4]
|
|
8001002: 1dfb adds r3, r7, #7
|
|
8001004: 9300 str r3, [sp, #0]
|
|
8001006: 2301 movs r3, #1
|
|
8001008: 2232 movs r2, #50 @ 0x32
|
|
800100a: 21be movs r1, #190 @ 0xbe
|
|
800100c: 488f ldr r0, [pc, #572] @ (800124c <HTS221_UpdateCalibration+0x2d8>)
|
|
800100e: f001 ff57 bl 8002ec0 <HAL_I2C_Mem_Read>
|
|
hts_cal.T0_degC_x8 = (((tempMSB & 0x03) <<8) | buffer) / 8.0f ;
|
|
8001012: 79bb ldrb r3, [r7, #6]
|
|
8001014: 021b lsls r3, r3, #8
|
|
8001016: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
800101a: 79fa ldrb r2, [r7, #7]
|
|
800101c: 4313 orrs r3, r2
|
|
800101e: ee07 3a90 vmov s15, r3
|
|
8001022: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
8001026: eef2 6a00 vmov.f32 s13, #32 @ 0x41000000 8.0
|
|
800102a: eec7 7a26 vdiv.f32 s15, s14, s13
|
|
800102e: 4b88 ldr r3, [pc, #544] @ (8001250 <HTS221_UpdateCalibration+0x2dc>)
|
|
8001030: edc3 7a02 vstr s15, [r3, #8]
|
|
|
|
HAL_I2C_Mem_Read(&hi2c2, I2C_TH, HTS_T1_degC_x8, I2C_MEMADD_SIZE_8BIT, &buffer, 1, 1000);
|
|
8001034: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
8001038: 9302 str r3, [sp, #8]
|
|
800103a: 2301 movs r3, #1
|
|
800103c: 9301 str r3, [sp, #4]
|
|
800103e: 1dfb adds r3, r7, #7
|
|
8001040: 9300 str r3, [sp, #0]
|
|
8001042: 2301 movs r3, #1
|
|
8001044: 2233 movs r2, #51 @ 0x33
|
|
8001046: 21be movs r1, #190 @ 0xbe
|
|
8001048: 4880 ldr r0, [pc, #512] @ (800124c <HTS221_UpdateCalibration+0x2d8>)
|
|
800104a: f001 ff39 bl 8002ec0 <HAL_I2C_Mem_Read>
|
|
hts_cal.T1_degC_x8 = (((tempMSB & 0x0C) <<6) | buffer) / 8.0f ;
|
|
800104e: 79bb ldrb r3, [r7, #6]
|
|
8001050: 019b lsls r3, r3, #6
|
|
8001052: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
8001056: 79fa ldrb r2, [r7, #7]
|
|
8001058: 4313 orrs r3, r2
|
|
800105a: ee07 3a90 vmov s15, r3
|
|
800105e: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
8001062: eef2 6a00 vmov.f32 s13, #32 @ 0x41000000 8.0
|
|
8001066: eec7 7a26 vdiv.f32 s15, s14, s13
|
|
800106a: 4b79 ldr r3, [pc, #484] @ (8001250 <HTS221_UpdateCalibration+0x2dc>)
|
|
800106c: edc3 7a03 vstr s15, [r3, #12]
|
|
|
|
HAL_I2C_Mem_Read(&hi2c2, I2C_TH, HTS_H0_T0_OUT_LSB, I2C_MEMADD_SIZE_8BIT, &buffer, 1, 1000);
|
|
8001070: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
8001074: 9302 str r3, [sp, #8]
|
|
8001076: 2301 movs r3, #1
|
|
8001078: 9301 str r3, [sp, #4]
|
|
800107a: 1dfb adds r3, r7, #7
|
|
800107c: 9300 str r3, [sp, #0]
|
|
800107e: 2301 movs r3, #1
|
|
8001080: 2236 movs r2, #54 @ 0x36
|
|
8001082: 21be movs r1, #190 @ 0xbe
|
|
8001084: 4871 ldr r0, [pc, #452] @ (800124c <HTS221_UpdateCalibration+0x2d8>)
|
|
8001086: f001 ff1b bl 8002ec0 <HAL_I2C_Mem_Read>
|
|
HAL_I2C_Mem_Read(&hi2c2, I2C_TH, HTS_H0_T0_OUT_MSB, I2C_MEMADD_SIZE_8BIT, &tempMSB, 1, 1000);
|
|
800108a: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
800108e: 9302 str r3, [sp, #8]
|
|
8001090: 2301 movs r3, #1
|
|
8001092: 9301 str r3, [sp, #4]
|
|
8001094: 1dbb adds r3, r7, #6
|
|
8001096: 9300 str r3, [sp, #0]
|
|
8001098: 2301 movs r3, #1
|
|
800109a: 2237 movs r2, #55 @ 0x37
|
|
800109c: 21be movs r1, #190 @ 0xbe
|
|
800109e: 486b ldr r0, [pc, #428] @ (800124c <HTS221_UpdateCalibration+0x2d8>)
|
|
80010a0: f001 ff0e bl 8002ec0 <HAL_I2C_Mem_Read>
|
|
hts_cal.H0_T0_OUT = (tempMSB <<8) | buffer;
|
|
80010a4: 79bb ldrb r3, [r7, #6]
|
|
80010a6: b21b sxth r3, r3
|
|
80010a8: 021b lsls r3, r3, #8
|
|
80010aa: b21a sxth r2, r3
|
|
80010ac: 79fb ldrb r3, [r7, #7]
|
|
80010ae: b21b sxth r3, r3
|
|
80010b0: 4313 orrs r3, r2
|
|
80010b2: b21a sxth r2, r3
|
|
80010b4: 4b66 ldr r3, [pc, #408] @ (8001250 <HTS221_UpdateCalibration+0x2dc>)
|
|
80010b6: 821a strh r2, [r3, #16]
|
|
|
|
HAL_I2C_Mem_Read(&hi2c2, I2C_TH, HTS_H1_T0_OUT_LSB, I2C_MEMADD_SIZE_8BIT, &buffer, 1, 1000);
|
|
80010b8: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
80010bc: 9302 str r3, [sp, #8]
|
|
80010be: 2301 movs r3, #1
|
|
80010c0: 9301 str r3, [sp, #4]
|
|
80010c2: 1dfb adds r3, r7, #7
|
|
80010c4: 9300 str r3, [sp, #0]
|
|
80010c6: 2301 movs r3, #1
|
|
80010c8: 223a movs r2, #58 @ 0x3a
|
|
80010ca: 21be movs r1, #190 @ 0xbe
|
|
80010cc: 485f ldr r0, [pc, #380] @ (800124c <HTS221_UpdateCalibration+0x2d8>)
|
|
80010ce: f001 fef7 bl 8002ec0 <HAL_I2C_Mem_Read>
|
|
HAL_I2C_Mem_Read(&hi2c2, I2C_TH, HTS_H1_T0_OUT_MSB, I2C_MEMADD_SIZE_8BIT, &tempMSB, 1, 1000);
|
|
80010d2: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
80010d6: 9302 str r3, [sp, #8]
|
|
80010d8: 2301 movs r3, #1
|
|
80010da: 9301 str r3, [sp, #4]
|
|
80010dc: 1dbb adds r3, r7, #6
|
|
80010de: 9300 str r3, [sp, #0]
|
|
80010e0: 2301 movs r3, #1
|
|
80010e2: 223b movs r2, #59 @ 0x3b
|
|
80010e4: 21be movs r1, #190 @ 0xbe
|
|
80010e6: 4859 ldr r0, [pc, #356] @ (800124c <HTS221_UpdateCalibration+0x2d8>)
|
|
80010e8: f001 feea bl 8002ec0 <HAL_I2C_Mem_Read>
|
|
hts_cal.H1_T0_OUT = (tempMSB <<8) | buffer;
|
|
80010ec: 79bb ldrb r3, [r7, #6]
|
|
80010ee: b21b sxth r3, r3
|
|
80010f0: 021b lsls r3, r3, #8
|
|
80010f2: b21a sxth r2, r3
|
|
80010f4: 79fb ldrb r3, [r7, #7]
|
|
80010f6: b21b sxth r3, r3
|
|
80010f8: 4313 orrs r3, r2
|
|
80010fa: b21a sxth r2, r3
|
|
80010fc: 4b54 ldr r3, [pc, #336] @ (8001250 <HTS221_UpdateCalibration+0x2dc>)
|
|
80010fe: 825a strh r2, [r3, #18]
|
|
|
|
HAL_I2C_Mem_Read(&hi2c2, I2C_TH, HTS_T0_OUT_LSB, I2C_MEMADD_SIZE_8BIT, &buffer, 1, 1000);
|
|
8001100: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
8001104: 9302 str r3, [sp, #8]
|
|
8001106: 2301 movs r3, #1
|
|
8001108: 9301 str r3, [sp, #4]
|
|
800110a: 1dfb adds r3, r7, #7
|
|
800110c: 9300 str r3, [sp, #0]
|
|
800110e: 2301 movs r3, #1
|
|
8001110: 223c movs r2, #60 @ 0x3c
|
|
8001112: 21be movs r1, #190 @ 0xbe
|
|
8001114: 484d ldr r0, [pc, #308] @ (800124c <HTS221_UpdateCalibration+0x2d8>)
|
|
8001116: f001 fed3 bl 8002ec0 <HAL_I2C_Mem_Read>
|
|
HAL_I2C_Mem_Read(&hi2c2, I2C_TH, HTS_T0_OUT_MSB, I2C_MEMADD_SIZE_8BIT, &tempMSB, 1, 1000);
|
|
800111a: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
800111e: 9302 str r3, [sp, #8]
|
|
8001120: 2301 movs r3, #1
|
|
8001122: 9301 str r3, [sp, #4]
|
|
8001124: 1dbb adds r3, r7, #6
|
|
8001126: 9300 str r3, [sp, #0]
|
|
8001128: 2301 movs r3, #1
|
|
800112a: 223d movs r2, #61 @ 0x3d
|
|
800112c: 21be movs r1, #190 @ 0xbe
|
|
800112e: 4847 ldr r0, [pc, #284] @ (800124c <HTS221_UpdateCalibration+0x2d8>)
|
|
8001130: f001 fec6 bl 8002ec0 <HAL_I2C_Mem_Read>
|
|
hts_cal.T0_OUT = (tempMSB <<8) | buffer;
|
|
8001134: 79bb ldrb r3, [r7, #6]
|
|
8001136: b21b sxth r3, r3
|
|
8001138: 021b lsls r3, r3, #8
|
|
800113a: b21a sxth r2, r3
|
|
800113c: 79fb ldrb r3, [r7, #7]
|
|
800113e: b21b sxth r3, r3
|
|
8001140: 4313 orrs r3, r2
|
|
8001142: b21a sxth r2, r3
|
|
8001144: 4b42 ldr r3, [pc, #264] @ (8001250 <HTS221_UpdateCalibration+0x2dc>)
|
|
8001146: 829a strh r2, [r3, #20]
|
|
|
|
HAL_I2C_Mem_Read(&hi2c2, I2C_TH, HTS_T1_OUT_LSB, I2C_MEMADD_SIZE_8BIT, &buffer, 1, 1000);
|
|
8001148: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
800114c: 9302 str r3, [sp, #8]
|
|
800114e: 2301 movs r3, #1
|
|
8001150: 9301 str r3, [sp, #4]
|
|
8001152: 1dfb adds r3, r7, #7
|
|
8001154: 9300 str r3, [sp, #0]
|
|
8001156: 2301 movs r3, #1
|
|
8001158: 223e movs r2, #62 @ 0x3e
|
|
800115a: 21be movs r1, #190 @ 0xbe
|
|
800115c: 483b ldr r0, [pc, #236] @ (800124c <HTS221_UpdateCalibration+0x2d8>)
|
|
800115e: f001 feaf bl 8002ec0 <HAL_I2C_Mem_Read>
|
|
HAL_I2C_Mem_Read(&hi2c2, I2C_TH, HTS_T1_OUT_MSB, I2C_MEMADD_SIZE_8BIT, &tempMSB, 1, 1000);
|
|
8001162: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
8001166: 9302 str r3, [sp, #8]
|
|
8001168: 2301 movs r3, #1
|
|
800116a: 9301 str r3, [sp, #4]
|
|
800116c: 1dbb adds r3, r7, #6
|
|
800116e: 9300 str r3, [sp, #0]
|
|
8001170: 2301 movs r3, #1
|
|
8001172: 223f movs r2, #63 @ 0x3f
|
|
8001174: 21be movs r1, #190 @ 0xbe
|
|
8001176: 4835 ldr r0, [pc, #212] @ (800124c <HTS221_UpdateCalibration+0x2d8>)
|
|
8001178: f001 fea2 bl 8002ec0 <HAL_I2C_Mem_Read>
|
|
hts_cal.T1_OUT = (tempMSB <<8) | buffer;
|
|
800117c: 79bb ldrb r3, [r7, #6]
|
|
800117e: b21b sxth r3, r3
|
|
8001180: 021b lsls r3, r3, #8
|
|
8001182: b21a sxth r2, r3
|
|
8001184: 79fb ldrb r3, [r7, #7]
|
|
8001186: b21b sxth r3, r3
|
|
8001188: 4313 orrs r3, r2
|
|
800118a: b21a sxth r2, r3
|
|
800118c: 4b30 ldr r3, [pc, #192] @ (8001250 <HTS221_UpdateCalibration+0x2dc>)
|
|
800118e: 82da strh r2, [r3, #22]
|
|
|
|
|
|
hts_cal.ha = (hts_cal.H1_rH_x2 - hts_cal.H0_rH_x2) / (hts_cal.H1_T0_OUT - hts_cal.H0_T0_OUT);
|
|
8001190: 4b2f ldr r3, [pc, #188] @ (8001250 <HTS221_UpdateCalibration+0x2dc>)
|
|
8001192: ed93 7a01 vldr s14, [r3, #4]
|
|
8001196: 4b2e ldr r3, [pc, #184] @ (8001250 <HTS221_UpdateCalibration+0x2dc>)
|
|
8001198: edd3 7a00 vldr s15, [r3]
|
|
800119c: ee77 6a67 vsub.f32 s13, s14, s15
|
|
80011a0: 4b2b ldr r3, [pc, #172] @ (8001250 <HTS221_UpdateCalibration+0x2dc>)
|
|
80011a2: f9b3 3012 ldrsh.w r3, [r3, #18]
|
|
80011a6: 461a mov r2, r3
|
|
80011a8: 4b29 ldr r3, [pc, #164] @ (8001250 <HTS221_UpdateCalibration+0x2dc>)
|
|
80011aa: f9b3 3010 ldrsh.w r3, [r3, #16]
|
|
80011ae: 1ad3 subs r3, r2, r3
|
|
80011b0: ee07 3a90 vmov s15, r3
|
|
80011b4: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
80011b8: eec6 7a87 vdiv.f32 s15, s13, s14
|
|
80011bc: 4b24 ldr r3, [pc, #144] @ (8001250 <HTS221_UpdateCalibration+0x2dc>)
|
|
80011be: edc3 7a06 vstr s15, [r3, #24]
|
|
|
|
hts_cal.hb = hts_cal.H0_rH_x2 - hts_cal.ha*hts_cal.H0_T0_OUT;
|
|
80011c2: 4b23 ldr r3, [pc, #140] @ (8001250 <HTS221_UpdateCalibration+0x2dc>)
|
|
80011c4: ed93 7a00 vldr s14, [r3]
|
|
80011c8: 4b21 ldr r3, [pc, #132] @ (8001250 <HTS221_UpdateCalibration+0x2dc>)
|
|
80011ca: edd3 6a06 vldr s13, [r3, #24]
|
|
80011ce: 4b20 ldr r3, [pc, #128] @ (8001250 <HTS221_UpdateCalibration+0x2dc>)
|
|
80011d0: f9b3 3010 ldrsh.w r3, [r3, #16]
|
|
80011d4: ee07 3a90 vmov s15, r3
|
|
80011d8: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
80011dc: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
80011e0: ee77 7a67 vsub.f32 s15, s14, s15
|
|
80011e4: 4b1a ldr r3, [pc, #104] @ (8001250 <HTS221_UpdateCalibration+0x2dc>)
|
|
80011e6: edc3 7a07 vstr s15, [r3, #28]
|
|
|
|
hts_cal.ta = (hts_cal.T1_degC_x8 - hts_cal.T0_degC_x8) / (hts_cal.T1_OUT - hts_cal.T0_OUT);
|
|
80011ea: 4b19 ldr r3, [pc, #100] @ (8001250 <HTS221_UpdateCalibration+0x2dc>)
|
|
80011ec: ed93 7a03 vldr s14, [r3, #12]
|
|
80011f0: 4b17 ldr r3, [pc, #92] @ (8001250 <HTS221_UpdateCalibration+0x2dc>)
|
|
80011f2: edd3 7a02 vldr s15, [r3, #8]
|
|
80011f6: ee77 6a67 vsub.f32 s13, s14, s15
|
|
80011fa: 4b15 ldr r3, [pc, #84] @ (8001250 <HTS221_UpdateCalibration+0x2dc>)
|
|
80011fc: f9b3 3016 ldrsh.w r3, [r3, #22]
|
|
8001200: 461a mov r2, r3
|
|
8001202: 4b13 ldr r3, [pc, #76] @ (8001250 <HTS221_UpdateCalibration+0x2dc>)
|
|
8001204: f9b3 3014 ldrsh.w r3, [r3, #20]
|
|
8001208: 1ad3 subs r3, r2, r3
|
|
800120a: ee07 3a90 vmov s15, r3
|
|
800120e: eeb8 7ae7 vcvt.f32.s32 s14, s15
|
|
8001212: eec6 7a87 vdiv.f32 s15, s13, s14
|
|
8001216: 4b0e ldr r3, [pc, #56] @ (8001250 <HTS221_UpdateCalibration+0x2dc>)
|
|
8001218: edc3 7a08 vstr s15, [r3, #32]
|
|
|
|
hts_cal.tb = hts_cal.T0_degC_x8 - hts_cal.ha*hts_cal.T0_OUT;
|
|
800121c: 4b0c ldr r3, [pc, #48] @ (8001250 <HTS221_UpdateCalibration+0x2dc>)
|
|
800121e: ed93 7a02 vldr s14, [r3, #8]
|
|
8001222: 4b0b ldr r3, [pc, #44] @ (8001250 <HTS221_UpdateCalibration+0x2dc>)
|
|
8001224: edd3 6a06 vldr s13, [r3, #24]
|
|
8001228: 4b09 ldr r3, [pc, #36] @ (8001250 <HTS221_UpdateCalibration+0x2dc>)
|
|
800122a: f9b3 3014 ldrsh.w r3, [r3, #20]
|
|
800122e: ee07 3a90 vmov s15, r3
|
|
8001232: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
8001236: ee66 7aa7 vmul.f32 s15, s13, s15
|
|
800123a: ee77 7a67 vsub.f32 s15, s14, s15
|
|
800123e: 4b04 ldr r3, [pc, #16] @ (8001250 <HTS221_UpdateCalibration+0x2dc>)
|
|
8001240: edc3 7a09 vstr s15, [r3, #36] @ 0x24
|
|
|
|
}
|
|
8001244: bf00 nop
|
|
8001246: 3708 adds r7, #8
|
|
8001248: 46bd mov sp, r7
|
|
800124a: bd80 pop {r7, pc}
|
|
800124c: 20000238 .word 0x20000238
|
|
8001250: 20000204 .word 0x20000204
|
|
|
|
08001254 <HTS221_Init>:
|
|
|
|
void HTS221_Init() {
|
|
8001254: b580 push {r7, lr}
|
|
8001256: b086 sub sp, #24
|
|
8001258: af04 add r7, sp, #16
|
|
uint8_t buffer[1];
|
|
buffer[0] = 0x87;
|
|
800125a: 2387 movs r3, #135 @ 0x87
|
|
800125c: 713b strb r3, [r7, #4]
|
|
HAL_I2C_Mem_Write(&hi2c2, 0xBE, 0x20, I2C_MEMADD_SIZE_8BIT, buffer, 1, 1000);
|
|
800125e: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
8001262: 9302 str r3, [sp, #8]
|
|
8001264: 2301 movs r3, #1
|
|
8001266: 9301 str r3, [sp, #4]
|
|
8001268: 1d3b adds r3, r7, #4
|
|
800126a: 9300 str r3, [sp, #0]
|
|
800126c: 2301 movs r3, #1
|
|
800126e: 2220 movs r2, #32
|
|
8001270: 21be movs r1, #190 @ 0xbe
|
|
8001272: 4804 ldr r0, [pc, #16] @ (8001284 <HTS221_Init+0x30>)
|
|
8001274: f001 fd10 bl 8002c98 <HAL_I2C_Mem_Write>
|
|
HTS221_UpdateCalibration();
|
|
8001278: f7ff fe7c bl 8000f74 <HTS221_UpdateCalibration>
|
|
}
|
|
800127c: bf00 nop
|
|
800127e: 3708 adds r7, #8
|
|
8001280: 46bd mov sp, r7
|
|
8001282: bd80 pop {r7, pc}
|
|
8001284: 20000238 .word 0x20000238
|
|
|
|
08001288 <HTS221_Read>:
|
|
|
|
THSample HTS221_Read() {
|
|
8001288: b580 push {r7, lr}
|
|
800128a: b08c sub sp, #48 @ 0x30
|
|
800128c: af04 add r7, sp, #16
|
|
THSample ths;
|
|
|
|
uint8_t buffer[4];
|
|
HAL_I2C_Mem_Read(&hi2c2, 0xBE, 0x80 | 0x28, I2C_MEMADD_SIZE_8BIT, buffer, 4, 1000);
|
|
800128e: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
8001292: 9302 str r3, [sp, #8]
|
|
8001294: 2304 movs r3, #4
|
|
8001296: 9301 str r3, [sp, #4]
|
|
8001298: f107 0308 add.w r3, r7, #8
|
|
800129c: 9300 str r3, [sp, #0]
|
|
800129e: 2301 movs r3, #1
|
|
80012a0: 22a8 movs r2, #168 @ 0xa8
|
|
80012a2: 21be movs r1, #190 @ 0xbe
|
|
80012a4: 4825 ldr r0, [pc, #148] @ (800133c <HTS221_Read+0xb4>)
|
|
80012a6: f001 fe0b bl 8002ec0 <HAL_I2C_Mem_Read>
|
|
|
|
int16_t hum_raw;
|
|
int16_t temp_raw;
|
|
|
|
hum_raw = (buffer[1] << 8) | buffer[0];
|
|
80012aa: 7a7b ldrb r3, [r7, #9]
|
|
80012ac: b21b sxth r3, r3
|
|
80012ae: 021b lsls r3, r3, #8
|
|
80012b0: b21a sxth r2, r3
|
|
80012b2: 7a3b ldrb r3, [r7, #8]
|
|
80012b4: b21b sxth r3, r3
|
|
80012b6: 4313 orrs r3, r2
|
|
80012b8: 83fb strh r3, [r7, #30]
|
|
temp_raw = (buffer[3] << 8) | buffer[2];
|
|
80012ba: 7afb ldrb r3, [r7, #11]
|
|
80012bc: b21b sxth r3, r3
|
|
80012be: 021b lsls r3, r3, #8
|
|
80012c0: b21a sxth r2, r3
|
|
80012c2: 7abb ldrb r3, [r7, #10]
|
|
80012c4: b21b sxth r3, r3
|
|
80012c6: 4313 orrs r3, r2
|
|
80012c8: 83bb strh r3, [r7, #28]
|
|
|
|
ths.hum = hts_cal.ha * hum_raw + hts_cal.hb;
|
|
80012ca: 4b1d ldr r3, [pc, #116] @ (8001340 <HTS221_Read+0xb8>)
|
|
80012cc: ed93 7a06 vldr s14, [r3, #24]
|
|
80012d0: f9b7 301e ldrsh.w r3, [r7, #30]
|
|
80012d4: ee07 3a90 vmov s15, r3
|
|
80012d8: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
80012dc: ee27 7a27 vmul.f32 s14, s14, s15
|
|
80012e0: 4b17 ldr r3, [pc, #92] @ (8001340 <HTS221_Read+0xb8>)
|
|
80012e2: edd3 7a07 vldr s15, [r3, #28]
|
|
80012e6: ee77 7a27 vadd.f32 s15, s14, s15
|
|
80012ea: edc7 7a04 vstr s15, [r7, #16]
|
|
ths.temp = hts_cal.ta * temp_raw + hts_cal.tb;
|
|
80012ee: 4b14 ldr r3, [pc, #80] @ (8001340 <HTS221_Read+0xb8>)
|
|
80012f0: ed93 7a08 vldr s14, [r3, #32]
|
|
80012f4: f9b7 301c ldrsh.w r3, [r7, #28]
|
|
80012f8: ee07 3a90 vmov s15, r3
|
|
80012fc: eef8 7ae7 vcvt.f32.s32 s15, s15
|
|
8001300: ee27 7a27 vmul.f32 s14, s14, s15
|
|
8001304: 4b0e ldr r3, [pc, #56] @ (8001340 <HTS221_Read+0xb8>)
|
|
8001306: edd3 7a09 vldr s15, [r3, #36] @ 0x24
|
|
800130a: ee77 7a27 vadd.f32 s15, s14, s15
|
|
800130e: edc7 7a03 vstr s15, [r7, #12]
|
|
|
|
return ths;
|
|
8001312: f107 0314 add.w r3, r7, #20
|
|
8001316: f107 020c add.w r2, r7, #12
|
|
800131a: e892 0003 ldmia.w r2, {r0, r1}
|
|
800131e: e883 0003 stmia.w r3, {r0, r1}
|
|
|
|
return ths;
|
|
}
|
|
8001322: 697a ldr r2, [r7, #20]
|
|
8001324: 69bb ldr r3, [r7, #24]
|
|
8001326: ee07 2a10 vmov s14, r2
|
|
800132a: ee07 3a90 vmov s15, r3
|
|
800132e: eeb0 0a47 vmov.f32 s0, s14
|
|
8001332: eef0 0a67 vmov.f32 s1, s15
|
|
8001336: 3720 adds r7, #32
|
|
8001338: 46bd mov sp, r7
|
|
800133a: bd80 pop {r7, pc}
|
|
800133c: 20000238 .word 0x20000238
|
|
8001340: 20000204 .word 0x20000204
|
|
|
|
08001344 <LPS22_Init>:
|
|
#include "stm32l4xx_hal.h"
|
|
|
|
extern I2C_HandleTypeDef hi2c2;
|
|
|
|
void LPS22_Init() {
|
|
8001344: b580 push {r7, lr}
|
|
8001346: b086 sub sp, #24
|
|
8001348: af04 add r7, sp, #16
|
|
uint8_t buffer[1];
|
|
buffer[0] = 0x42;
|
|
800134a: 2342 movs r3, #66 @ 0x42
|
|
800134c: 713b strb r3, [r7, #4]
|
|
|
|
HAL_I2C_Mem_Write(&hi2c2, 0xBA, 0x10, I2C_MEMADD_SIZE_8BIT, buffer, 1 , 1000);
|
|
800134e: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
8001352: 9302 str r3, [sp, #8]
|
|
8001354: 2301 movs r3, #1
|
|
8001356: 9301 str r3, [sp, #4]
|
|
8001358: 1d3b adds r3, r7, #4
|
|
800135a: 9300 str r3, [sp, #0]
|
|
800135c: 2301 movs r3, #1
|
|
800135e: 2210 movs r2, #16
|
|
8001360: 21ba movs r1, #186 @ 0xba
|
|
8001362: 4803 ldr r0, [pc, #12] @ (8001370 <LPS22_Init+0x2c>)
|
|
8001364: f001 fc98 bl 8002c98 <HAL_I2C_Mem_Write>
|
|
}
|
|
8001368: bf00 nop
|
|
800136a: 3708 adds r7, #8
|
|
800136c: 46bd mov sp, r7
|
|
800136e: bd80 pop {r7, pc}
|
|
8001370: 20000238 .word 0x20000238
|
|
|
|
08001374 <LPS22_ReadPress>:
|
|
|
|
float LPS22_ReadPress() {
|
|
8001374: b580 push {r7, lr}
|
|
8001376: b088 sub sp, #32
|
|
8001378: af04 add r7, sp, #16
|
|
float press;
|
|
|
|
uint8_t buffer[3];
|
|
|
|
HAL_I2C_Mem_Read(&hi2c2, 0xBA, 0x28, I2C_MEMADD_SIZE_8BIT, buffer, 3, 1000);
|
|
800137a: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
800137e: 9302 str r3, [sp, #8]
|
|
8001380: 2303 movs r3, #3
|
|
8001382: 9301 str r3, [sp, #4]
|
|
8001384: 1d3b adds r3, r7, #4
|
|
8001386: 9300 str r3, [sp, #0]
|
|
8001388: 2301 movs r3, #1
|
|
800138a: 2228 movs r2, #40 @ 0x28
|
|
800138c: 21ba movs r1, #186 @ 0xba
|
|
800138e: 480f ldr r0, [pc, #60] @ (80013cc <LPS22_ReadPress+0x58>)
|
|
8001390: f001 fd96 bl 8002ec0 <HAL_I2C_Mem_Read>
|
|
|
|
uint32_t press_raw = (buffer[2] << 16) | (buffer[1] << 8) | buffer[0];
|
|
8001394: 79bb ldrb r3, [r7, #6]
|
|
8001396: 041a lsls r2, r3, #16
|
|
8001398: 797b ldrb r3, [r7, #5]
|
|
800139a: 021b lsls r3, r3, #8
|
|
800139c: 4313 orrs r3, r2
|
|
800139e: 793a ldrb r2, [r7, #4]
|
|
80013a0: 4313 orrs r3, r2
|
|
80013a2: 60fb str r3, [r7, #12]
|
|
|
|
press = press_raw / 4096.0f;
|
|
80013a4: 68fb ldr r3, [r7, #12]
|
|
80013a6: ee07 3a90 vmov s15, r3
|
|
80013aa: eeb8 7a67 vcvt.f32.u32 s14, s15
|
|
80013ae: eddf 6a08 vldr s13, [pc, #32] @ 80013d0 <LPS22_ReadPress+0x5c>
|
|
80013b2: eec7 7a26 vdiv.f32 s15, s14, s13
|
|
80013b6: edc7 7a02 vstr s15, [r7, #8]
|
|
|
|
return press;
|
|
80013ba: 68bb ldr r3, [r7, #8]
|
|
80013bc: ee07 3a90 vmov s15, r3
|
|
}
|
|
80013c0: eeb0 0a67 vmov.f32 s0, s15
|
|
80013c4: 3710 adds r7, #16
|
|
80013c6: 46bd mov sp, r7
|
|
80013c8: bd80 pop {r7, pc}
|
|
80013ca: bf00 nop
|
|
80013cc: 20000238 .word 0x20000238
|
|
80013d0: 45800000 .word 0x45800000
|
|
|
|
080013d4 <lcd_clock>:
|
|
uint8_t _lcd_line = 0;
|
|
|
|
|
|
|
|
void lcd_clock(void)
|
|
{
|
|
80013d4: b580 push {r7, lr}
|
|
80013d6: af00 add r7, sp, #0
|
|
// Pulse clock
|
|
HAL_GPIO_WritePin(CLOCK_PORT, LCD_CLOCK, 1);
|
|
80013d8: 2201 movs r2, #1
|
|
80013da: f44f 4100 mov.w r1, #32768 @ 0x8000
|
|
80013de: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
80013e2: f001 fba5 bl 8002b30 <HAL_GPIO_WritePin>
|
|
|
|
HAL_Delay(1);
|
|
80013e6: 2001 movs r0, #1
|
|
80013e8: f001 f844 bl 8002474 <HAL_Delay>
|
|
HAL_GPIO_WritePin(CLOCK_PORT, LCD_CLOCK, 0);
|
|
80013ec: 2200 movs r2, #0
|
|
80013ee: f44f 4100 mov.w r1, #32768 @ 0x8000
|
|
80013f2: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
80013f6: f001 fb9b bl 8002b30 <HAL_GPIO_WritePin>
|
|
HAL_Delay(1);
|
|
80013fa: 2001 movs r0, #1
|
|
80013fc: f001 f83a bl 8002474 <HAL_Delay>
|
|
}
|
|
8001400: bf00 nop
|
|
8001402: bd80 pop {r7, pc}
|
|
|
|
08001404 <lcd_reset>:
|
|
|
|
void lcd_reset(void)
|
|
{
|
|
8001404: b580 push {r7, lr}
|
|
8001406: af00 add r7, sp, #0
|
|
// Resets display from any state to 4-bit mode, first nibble.
|
|
|
|
// Set everything low first
|
|
HAL_GPIO_WritePin(RS_PORT, LCD_RS, 0);
|
|
8001408: 2200 movs r2, #0
|
|
800140a: 2104 movs r1, #4
|
|
800140c: 4820 ldr r0, [pc, #128] @ (8001490 <lcd_reset+0x8c>)
|
|
800140e: f001 fb8f bl 8002b30 <HAL_GPIO_WritePin>
|
|
|
|
HAL_GPIO_WritePin(LCD_PORT7, LCD_7, 0);
|
|
8001412: 2200 movs r2, #0
|
|
8001414: 2110 movs r1, #16
|
|
8001416: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
800141a: f001 fb89 bl 8002b30 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(LCD_PORT4, LCD_4, 0);
|
|
800141e: 2200 movs r2, #0
|
|
8001420: 2108 movs r1, #8
|
|
8001422: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
8001426: f001 fb83 bl 8002b30 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(LCD_PORT56, LCD_5, 0);
|
|
800142a: 2200 movs r2, #0
|
|
800142c: 2110 movs r1, #16
|
|
800142e: 4818 ldr r0, [pc, #96] @ (8001490 <lcd_reset+0x8c>)
|
|
8001430: f001 fb7e bl 8002b30 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(LCD_PORT56, LCD_6, 0);
|
|
8001434: 2200 movs r2, #0
|
|
8001436: 2102 movs r1, #2
|
|
8001438: 4815 ldr r0, [pc, #84] @ (8001490 <lcd_reset+0x8c>)
|
|
800143a: f001 fb79 bl 8002b30 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(CLOCK_PORT, LCD_CLOCK, 0);
|
|
800143e: 2200 movs r2, #0
|
|
8001440: f44f 4100 mov.w r1, #32768 @ 0x8000
|
|
8001444: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
8001448: f001 fb72 bl 8002b30 <HAL_GPIO_WritePin>
|
|
// from any setting
|
|
|
|
// Write 0b0011 three times
|
|
// (Everyday Practical Electronics says 3 times, Wikipedia says 2 times,
|
|
// 3 seems to work better).
|
|
HAL_GPIO_WritePin(LCD_PORT4, LCD_4, 1);
|
|
800144c: 2201 movs r2, #1
|
|
800144e: 2108 movs r1, #8
|
|
8001450: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
8001454: f001 fb6c bl 8002b30 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(LCD_PORT56, LCD_5, 1);
|
|
8001458: 2201 movs r2, #1
|
|
800145a: 2110 movs r1, #16
|
|
800145c: 480c ldr r0, [pc, #48] @ (8001490 <lcd_reset+0x8c>)
|
|
800145e: f001 fb67 bl 8002b30 <HAL_GPIO_WritePin>
|
|
lcd_clock();
|
|
8001462: f7ff ffb7 bl 80013d4 <lcd_clock>
|
|
lcd_clock();
|
|
8001466: f7ff ffb5 bl 80013d4 <lcd_clock>
|
|
lcd_clock();
|
|
800146a: f7ff ffb3 bl 80013d4 <lcd_clock>
|
|
// LCD now guaranteed to be in 8-bit state
|
|
// Now write 0b0010 (set to 4-bit mode, ready for first nibble)
|
|
HAL_GPIO_WritePin(LCD_PORT4, LCD_4, 0);
|
|
800146e: 2200 movs r2, #0
|
|
8001470: 2108 movs r1, #8
|
|
8001472: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
8001476: f001 fb5b bl 8002b30 <HAL_GPIO_WritePin>
|
|
lcd_clock();
|
|
800147a: f7ff ffab bl 80013d4 <lcd_clock>
|
|
|
|
HAL_GPIO_WritePin(Led_LCD_GPIO_Port, Led_LCD_Pin, 1);
|
|
800147e: 2201 movs r2, #1
|
|
8001480: 2104 movs r1, #4
|
|
8001482: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
8001486: f001 fb53 bl 8002b30 <HAL_GPIO_WritePin>
|
|
}
|
|
800148a: bf00 nop
|
|
800148c: bd80 pop {r7, pc}
|
|
800148e: bf00 nop
|
|
8001490: 48000400 .word 0x48000400
|
|
|
|
08001494 <lcd_write>:
|
|
* for proper masks to be calculated.
|
|
* Aside from this, setting the RS bit seems to go wrong.
|
|
*/
|
|
|
|
void lcd_write(uint8_t byte, uint8_t rs)
|
|
{
|
|
8001494: b580 push {r7, lr}
|
|
8001496: b082 sub sp, #8
|
|
8001498: af00 add r7, sp, #0
|
|
800149a: 4603 mov r3, r0
|
|
800149c: 460a mov r2, r1
|
|
800149e: 71fb strb r3, [r7, #7]
|
|
80014a0: 4613 mov r3, r2
|
|
80014a2: 71bb strb r3, [r7, #6]
|
|
// Writes a byte to the display (rs must be either 0 or 1)
|
|
//rs=0 comando;; rs=1 dato
|
|
// Write second nibble and set RS
|
|
|
|
if((byte >> 4 ) & 1)
|
|
80014a4: 79fb ldrb r3, [r7, #7]
|
|
80014a6: 091b lsrs r3, r3, #4
|
|
80014a8: b2db uxtb r3, r3
|
|
80014aa: f003 0301 and.w r3, r3, #1
|
|
80014ae: 2b00 cmp r3, #0
|
|
80014b0: d006 beq.n 80014c0 <lcd_write+0x2c>
|
|
HAL_GPIO_WritePin(LCD_PORT4, LCD_4, 1);
|
|
80014b2: 2201 movs r2, #1
|
|
80014b4: 2108 movs r1, #8
|
|
80014b6: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
80014ba: f001 fb39 bl 8002b30 <HAL_GPIO_WritePin>
|
|
80014be: e005 b.n 80014cc <lcd_write+0x38>
|
|
else
|
|
HAL_GPIO_WritePin(LCD_PORT4, LCD_4, 0);
|
|
80014c0: 2200 movs r2, #0
|
|
80014c2: 2108 movs r1, #8
|
|
80014c4: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
80014c8: f001 fb32 bl 8002b30 <HAL_GPIO_WritePin>
|
|
|
|
if((byte >> 5 ) & 1)
|
|
80014cc: 79fb ldrb r3, [r7, #7]
|
|
80014ce: 095b lsrs r3, r3, #5
|
|
80014d0: b2db uxtb r3, r3
|
|
80014d2: f003 0301 and.w r3, r3, #1
|
|
80014d6: 2b00 cmp r3, #0
|
|
80014d8: d005 beq.n 80014e6 <lcd_write+0x52>
|
|
HAL_GPIO_WritePin(LCD_PORT56, LCD_5, 1);
|
|
80014da: 2201 movs r2, #1
|
|
80014dc: 2110 movs r1, #16
|
|
80014de: 4847 ldr r0, [pc, #284] @ (80015fc <lcd_write+0x168>)
|
|
80014e0: f001 fb26 bl 8002b30 <HAL_GPIO_WritePin>
|
|
80014e4: e004 b.n 80014f0 <lcd_write+0x5c>
|
|
else
|
|
HAL_GPIO_WritePin(LCD_PORT56, LCD_5, 0);
|
|
80014e6: 2200 movs r2, #0
|
|
80014e8: 2110 movs r1, #16
|
|
80014ea: 4844 ldr r0, [pc, #272] @ (80015fc <lcd_write+0x168>)
|
|
80014ec: f001 fb20 bl 8002b30 <HAL_GPIO_WritePin>
|
|
|
|
if((byte >> 6 ) & 1)
|
|
80014f0: 79fb ldrb r3, [r7, #7]
|
|
80014f2: 099b lsrs r3, r3, #6
|
|
80014f4: b2db uxtb r3, r3
|
|
80014f6: f003 0301 and.w r3, r3, #1
|
|
80014fa: 2b00 cmp r3, #0
|
|
80014fc: d005 beq.n 800150a <lcd_write+0x76>
|
|
HAL_GPIO_WritePin(LCD_PORT56, LCD_6, 1);
|
|
80014fe: 2201 movs r2, #1
|
|
8001500: 2102 movs r1, #2
|
|
8001502: 483e ldr r0, [pc, #248] @ (80015fc <lcd_write+0x168>)
|
|
8001504: f001 fb14 bl 8002b30 <HAL_GPIO_WritePin>
|
|
8001508: e004 b.n 8001514 <lcd_write+0x80>
|
|
else
|
|
HAL_GPIO_WritePin(LCD_PORT56, LCD_6, 0);
|
|
800150a: 2200 movs r2, #0
|
|
800150c: 2102 movs r1, #2
|
|
800150e: 483b ldr r0, [pc, #236] @ (80015fc <lcd_write+0x168>)
|
|
8001510: f001 fb0e bl 8002b30 <HAL_GPIO_WritePin>
|
|
|
|
if((byte >> 7 ) & 1)
|
|
8001514: 79fb ldrb r3, [r7, #7]
|
|
8001516: 09db lsrs r3, r3, #7
|
|
8001518: b2db uxtb r3, r3
|
|
800151a: f003 0301 and.w r3, r3, #1
|
|
800151e: 2b00 cmp r3, #0
|
|
8001520: d006 beq.n 8001530 <lcd_write+0x9c>
|
|
HAL_GPIO_WritePin(LCD_PORT7, LCD_7, 1);
|
|
8001522: 2201 movs r2, #1
|
|
8001524: 2110 movs r1, #16
|
|
8001526: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
800152a: f001 fb01 bl 8002b30 <HAL_GPIO_WritePin>
|
|
800152e: e005 b.n 800153c <lcd_write+0xa8>
|
|
else
|
|
HAL_GPIO_WritePin(LCD_PORT7, LCD_7, 0);
|
|
8001530: 2200 movs r2, #0
|
|
8001532: 2110 movs r1, #16
|
|
8001534: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
8001538: f001 fafa bl 8002b30 <HAL_GPIO_WritePin>
|
|
|
|
if(rs)
|
|
800153c: 79bb ldrb r3, [r7, #6]
|
|
800153e: 2b00 cmp r3, #0
|
|
8001540: d005 beq.n 800154e <lcd_write+0xba>
|
|
HAL_GPIO_WritePin(RS_PORT, LCD_RS, 1);
|
|
8001542: 2201 movs r2, #1
|
|
8001544: 2104 movs r1, #4
|
|
8001546: 482d ldr r0, [pc, #180] @ (80015fc <lcd_write+0x168>)
|
|
8001548: f001 faf2 bl 8002b30 <HAL_GPIO_WritePin>
|
|
800154c: e004 b.n 8001558 <lcd_write+0xc4>
|
|
else
|
|
HAL_GPIO_WritePin(RS_PORT, LCD_RS, 0);
|
|
800154e: 2200 movs r2, #0
|
|
8001550: 2104 movs r1, #4
|
|
8001552: 482a ldr r0, [pc, #168] @ (80015fc <lcd_write+0x168>)
|
|
8001554: f001 faec bl 8002b30 <HAL_GPIO_WritePin>
|
|
|
|
lcd_clock();
|
|
8001558: f7ff ff3c bl 80013d4 <lcd_clock>
|
|
|
|
// Write first nibble
|
|
|
|
if(byte & 1)
|
|
800155c: 79fb ldrb r3, [r7, #7]
|
|
800155e: f003 0301 and.w r3, r3, #1
|
|
8001562: 2b00 cmp r3, #0
|
|
8001564: d006 beq.n 8001574 <lcd_write+0xe0>
|
|
HAL_GPIO_WritePin(LCD_PORT4, LCD_4, 1);
|
|
8001566: 2201 movs r2, #1
|
|
8001568: 2108 movs r1, #8
|
|
800156a: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
800156e: f001 fadf bl 8002b30 <HAL_GPIO_WritePin>
|
|
8001572: e005 b.n 8001580 <lcd_write+0xec>
|
|
else
|
|
HAL_GPIO_WritePin(LCD_PORT4, LCD_4, 0);
|
|
8001574: 2200 movs r2, #0
|
|
8001576: 2108 movs r1, #8
|
|
8001578: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
800157c: f001 fad8 bl 8002b30 <HAL_GPIO_WritePin>
|
|
|
|
if((byte >> 1 ) & 1)
|
|
8001580: 79fb ldrb r3, [r7, #7]
|
|
8001582: 085b lsrs r3, r3, #1
|
|
8001584: b2db uxtb r3, r3
|
|
8001586: f003 0301 and.w r3, r3, #1
|
|
800158a: 2b00 cmp r3, #0
|
|
800158c: d005 beq.n 800159a <lcd_write+0x106>
|
|
HAL_GPIO_WritePin(LCD_PORT56, LCD_5, 1);
|
|
800158e: 2201 movs r2, #1
|
|
8001590: 2110 movs r1, #16
|
|
8001592: 481a ldr r0, [pc, #104] @ (80015fc <lcd_write+0x168>)
|
|
8001594: f001 facc bl 8002b30 <HAL_GPIO_WritePin>
|
|
8001598: e004 b.n 80015a4 <lcd_write+0x110>
|
|
else
|
|
HAL_GPIO_WritePin(LCD_PORT56, LCD_5, 0);
|
|
800159a: 2200 movs r2, #0
|
|
800159c: 2110 movs r1, #16
|
|
800159e: 4817 ldr r0, [pc, #92] @ (80015fc <lcd_write+0x168>)
|
|
80015a0: f001 fac6 bl 8002b30 <HAL_GPIO_WritePin>
|
|
|
|
if((byte >> 2 ) & 1)
|
|
80015a4: 79fb ldrb r3, [r7, #7]
|
|
80015a6: 089b lsrs r3, r3, #2
|
|
80015a8: b2db uxtb r3, r3
|
|
80015aa: f003 0301 and.w r3, r3, #1
|
|
80015ae: 2b00 cmp r3, #0
|
|
80015b0: d005 beq.n 80015be <lcd_write+0x12a>
|
|
HAL_GPIO_WritePin(LCD_PORT56, LCD_6, 1);
|
|
80015b2: 2201 movs r2, #1
|
|
80015b4: 2102 movs r1, #2
|
|
80015b6: 4811 ldr r0, [pc, #68] @ (80015fc <lcd_write+0x168>)
|
|
80015b8: f001 faba bl 8002b30 <HAL_GPIO_WritePin>
|
|
80015bc: e004 b.n 80015c8 <lcd_write+0x134>
|
|
else
|
|
HAL_GPIO_WritePin(LCD_PORT56, LCD_6, 0);
|
|
80015be: 2200 movs r2, #0
|
|
80015c0: 2102 movs r1, #2
|
|
80015c2: 480e ldr r0, [pc, #56] @ (80015fc <lcd_write+0x168>)
|
|
80015c4: f001 fab4 bl 8002b30 <HAL_GPIO_WritePin>
|
|
|
|
if((byte >> 3 ) & 1)
|
|
80015c8: 79fb ldrb r3, [r7, #7]
|
|
80015ca: 08db lsrs r3, r3, #3
|
|
80015cc: b2db uxtb r3, r3
|
|
80015ce: f003 0301 and.w r3, r3, #1
|
|
80015d2: 2b00 cmp r3, #0
|
|
80015d4: d006 beq.n 80015e4 <lcd_write+0x150>
|
|
HAL_GPIO_WritePin(LCD_PORT7, LCD_7, 1);
|
|
80015d6: 2201 movs r2, #1
|
|
80015d8: 2110 movs r1, #16
|
|
80015da: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
80015de: f001 faa7 bl 8002b30 <HAL_GPIO_WritePin>
|
|
80015e2: e005 b.n 80015f0 <lcd_write+0x15c>
|
|
else
|
|
HAL_GPIO_WritePin(LCD_PORT7, LCD_7, 0);
|
|
80015e4: 2200 movs r2, #0
|
|
80015e6: 2110 movs r1, #16
|
|
80015e8: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
80015ec: f001 faa0 bl 8002b30 <HAL_GPIO_WritePin>
|
|
|
|
lcd_clock();
|
|
80015f0: f7ff fef0 bl 80013d4 <lcd_clock>
|
|
}
|
|
80015f4: bf00 nop
|
|
80015f6: 3708 adds r7, #8
|
|
80015f8: 46bd mov sp, r7
|
|
80015fa: bd80 pop {r7, pc}
|
|
80015fc: 48000400 .word 0x48000400
|
|
|
|
08001600 <lcd_clear>:
|
|
|
|
void lcd_clear(void)
|
|
{
|
|
8001600: b580 push {r7, lr}
|
|
8001602: af00 add r7, sp, #0
|
|
// Clears display, resets cursor
|
|
lcd_write(0b00000001, 0);
|
|
8001604: 2100 movs r1, #0
|
|
8001606: 2001 movs r0, #1
|
|
8001608: f7ff ff44 bl 8001494 <lcd_write>
|
|
_lcd_char = 0;
|
|
800160c: 4b03 ldr r3, [pc, #12] @ (800161c <lcd_clear+0x1c>)
|
|
800160e: 2200 movs r2, #0
|
|
8001610: 701a strb r2, [r3, #0]
|
|
_lcd_line = 0;
|
|
8001612: 4b03 ldr r3, [pc, #12] @ (8001620 <lcd_clear+0x20>)
|
|
8001614: 2200 movs r2, #0
|
|
8001616: 701a strb r2, [r3, #0]
|
|
}
|
|
8001618: bf00 nop
|
|
800161a: bd80 pop {r7, pc}
|
|
800161c: 20000234 .word 0x20000234
|
|
8001620: 20000235 .word 0x20000235
|
|
|
|
08001624 <lcd_display_settings>:
|
|
|
|
void lcd_display_settings(uint8_t on, uint8_t underline, uint8_t blink)
|
|
{
|
|
8001624: b580 push {r7, lr}
|
|
8001626: b082 sub sp, #8
|
|
8001628: af00 add r7, sp, #0
|
|
800162a: 4603 mov r3, r0
|
|
800162c: 71fb strb r3, [r7, #7]
|
|
800162e: 460b mov r3, r1
|
|
8001630: 71bb strb r3, [r7, #6]
|
|
8001632: 4613 mov r3, r2
|
|
8001634: 717b strb r3, [r7, #5]
|
|
// "Display On/Off & Cursor" command. All parameters must be either 0 or 1
|
|
|
|
lcd_write(0b00001000 | (on << 2) | (underline << 1) | blink, 0);
|
|
8001636: f997 3007 ldrsb.w r3, [r7, #7]
|
|
800163a: 009b lsls r3, r3, #2
|
|
800163c: b25b sxtb r3, r3
|
|
800163e: f043 0308 orr.w r3, r3, #8
|
|
8001642: b25a sxtb r2, r3
|
|
8001644: f997 3006 ldrsb.w r3, [r7, #6]
|
|
8001648: 005b lsls r3, r3, #1
|
|
800164a: b25b sxtb r3, r3
|
|
800164c: 4313 orrs r3, r2
|
|
800164e: b25a sxtb r2, r3
|
|
8001650: f997 3005 ldrsb.w r3, [r7, #5]
|
|
8001654: 4313 orrs r3, r2
|
|
8001656: b25b sxtb r3, r3
|
|
8001658: b2db uxtb r3, r3
|
|
800165a: 2100 movs r1, #0
|
|
800165c: 4618 mov r0, r3
|
|
800165e: f7ff ff19 bl 8001494 <lcd_write>
|
|
}
|
|
8001662: bf00 nop
|
|
8001664: 3708 adds r7, #8
|
|
8001666: 46bd mov sp, r7
|
|
8001668: bd80 pop {r7, pc}
|
|
|
|
0800166a <lcd_display_address>:
|
|
|
|
void lcd_display_address(uint8_t address)
|
|
{
|
|
800166a: b580 push {r7, lr}
|
|
800166c: b082 sub sp, #8
|
|
800166e: af00 add r7, sp, #0
|
|
8001670: 4603 mov r3, r0
|
|
8001672: 71fb strb r3, [r7, #7]
|
|
lcd_write(0b10000000 | address, 0);
|
|
8001674: 79fb ldrb r3, [r7, #7]
|
|
8001676: f063 037f orn r3, r3, #127 @ 0x7f
|
|
800167a: b2db uxtb r3, r3
|
|
800167c: 2100 movs r1, #0
|
|
800167e: 4618 mov r0, r3
|
|
8001680: f7ff ff08 bl 8001494 <lcd_write>
|
|
}
|
|
8001684: bf00 nop
|
|
8001686: 3708 adds r7, #8
|
|
8001688: 46bd mov sp, r7
|
|
800168a: bd80 pop {r7, pc}
|
|
|
|
0800168c <lcd_print>:
|
|
{
|
|
lcd_write(0b01000000 | address, 0);
|
|
}
|
|
|
|
void lcd_print(char string[])
|
|
{
|
|
800168c: b580 push {r7, lr}
|
|
800168e: b084 sub sp, #16
|
|
8001690: af00 add r7, sp, #0
|
|
8001692: 6078 str r0, [r7, #4]
|
|
uint8_t i;
|
|
for(i = 0; string[i] != 0; i++) {
|
|
8001694: 2300 movs r3, #0
|
|
8001696: 73fb strb r3, [r7, #15]
|
|
8001698: e055 b.n 8001746 <lcd_print+0xba>
|
|
// If we know the display properties and a newline character is
|
|
// present, print the rest of the string on the new line.
|
|
if(lcd_lines && string[i] == '\n') {
|
|
800169a: 4b30 ldr r3, [pc, #192] @ (800175c <lcd_print+0xd0>)
|
|
800169c: 781b ldrb r3, [r3, #0]
|
|
800169e: 2b00 cmp r3, #0
|
|
80016a0: d01c beq.n 80016dc <lcd_print+0x50>
|
|
80016a2: 7bfb ldrb r3, [r7, #15]
|
|
80016a4: 687a ldr r2, [r7, #4]
|
|
80016a6: 4413 add r3, r2
|
|
80016a8: 781b ldrb r3, [r3, #0]
|
|
80016aa: 2b0a cmp r3, #10
|
|
80016ac: d116 bne.n 80016dc <lcd_print+0x50>
|
|
if(_lcd_line < lcd_lines) {
|
|
80016ae: 4b2c ldr r3, [pc, #176] @ (8001760 <lcd_print+0xd4>)
|
|
80016b0: 781a ldrb r2, [r3, #0]
|
|
80016b2: 4b2a ldr r3, [pc, #168] @ (800175c <lcd_print+0xd0>)
|
|
80016b4: 781b ldrb r3, [r3, #0]
|
|
80016b6: 429a cmp r2, r3
|
|
80016b8: d242 bcs.n 8001740 <lcd_print+0xb4>
|
|
lcd_display_address(lcd_line_addresses[_lcd_line++]);
|
|
80016ba: 4b2a ldr r3, [pc, #168] @ (8001764 <lcd_print+0xd8>)
|
|
80016bc: 681a ldr r2, [r3, #0]
|
|
80016be: 4b28 ldr r3, [pc, #160] @ (8001760 <lcd_print+0xd4>)
|
|
80016c0: 781b ldrb r3, [r3, #0]
|
|
80016c2: 1c59 adds r1, r3, #1
|
|
80016c4: b2c8 uxtb r0, r1
|
|
80016c6: 4926 ldr r1, [pc, #152] @ (8001760 <lcd_print+0xd4>)
|
|
80016c8: 7008 strb r0, [r1, #0]
|
|
80016ca: 4413 add r3, r2
|
|
80016cc: 781b ldrb r3, [r3, #0]
|
|
80016ce: 4618 mov r0, r3
|
|
80016d0: f7ff ffcb bl 800166a <lcd_display_address>
|
|
_lcd_char = 0;
|
|
80016d4: 4b24 ldr r3, [pc, #144] @ (8001768 <lcd_print+0xdc>)
|
|
80016d6: 2200 movs r2, #0
|
|
80016d8: 701a strb r2, [r3, #0]
|
|
if(_lcd_line < lcd_lines) {
|
|
80016da: e031 b.n 8001740 <lcd_print+0xb4>
|
|
}
|
|
}
|
|
else {
|
|
// If we know the display properties and have reached the end of
|
|
// line, print the rest on the next line
|
|
if(lcd_chars)
|
|
80016dc: 4b23 ldr r3, [pc, #140] @ (800176c <lcd_print+0xe0>)
|
|
80016de: 781b ldrb r3, [r3, #0]
|
|
80016e0: 2b00 cmp r3, #0
|
|
80016e2: d01b beq.n 800171c <lcd_print+0x90>
|
|
if((_lcd_char == lcd_chars) && (_lcd_line < lcd_lines)) {
|
|
80016e4: 4b20 ldr r3, [pc, #128] @ (8001768 <lcd_print+0xdc>)
|
|
80016e6: 781a ldrb r2, [r3, #0]
|
|
80016e8: 4b20 ldr r3, [pc, #128] @ (800176c <lcd_print+0xe0>)
|
|
80016ea: 781b ldrb r3, [r3, #0]
|
|
80016ec: 429a cmp r2, r3
|
|
80016ee: d115 bne.n 800171c <lcd_print+0x90>
|
|
80016f0: 4b1b ldr r3, [pc, #108] @ (8001760 <lcd_print+0xd4>)
|
|
80016f2: 781a ldrb r2, [r3, #0]
|
|
80016f4: 4b19 ldr r3, [pc, #100] @ (800175c <lcd_print+0xd0>)
|
|
80016f6: 781b ldrb r3, [r3, #0]
|
|
80016f8: 429a cmp r2, r3
|
|
80016fa: d20f bcs.n 800171c <lcd_print+0x90>
|
|
lcd_display_address(lcd_line_addresses[_lcd_line++]);
|
|
80016fc: 4b19 ldr r3, [pc, #100] @ (8001764 <lcd_print+0xd8>)
|
|
80016fe: 681a ldr r2, [r3, #0]
|
|
8001700: 4b17 ldr r3, [pc, #92] @ (8001760 <lcd_print+0xd4>)
|
|
8001702: 781b ldrb r3, [r3, #0]
|
|
8001704: 1c59 adds r1, r3, #1
|
|
8001706: b2c8 uxtb r0, r1
|
|
8001708: 4915 ldr r1, [pc, #84] @ (8001760 <lcd_print+0xd4>)
|
|
800170a: 7008 strb r0, [r1, #0]
|
|
800170c: 4413 add r3, r2
|
|
800170e: 781b ldrb r3, [r3, #0]
|
|
8001710: 4618 mov r0, r3
|
|
8001712: f7ff ffaa bl 800166a <lcd_display_address>
|
|
_lcd_char = 0;
|
|
8001716: 4b14 ldr r3, [pc, #80] @ (8001768 <lcd_print+0xdc>)
|
|
8001718: 2200 movs r2, #0
|
|
800171a: 701a strb r2, [r3, #0]
|
|
}
|
|
lcd_write(string[i], 1);
|
|
800171c: 7bfb ldrb r3, [r7, #15]
|
|
800171e: 687a ldr r2, [r7, #4]
|
|
8001720: 4413 add r3, r2
|
|
8001722: 781b ldrb r3, [r3, #0]
|
|
8001724: 2101 movs r1, #1
|
|
8001726: 4618 mov r0, r3
|
|
8001728: f7ff feb4 bl 8001494 <lcd_write>
|
|
if(lcd_chars) _lcd_char++;
|
|
800172c: 4b0f ldr r3, [pc, #60] @ (800176c <lcd_print+0xe0>)
|
|
800172e: 781b ldrb r3, [r3, #0]
|
|
8001730: 2b00 cmp r3, #0
|
|
8001732: d005 beq.n 8001740 <lcd_print+0xb4>
|
|
8001734: 4b0c ldr r3, [pc, #48] @ (8001768 <lcd_print+0xdc>)
|
|
8001736: 781b ldrb r3, [r3, #0]
|
|
8001738: 3301 adds r3, #1
|
|
800173a: b2da uxtb r2, r3
|
|
800173c: 4b0a ldr r3, [pc, #40] @ (8001768 <lcd_print+0xdc>)
|
|
800173e: 701a strb r2, [r3, #0]
|
|
for(i = 0; string[i] != 0; i++) {
|
|
8001740: 7bfb ldrb r3, [r7, #15]
|
|
8001742: 3301 adds r3, #1
|
|
8001744: 73fb strb r3, [r7, #15]
|
|
8001746: 7bfb ldrb r3, [r7, #15]
|
|
8001748: 687a ldr r2, [r7, #4]
|
|
800174a: 4413 add r3, r2
|
|
800174c: 781b ldrb r3, [r3, #0]
|
|
800174e: 2b00 cmp r3, #0
|
|
8001750: d1a3 bne.n 800169a <lcd_print+0xe>
|
|
}
|
|
}
|
|
}
|
|
8001752: bf00 nop
|
|
8001754: bf00 nop
|
|
8001756: 3710 adds r7, #16
|
|
8001758: 46bd mov sp, r7
|
|
800175a: bd80 pop {r7, pc}
|
|
800175c: 2000022d .word 0x2000022d
|
|
8001760: 20000235 .word 0x20000235
|
|
8001764: 20000230 .word 0x20000230
|
|
8001768: 20000234 .word 0x20000234
|
|
800176c: 2000022c .word 0x2000022c
|
|
|
|
08001770 <moveToXY>:
|
|
unsigned char ones = (integer - thousands*1000 - hundreds*100 - tens*10);
|
|
lcd_write( ones + 0x30,1);
|
|
}
|
|
|
|
void moveToXY(unsigned char row, unsigned char column)
|
|
{
|
|
8001770: b580 push {r7, lr}
|
|
8001772: b084 sub sp, #16
|
|
8001774: af00 add r7, sp, #0
|
|
8001776: 4603 mov r3, r0
|
|
8001778: 460a mov r2, r1
|
|
800177a: 71fb strb r3, [r7, #7]
|
|
800177c: 4613 mov r3, r2
|
|
800177e: 71bb strb r3, [r7, #6]
|
|
// Determine the new position
|
|
int position = (row * 16) + column;
|
|
8001780: 79fb ldrb r3, [r7, #7]
|
|
8001782: 011a lsls r2, r3, #4
|
|
8001784: 79bb ldrb r3, [r7, #6]
|
|
8001786: 4413 add r3, r2
|
|
8001788: 60fb str r3, [r7, #12]
|
|
|
|
// Send the correct commands to the command register of the LCD
|
|
if(position < 16)
|
|
800178a: 68fb ldr r3, [r7, #12]
|
|
800178c: 2b0f cmp r3, #15
|
|
800178e: dc0a bgt.n 80017a6 <moveToXY+0x36>
|
|
lcd_write( 0x80 | position,0);
|
|
8001790: 68fb ldr r3, [r7, #12]
|
|
8001792: b25b sxtb r3, r3
|
|
8001794: f063 037f orn r3, r3, #127 @ 0x7f
|
|
8001798: b25b sxtb r3, r3
|
|
800179a: b2db uxtb r3, r3
|
|
800179c: 2100 movs r1, #0
|
|
800179e: 4618 mov r0, r3
|
|
80017a0: f7ff fe78 bl 8001494 <lcd_write>
|
|
lcd_write( 0x80 | (position % 16 + 0x40),0);
|
|
else if(position >= 41 && position < 60)
|
|
lcd_write( 0x80 | (position % 40 + 0x14),0);
|
|
else if(position >= 20 && position < 40)
|
|
lcd_write( 0x80 | (position % 60 + 0x54),0);
|
|
}
|
|
80017a4: e059 b.n 800185a <moveToXY+0xea>
|
|
else if(position >= 16 && position < 32)
|
|
80017a6: 68fb ldr r3, [r7, #12]
|
|
80017a8: 2b0f cmp r3, #15
|
|
80017aa: dd17 ble.n 80017dc <moveToXY+0x6c>
|
|
80017ac: 68fb ldr r3, [r7, #12]
|
|
80017ae: 2b1f cmp r3, #31
|
|
80017b0: dc14 bgt.n 80017dc <moveToXY+0x6c>
|
|
lcd_write( 0x80 | (position % 16 + 0x40),0);
|
|
80017b2: 68fb ldr r3, [r7, #12]
|
|
80017b4: 425a negs r2, r3
|
|
80017b6: f003 030f and.w r3, r3, #15
|
|
80017ba: f002 020f and.w r2, r2, #15
|
|
80017be: bf58 it pl
|
|
80017c0: 4253 negpl r3, r2
|
|
80017c2: b2db uxtb r3, r3
|
|
80017c4: 3340 adds r3, #64 @ 0x40
|
|
80017c6: b2db uxtb r3, r3
|
|
80017c8: b25b sxtb r3, r3
|
|
80017ca: f063 037f orn r3, r3, #127 @ 0x7f
|
|
80017ce: b25b sxtb r3, r3
|
|
80017d0: b2db uxtb r3, r3
|
|
80017d2: 2100 movs r1, #0
|
|
80017d4: 4618 mov r0, r3
|
|
80017d6: f7ff fe5d bl 8001494 <lcd_write>
|
|
80017da: e03e b.n 800185a <moveToXY+0xea>
|
|
else if(position >= 41 && position < 60)
|
|
80017dc: 68fb ldr r3, [r7, #12]
|
|
80017de: 2b28 cmp r3, #40 @ 0x28
|
|
80017e0: dd1b ble.n 800181a <moveToXY+0xaa>
|
|
80017e2: 68fb ldr r3, [r7, #12]
|
|
80017e4: 2b3b cmp r3, #59 @ 0x3b
|
|
80017e6: dc18 bgt.n 800181a <moveToXY+0xaa>
|
|
lcd_write( 0x80 | (position % 40 + 0x14),0);
|
|
80017e8: 68fa ldr r2, [r7, #12]
|
|
80017ea: 4b1e ldr r3, [pc, #120] @ (8001864 <moveToXY+0xf4>)
|
|
80017ec: fb83 1302 smull r1, r3, r3, r2
|
|
80017f0: 1119 asrs r1, r3, #4
|
|
80017f2: 17d3 asrs r3, r2, #31
|
|
80017f4: 1ac9 subs r1, r1, r3
|
|
80017f6: 460b mov r3, r1
|
|
80017f8: 009b lsls r3, r3, #2
|
|
80017fa: 440b add r3, r1
|
|
80017fc: 00db lsls r3, r3, #3
|
|
80017fe: 1ad1 subs r1, r2, r3
|
|
8001800: b2cb uxtb r3, r1
|
|
8001802: 3314 adds r3, #20
|
|
8001804: b2db uxtb r3, r3
|
|
8001806: b25b sxtb r3, r3
|
|
8001808: f063 037f orn r3, r3, #127 @ 0x7f
|
|
800180c: b25b sxtb r3, r3
|
|
800180e: b2db uxtb r3, r3
|
|
8001810: 2100 movs r1, #0
|
|
8001812: 4618 mov r0, r3
|
|
8001814: f7ff fe3e bl 8001494 <lcd_write>
|
|
8001818: e01f b.n 800185a <moveToXY+0xea>
|
|
else if(position >= 20 && position < 40)
|
|
800181a: 68fb ldr r3, [r7, #12]
|
|
800181c: 2b13 cmp r3, #19
|
|
800181e: dd1c ble.n 800185a <moveToXY+0xea>
|
|
8001820: 68fb ldr r3, [r7, #12]
|
|
8001822: 2b27 cmp r3, #39 @ 0x27
|
|
8001824: dc19 bgt.n 800185a <moveToXY+0xea>
|
|
lcd_write( 0x80 | (position % 60 + 0x54),0);
|
|
8001826: 68fa ldr r2, [r7, #12]
|
|
8001828: 4b0f ldr r3, [pc, #60] @ (8001868 <moveToXY+0xf8>)
|
|
800182a: fb83 1302 smull r1, r3, r3, r2
|
|
800182e: 4413 add r3, r2
|
|
8001830: 1159 asrs r1, r3, #5
|
|
8001832: 17d3 asrs r3, r2, #31
|
|
8001834: 1ac9 subs r1, r1, r3
|
|
8001836: 460b mov r3, r1
|
|
8001838: 011b lsls r3, r3, #4
|
|
800183a: 1a5b subs r3, r3, r1
|
|
800183c: 009b lsls r3, r3, #2
|
|
800183e: 1ad1 subs r1, r2, r3
|
|
8001840: b2cb uxtb r3, r1
|
|
8001842: 3354 adds r3, #84 @ 0x54
|
|
8001844: b2db uxtb r3, r3
|
|
8001846: b25b sxtb r3, r3
|
|
8001848: f063 037f orn r3, r3, #127 @ 0x7f
|
|
800184c: b25b sxtb r3, r3
|
|
800184e: b2db uxtb r3, r3
|
|
8001850: 2100 movs r1, #0
|
|
8001852: 4618 mov r0, r3
|
|
8001854: f7ff fe1e bl 8001494 <lcd_write>
|
|
}
|
|
8001858: e7ff b.n 800185a <moveToXY+0xea>
|
|
800185a: bf00 nop
|
|
800185c: 3710 adds r7, #16
|
|
800185e: 46bd mov sp, r7
|
|
8001860: bd80 pop {r7, pc}
|
|
8001862: bf00 nop
|
|
8001864: 66666667 .word 0x66666667
|
|
8001868: 88888889 .word 0x88888889
|
|
|
|
0800186c <__io_putchar>:
|
|
/* USER CODE END PFP */
|
|
|
|
/* Private user code ---------------------------------------------------------*/
|
|
/* USER CODE BEGIN 0 */
|
|
void __io_putchar(int ch)
|
|
{
|
|
800186c: b580 push {r7, lr}
|
|
800186e: b084 sub sp, #16
|
|
8001870: af00 add r7, sp, #0
|
|
8001872: 6078 str r0, [r7, #4]
|
|
uint8_t c[1];
|
|
c[0] = ch & 0x00ff;
|
|
8001874: 687b ldr r3, [r7, #4]
|
|
8001876: b2db uxtb r3, r3
|
|
8001878: 733b strb r3, [r7, #12]
|
|
HAL_UART_Transmit(&huart1, &*c, 1, 10);
|
|
800187a: f107 010c add.w r1, r7, #12
|
|
800187e: 230a movs r3, #10
|
|
8001880: 2201 movs r2, #1
|
|
8001882: 4803 ldr r0, [pc, #12] @ (8001890 <__io_putchar+0x24>)
|
|
8001884: f003 fafe bl 8004e84 <HAL_UART_Transmit>
|
|
return ch;
|
|
8001888: bf00 nop
|
|
}
|
|
800188a: 3710 adds r7, #16
|
|
800188c: 46bd mov sp, r7
|
|
800188e: bd80 pop {r7, pc}
|
|
8001890: 2000028c .word 0x2000028c
|
|
|
|
08001894 <HAL_UART_RxCpltCallback>:
|
|
|
|
void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
8001894: b580 push {r7, lr}
|
|
8001896: b082 sub sp, #8
|
|
8001898: af00 add r7, sp, #0
|
|
800189a: 6078 str r0, [r7, #4]
|
|
switch (rxByte) {
|
|
800189c: 4b20 ldr r3, [pc, #128] @ (8001920 <HAL_UART_RxCpltCallback+0x8c>)
|
|
800189e: 781b ldrb r3, [r3, #0]
|
|
80018a0: 2b75 cmp r3, #117 @ 0x75
|
|
80018a2: d025 beq.n 80018f0 <HAL_UART_RxCpltCallback+0x5c>
|
|
80018a4: 2b75 cmp r3, #117 @ 0x75
|
|
80018a6: dc2e bgt.n 8001906 <HAL_UART_RxCpltCallback+0x72>
|
|
80018a8: 2b63 cmp r3, #99 @ 0x63
|
|
80018aa: d009 beq.n 80018c0 <HAL_UART_RxCpltCallback+0x2c>
|
|
80018ac: 2b63 cmp r3, #99 @ 0x63
|
|
80018ae: db2a blt.n 8001906 <HAL_UART_RxCpltCallback+0x72>
|
|
80018b0: 3b6d subs r3, #109 @ 0x6d
|
|
80018b2: 2b01 cmp r3, #1
|
|
80018b4: d827 bhi.n 8001906 <HAL_UART_RxCpltCallback+0x72>
|
|
case 'm':
|
|
case 'n':
|
|
displayMode = rxByte;
|
|
80018b6: 4b1a ldr r3, [pc, #104] @ (8001920 <HAL_UART_RxCpltCallback+0x8c>)
|
|
80018b8: 781a ldrb r2, [r3, #0]
|
|
80018ba: 4b1a ldr r3, [pc, #104] @ (8001924 <HAL_UART_RxCpltCallback+0x90>)
|
|
80018bc: 701a strb r2, [r3, #0]
|
|
break;
|
|
80018be: e026 b.n 800190e <HAL_UART_RxCpltCallback+0x7a>
|
|
case 'c':
|
|
maxTemp = -100.0; minTemp = 100.0;
|
|
80018c0: 4b19 ldr r3, [pc, #100] @ (8001928 <HAL_UART_RxCpltCallback+0x94>)
|
|
80018c2: 4a1a ldr r2, [pc, #104] @ (800192c <HAL_UART_RxCpltCallback+0x98>)
|
|
80018c4: 601a str r2, [r3, #0]
|
|
80018c6: 4b1a ldr r3, [pc, #104] @ (8001930 <HAL_UART_RxCpltCallback+0x9c>)
|
|
80018c8: 4a1a ldr r2, [pc, #104] @ (8001934 <HAL_UART_RxCpltCallback+0xa0>)
|
|
80018ca: 601a str r2, [r3, #0]
|
|
maxHum = 0.0; minHum = 100.0;
|
|
80018cc: 4b1a ldr r3, [pc, #104] @ (8001938 <HAL_UART_RxCpltCallback+0xa4>)
|
|
80018ce: f04f 0200 mov.w r2, #0
|
|
80018d2: 601a str r2, [r3, #0]
|
|
80018d4: 4b19 ldr r3, [pc, #100] @ (800193c <HAL_UART_RxCpltCallback+0xa8>)
|
|
80018d6: 4a17 ldr r2, [pc, #92] @ (8001934 <HAL_UART_RxCpltCallback+0xa0>)
|
|
80018d8: 601a str r2, [r3, #0]
|
|
maxPress = 0.0; minPress = 2000.0;
|
|
80018da: 4b19 ldr r3, [pc, #100] @ (8001940 <HAL_UART_RxCpltCallback+0xac>)
|
|
80018dc: f04f 0200 mov.w r2, #0
|
|
80018e0: 601a str r2, [r3, #0]
|
|
80018e2: 4b18 ldr r3, [pc, #96] @ (8001944 <HAL_UART_RxCpltCallback+0xb0>)
|
|
80018e4: 4a18 ldr r2, [pc, #96] @ (8001948 <HAL_UART_RxCpltCallback+0xb4>)
|
|
80018e6: 601a str r2, [r3, #0]
|
|
displayMode = ' ';
|
|
80018e8: 4b0e ldr r3, [pc, #56] @ (8001924 <HAL_UART_RxCpltCallback+0x90>)
|
|
80018ea: 2220 movs r2, #32
|
|
80018ec: 701a strb r2, [r3, #0]
|
|
break;
|
|
80018ee: e00e b.n 800190e <HAL_UART_RxCpltCallback+0x7a>
|
|
case 'u':
|
|
useFahrenheit = !useFahrenheit;
|
|
80018f0: 4b16 ldr r3, [pc, #88] @ (800194c <HAL_UART_RxCpltCallback+0xb8>)
|
|
80018f2: 681b ldr r3, [r3, #0]
|
|
80018f4: 2b00 cmp r3, #0
|
|
80018f6: bf0c ite eq
|
|
80018f8: 2301 moveq r3, #1
|
|
80018fa: 2300 movne r3, #0
|
|
80018fc: b2db uxtb r3, r3
|
|
80018fe: 461a mov r2, r3
|
|
8001900: 4b12 ldr r3, [pc, #72] @ (800194c <HAL_UART_RxCpltCallback+0xb8>)
|
|
8001902: 601a str r2, [r3, #0]
|
|
break;
|
|
8001904: e003 b.n 800190e <HAL_UART_RxCpltCallback+0x7a>
|
|
default:
|
|
displayMode = ' ';
|
|
8001906: 4b07 ldr r3, [pc, #28] @ (8001924 <HAL_UART_RxCpltCallback+0x90>)
|
|
8001908: 2220 movs r2, #32
|
|
800190a: 701a strb r2, [r3, #0]
|
|
break;
|
|
800190c: bf00 nop
|
|
}
|
|
HAL_UART_Receive_IT(&huart1, &rxByte, 1);
|
|
800190e: 2201 movs r2, #1
|
|
8001910: 4903 ldr r1, [pc, #12] @ (8001920 <HAL_UART_RxCpltCallback+0x8c>)
|
|
8001912: 480f ldr r0, [pc, #60] @ (8001950 <HAL_UART_RxCpltCallback+0xbc>)
|
|
8001914: f003 fb40 bl 8004f98 <HAL_UART_Receive_IT>
|
|
}
|
|
8001918: bf00 nop
|
|
800191a: 3708 adds r7, #8
|
|
800191c: 46bd mov sp, r7
|
|
800191e: bd80 pop {r7, pc}
|
|
8001920: 20000314 .word 0x20000314
|
|
8001924: 20000000 .word 0x20000000
|
|
8001928: 20000004 .word 0x20000004
|
|
800192c: c2c80000 .word 0xc2c80000
|
|
8001930: 20000008 .word 0x20000008
|
|
8001934: 42c80000 .word 0x42c80000
|
|
8001938: 2000031c .word 0x2000031c
|
|
800193c: 2000000c .word 0x2000000c
|
|
8001940: 20000320 .word 0x20000320
|
|
8001944: 20000010 .word 0x20000010
|
|
8001948: 44fa0000 .word 0x44fa0000
|
|
800194c: 20000318 .word 0x20000318
|
|
8001950: 2000028c .word 0x2000028c
|
|
8001954: 00000000 .word 0x00000000
|
|
|
|
08001958 <main>:
|
|
/**
|
|
* @brief The application entry point.
|
|
* @retval int
|
|
*/
|
|
int main(void)
|
|
{
|
|
8001958: b5f0 push {r4, r5, r6, r7, lr}
|
|
800195a: b091 sub sp, #68 @ 0x44
|
|
800195c: af04 add r7, sp, #16
|
|
/* USER CODE END 1 */
|
|
|
|
/* MCU Configuration--------------------------------------------------------*/
|
|
|
|
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
|
|
HAL_Init();
|
|
800195e: f000 fd14 bl 800238a <HAL_Init>
|
|
/* USER CODE BEGIN Init */
|
|
|
|
/* USER CODE END Init */
|
|
|
|
/* Configure the system clock */
|
|
SystemClock_Config();
|
|
8001962: f000 f9d1 bl 8001d08 <SystemClock_Config>
|
|
/* USER CODE BEGIN SysInit */
|
|
|
|
/* USER CODE END SysInit */
|
|
|
|
/* Initialize all configured peripherals */
|
|
MX_GPIO_Init();
|
|
8001966: f000 fa91 bl 8001e8c <MX_GPIO_Init>
|
|
MX_I2C2_Init();
|
|
800196a: f000 fa1f bl 8001dac <MX_I2C2_Init>
|
|
MX_USART1_UART_Init();
|
|
800196e: f000 fa5d bl 8001e2c <MX_USART1_UART_Init>
|
|
/* USER CODE BEGIN 2 */
|
|
|
|
// LCD44780 INIT
|
|
lcd_reset();
|
|
8001972: f7ff fd47 bl 8001404 <lcd_reset>
|
|
lcd_display_settings(1,0,0);
|
|
8001976: 2200 movs r2, #0
|
|
8001978: 2100 movs r1, #0
|
|
800197a: 2001 movs r0, #1
|
|
800197c: f7ff fe52 bl 8001624 <lcd_display_settings>
|
|
lcd_clear();
|
|
8001980: f7ff fe3e bl 8001600 <lcd_clear>
|
|
|
|
// LPS22 INIT
|
|
LPS22_Init();
|
|
8001984: f7ff fcde bl 8001344 <LPS22_Init>
|
|
|
|
// HTS221 INIT
|
|
HTS221_Init();
|
|
8001988: f7ff fc64 bl 8001254 <HTS221_Init>
|
|
|
|
// USART INTERRUPTIONS
|
|
HAL_UART_Receive_IT(&huart1, &rxByte, 1);
|
|
800198c: 2201 movs r2, #1
|
|
800198e: 49a4 ldr r1, [pc, #656] @ (8001c20 <main+0x2c8>)
|
|
8001990: 48a4 ldr r0, [pc, #656] @ (8001c24 <main+0x2cc>)
|
|
8001992: f003 fb01 bl 8004f98 <HAL_UART_Receive_IT>
|
|
/* Infinite loop */
|
|
/* USER CODE BEGIN WHILE */
|
|
while (1)
|
|
{
|
|
uint8_t str[20];
|
|
float pressure = LPS22_ReadPress();
|
|
8001996: f7ff fced bl 8001374 <LPS22_ReadPress>
|
|
800199a: ed87 0a0b vstr s0, [r7, #44] @ 0x2c
|
|
THSample ths = HTS221_Read();
|
|
800199e: f7ff fc73 bl 8001288 <HTS221_Read>
|
|
80019a2: eeb0 7a40 vmov.f32 s14, s0
|
|
80019a6: eef0 7a60 vmov.f32 s15, s1
|
|
80019aa: ed87 7a00 vstr s14, [r7]
|
|
80019ae: edc7 7a01 vstr s15, [r7, #4]
|
|
|
|
if (ths.temp > maxTemp) maxTemp = ths.temp;
|
|
80019b2: ed97 7a00 vldr s14, [r7]
|
|
80019b6: 4b9c ldr r3, [pc, #624] @ (8001c28 <main+0x2d0>)
|
|
80019b8: edd3 7a00 vldr s15, [r3]
|
|
80019bc: eeb4 7ae7 vcmpe.f32 s14, s15
|
|
80019c0: eef1 fa10 vmrs APSR_nzcv, fpscr
|
|
80019c4: dd02 ble.n 80019cc <main+0x74>
|
|
80019c6: 683b ldr r3, [r7, #0]
|
|
80019c8: 4a97 ldr r2, [pc, #604] @ (8001c28 <main+0x2d0>)
|
|
80019ca: 6013 str r3, [r2, #0]
|
|
if (ths.temp < minTemp) minTemp = ths.temp;
|
|
80019cc: ed97 7a00 vldr s14, [r7]
|
|
80019d0: 4b96 ldr r3, [pc, #600] @ (8001c2c <main+0x2d4>)
|
|
80019d2: edd3 7a00 vldr s15, [r3]
|
|
80019d6: eeb4 7ae7 vcmpe.f32 s14, s15
|
|
80019da: eef1 fa10 vmrs APSR_nzcv, fpscr
|
|
80019de: d502 bpl.n 80019e6 <main+0x8e>
|
|
80019e0: 683b ldr r3, [r7, #0]
|
|
80019e2: 4a92 ldr r2, [pc, #584] @ (8001c2c <main+0x2d4>)
|
|
80019e4: 6013 str r3, [r2, #0]
|
|
if (ths.hum > maxHum) maxHum = ths.hum;
|
|
80019e6: ed97 7a01 vldr s14, [r7, #4]
|
|
80019ea: 4b91 ldr r3, [pc, #580] @ (8001c30 <main+0x2d8>)
|
|
80019ec: edd3 7a00 vldr s15, [r3]
|
|
80019f0: eeb4 7ae7 vcmpe.f32 s14, s15
|
|
80019f4: eef1 fa10 vmrs APSR_nzcv, fpscr
|
|
80019f8: dd02 ble.n 8001a00 <main+0xa8>
|
|
80019fa: 687b ldr r3, [r7, #4]
|
|
80019fc: 4a8c ldr r2, [pc, #560] @ (8001c30 <main+0x2d8>)
|
|
80019fe: 6013 str r3, [r2, #0]
|
|
if (ths.hum < minHum) minHum = ths.hum;
|
|
8001a00: ed97 7a01 vldr s14, [r7, #4]
|
|
8001a04: 4b8b ldr r3, [pc, #556] @ (8001c34 <main+0x2dc>)
|
|
8001a06: edd3 7a00 vldr s15, [r3]
|
|
8001a0a: eeb4 7ae7 vcmpe.f32 s14, s15
|
|
8001a0e: eef1 fa10 vmrs APSR_nzcv, fpscr
|
|
8001a12: d502 bpl.n 8001a1a <main+0xc2>
|
|
8001a14: 687b ldr r3, [r7, #4]
|
|
8001a16: 4a87 ldr r2, [pc, #540] @ (8001c34 <main+0x2dc>)
|
|
8001a18: 6013 str r3, [r2, #0]
|
|
if (pressure > maxPress) maxPress = pressure;
|
|
8001a1a: 4b87 ldr r3, [pc, #540] @ (8001c38 <main+0x2e0>)
|
|
8001a1c: edd3 7a00 vldr s15, [r3]
|
|
8001a20: ed97 7a0b vldr s14, [r7, #44] @ 0x2c
|
|
8001a24: eeb4 7ae7 vcmpe.f32 s14, s15
|
|
8001a28: eef1 fa10 vmrs APSR_nzcv, fpscr
|
|
8001a2c: dd02 ble.n 8001a34 <main+0xdc>
|
|
8001a2e: 4a82 ldr r2, [pc, #520] @ (8001c38 <main+0x2e0>)
|
|
8001a30: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8001a32: 6013 str r3, [r2, #0]
|
|
if (pressure < minPress) minPress = pressure;
|
|
8001a34: 4b81 ldr r3, [pc, #516] @ (8001c3c <main+0x2e4>)
|
|
8001a36: edd3 7a00 vldr s15, [r3]
|
|
8001a3a: ed97 7a0b vldr s14, [r7, #44] @ 0x2c
|
|
8001a3e: eeb4 7ae7 vcmpe.f32 s14, s15
|
|
8001a42: eef1 fa10 vmrs APSR_nzcv, fpscr
|
|
8001a46: d502 bpl.n 8001a4e <main+0xf6>
|
|
8001a48: 4a7c ldr r2, [pc, #496] @ (8001c3c <main+0x2e4>)
|
|
8001a4a: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8001a4c: 6013 str r3, [r2, #0]
|
|
|
|
float tempToShow = useFahrenheit ? (ths.temp * 9.0 / 5.0) + 32 : ths.temp; // convertir a ºF si es necesario
|
|
8001a4e: 4b7c ldr r3, [pc, #496] @ (8001c40 <main+0x2e8>)
|
|
8001a50: 681b ldr r3, [r3, #0]
|
|
8001a52: 2b00 cmp r3, #0
|
|
8001a54: d022 beq.n 8001a9c <main+0x144>
|
|
8001a56: 683b ldr r3, [r7, #0]
|
|
8001a58: 4618 mov r0, r3
|
|
8001a5a: f7fe fd75 bl 8000548 <__aeabi_f2d>
|
|
8001a5e: f04f 0200 mov.w r2, #0
|
|
8001a62: 4b78 ldr r3, [pc, #480] @ (8001c44 <main+0x2ec>)
|
|
8001a64: f7fe fdc8 bl 80005f8 <__aeabi_dmul>
|
|
8001a68: 4602 mov r2, r0
|
|
8001a6a: 460b mov r3, r1
|
|
8001a6c: 4610 mov r0, r2
|
|
8001a6e: 4619 mov r1, r3
|
|
8001a70: f04f 0200 mov.w r2, #0
|
|
8001a74: 4b74 ldr r3, [pc, #464] @ (8001c48 <main+0x2f0>)
|
|
8001a76: f7fe fee9 bl 800084c <__aeabi_ddiv>
|
|
8001a7a: 4602 mov r2, r0
|
|
8001a7c: 460b mov r3, r1
|
|
8001a7e: 4610 mov r0, r2
|
|
8001a80: 4619 mov r1, r3
|
|
8001a82: f04f 0200 mov.w r2, #0
|
|
8001a86: 4b71 ldr r3, [pc, #452] @ (8001c4c <main+0x2f4>)
|
|
8001a88: f7fe fc00 bl 800028c <__adddf3>
|
|
8001a8c: 4602 mov r2, r0
|
|
8001a8e: 460b mov r3, r1
|
|
8001a90: 4610 mov r0, r2
|
|
8001a92: 4619 mov r1, r3
|
|
8001a94: f7ff f888 bl 8000ba8 <__aeabi_d2f>
|
|
8001a98: 4603 mov r3, r0
|
|
8001a9a: e000 b.n 8001a9e <main+0x146>
|
|
8001a9c: 683b ldr r3, [r7, #0]
|
|
8001a9e: 62bb str r3, [r7, #40] @ 0x28
|
|
float pressureToShow = useFahrenheit ? pressure * 0.75006 : pressure; // convertir a mmHg si es necesario
|
|
8001aa0: 4b67 ldr r3, [pc, #412] @ (8001c40 <main+0x2e8>)
|
|
8001aa2: 681b ldr r3, [r3, #0]
|
|
8001aa4: 2b00 cmp r3, #0
|
|
8001aa6: d00f beq.n 8001ac8 <main+0x170>
|
|
8001aa8: 6af8 ldr r0, [r7, #44] @ 0x2c
|
|
8001aaa: f7fe fd4d bl 8000548 <__aeabi_f2d>
|
|
8001aae: a35a add r3, pc, #360 @ (adr r3, 8001c18 <main+0x2c0>)
|
|
8001ab0: e9d3 2300 ldrd r2, r3, [r3]
|
|
8001ab4: f7fe fda0 bl 80005f8 <__aeabi_dmul>
|
|
8001ab8: 4602 mov r2, r0
|
|
8001aba: 460b mov r3, r1
|
|
8001abc: 4610 mov r0, r2
|
|
8001abe: 4619 mov r1, r3
|
|
8001ac0: f7ff f872 bl 8000ba8 <__aeabi_d2f>
|
|
8001ac4: 4603 mov r3, r0
|
|
8001ac6: e000 b.n 8001aca <main+0x172>
|
|
8001ac8: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
8001aca: 627b str r3, [r7, #36] @ 0x24
|
|
char tempUnit = useFahrenheit ? 'F' : 'C';
|
|
8001acc: 4b5c ldr r3, [pc, #368] @ (8001c40 <main+0x2e8>)
|
|
8001ace: 681b ldr r3, [r3, #0]
|
|
8001ad0: 2b00 cmp r3, #0
|
|
8001ad2: d001 beq.n 8001ad8 <main+0x180>
|
|
8001ad4: 2346 movs r3, #70 @ 0x46
|
|
8001ad6: e000 b.n 8001ada <main+0x182>
|
|
8001ad8: 2343 movs r3, #67 @ 0x43
|
|
8001ada: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
const char *pressUnit = useFahrenheit ? "mmHg" : "hPa";
|
|
8001ade: 4b58 ldr r3, [pc, #352] @ (8001c40 <main+0x2e8>)
|
|
8001ae0: 681b ldr r3, [r3, #0]
|
|
8001ae2: 2b00 cmp r3, #0
|
|
8001ae4: d001 beq.n 8001aea <main+0x192>
|
|
8001ae6: 4b5a ldr r3, [pc, #360] @ (8001c50 <main+0x2f8>)
|
|
8001ae8: e000 b.n 8001aec <main+0x194>
|
|
8001aea: 4b5a ldr r3, [pc, #360] @ (8001c54 <main+0x2fc>)
|
|
8001aec: 61fb str r3, [r7, #28]
|
|
|
|
switch (displayMode) {
|
|
8001aee: 4b5a ldr r3, [pc, #360] @ (8001c58 <main+0x300>)
|
|
8001af0: 781b ldrb r3, [r3, #0]
|
|
8001af2: 2b6d cmp r3, #109 @ 0x6d
|
|
8001af4: d002 beq.n 8001afc <main+0x1a4>
|
|
8001af6: 2b6e cmp r3, #110 @ 0x6e
|
|
8001af8: d047 beq.n 8001b8a <main+0x232>
|
|
8001afa: e0b7 b.n 8001c6c <main+0x314>
|
|
case 'm':
|
|
sprintf(str, "Max: %.1f%c %.1f%%", maxTemp, tempUnit, maxHum);
|
|
8001afc: 4b4a ldr r3, [pc, #296] @ (8001c28 <main+0x2d0>)
|
|
8001afe: 681b ldr r3, [r3, #0]
|
|
8001b00: 4618 mov r0, r3
|
|
8001b02: f7fe fd21 bl 8000548 <__aeabi_f2d>
|
|
8001b06: 4604 mov r4, r0
|
|
8001b08: 460d mov r5, r1
|
|
8001b0a: f897 6023 ldrb.w r6, [r7, #35] @ 0x23
|
|
8001b0e: 4b48 ldr r3, [pc, #288] @ (8001c30 <main+0x2d8>)
|
|
8001b10: 681b ldr r3, [r3, #0]
|
|
8001b12: 4618 mov r0, r3
|
|
8001b14: f7fe fd18 bl 8000548 <__aeabi_f2d>
|
|
8001b18: 4602 mov r2, r0
|
|
8001b1a: 460b mov r3, r1
|
|
8001b1c: f107 0008 add.w r0, r7, #8
|
|
8001b20: e9cd 2302 strd r2, r3, [sp, #8]
|
|
8001b24: 9600 str r6, [sp, #0]
|
|
8001b26: 4622 mov r2, r4
|
|
8001b28: 462b mov r3, r5
|
|
8001b2a: 494c ldr r1, [pc, #304] @ (8001c5c <main+0x304>)
|
|
8001b2c: f005 fa70 bl 8007010 <siprintf>
|
|
moveToXY(0, 0);
|
|
8001b30: 2100 movs r1, #0
|
|
8001b32: 2000 movs r0, #0
|
|
8001b34: f7ff fe1c bl 8001770 <moveToXY>
|
|
lcd_print(str);
|
|
8001b38: f107 0308 add.w r3, r7, #8
|
|
8001b3c: 4618 mov r0, r3
|
|
8001b3e: f7ff fda5 bl 800168c <lcd_print>
|
|
printf("%s\n\r", str); // Enviar a consola UART
|
|
8001b42: f107 0308 add.w r3, r7, #8
|
|
8001b46: 4619 mov r1, r3
|
|
8001b48: 4845 ldr r0, [pc, #276] @ (8001c60 <main+0x308>)
|
|
8001b4a: f005 fa4f bl 8006fec <iprintf>
|
|
|
|
sprintf(str, "Pres: %.1f%s", maxPress, pressUnit);
|
|
8001b4e: 4b3a ldr r3, [pc, #232] @ (8001c38 <main+0x2e0>)
|
|
8001b50: 681b ldr r3, [r3, #0]
|
|
8001b52: 4618 mov r0, r3
|
|
8001b54: f7fe fcf8 bl 8000548 <__aeabi_f2d>
|
|
8001b58: 4602 mov r2, r0
|
|
8001b5a: 460b mov r3, r1
|
|
8001b5c: f107 0008 add.w r0, r7, #8
|
|
8001b60: 69f9 ldr r1, [r7, #28]
|
|
8001b62: 9100 str r1, [sp, #0]
|
|
8001b64: 493f ldr r1, [pc, #252] @ (8001c64 <main+0x30c>)
|
|
8001b66: f005 fa53 bl 8007010 <siprintf>
|
|
moveToXY(1, 1);
|
|
8001b6a: 2101 movs r1, #1
|
|
8001b6c: 2001 movs r0, #1
|
|
8001b6e: f7ff fdff bl 8001770 <moveToXY>
|
|
lcd_print(str);
|
|
8001b72: f107 0308 add.w r3, r7, #8
|
|
8001b76: 4618 mov r0, r3
|
|
8001b78: f7ff fd88 bl 800168c <lcd_print>
|
|
printf("%s\n\r", str); // Enviar a consola UART
|
|
8001b7c: f107 0308 add.w r3, r7, #8
|
|
8001b80: 4619 mov r1, r3
|
|
8001b82: 4837 ldr r0, [pc, #220] @ (8001c60 <main+0x308>)
|
|
8001b84: f005 fa32 bl 8006fec <iprintf>
|
|
break;
|
|
8001b88: e0b2 b.n 8001cf0 <main+0x398>
|
|
|
|
case 'n':
|
|
sprintf(str, "Min: %.1f%c %.1f%%", minTemp, tempUnit, minHum);
|
|
8001b8a: 4b28 ldr r3, [pc, #160] @ (8001c2c <main+0x2d4>)
|
|
8001b8c: 681b ldr r3, [r3, #0]
|
|
8001b8e: 4618 mov r0, r3
|
|
8001b90: f7fe fcda bl 8000548 <__aeabi_f2d>
|
|
8001b94: 4604 mov r4, r0
|
|
8001b96: 460d mov r5, r1
|
|
8001b98: f897 6023 ldrb.w r6, [r7, #35] @ 0x23
|
|
8001b9c: 4b25 ldr r3, [pc, #148] @ (8001c34 <main+0x2dc>)
|
|
8001b9e: 681b ldr r3, [r3, #0]
|
|
8001ba0: 4618 mov r0, r3
|
|
8001ba2: f7fe fcd1 bl 8000548 <__aeabi_f2d>
|
|
8001ba6: 4602 mov r2, r0
|
|
8001ba8: 460b mov r3, r1
|
|
8001baa: f107 0008 add.w r0, r7, #8
|
|
8001bae: e9cd 2302 strd r2, r3, [sp, #8]
|
|
8001bb2: 9600 str r6, [sp, #0]
|
|
8001bb4: 4622 mov r2, r4
|
|
8001bb6: 462b mov r3, r5
|
|
8001bb8: 492b ldr r1, [pc, #172] @ (8001c68 <main+0x310>)
|
|
8001bba: f005 fa29 bl 8007010 <siprintf>
|
|
moveToXY(0, 0);
|
|
8001bbe: 2100 movs r1, #0
|
|
8001bc0: 2000 movs r0, #0
|
|
8001bc2: f7ff fdd5 bl 8001770 <moveToXY>
|
|
lcd_print(str);
|
|
8001bc6: f107 0308 add.w r3, r7, #8
|
|
8001bca: 4618 mov r0, r3
|
|
8001bcc: f7ff fd5e bl 800168c <lcd_print>
|
|
printf("%s\n\r", str); // Enviar a consola UART
|
|
8001bd0: f107 0308 add.w r3, r7, #8
|
|
8001bd4: 4619 mov r1, r3
|
|
8001bd6: 4822 ldr r0, [pc, #136] @ (8001c60 <main+0x308>)
|
|
8001bd8: f005 fa08 bl 8006fec <iprintf>
|
|
|
|
sprintf(str, "Pres: %.1f%s", minPress, pressUnit);
|
|
8001bdc: 4b17 ldr r3, [pc, #92] @ (8001c3c <main+0x2e4>)
|
|
8001bde: 681b ldr r3, [r3, #0]
|
|
8001be0: 4618 mov r0, r3
|
|
8001be2: f7fe fcb1 bl 8000548 <__aeabi_f2d>
|
|
8001be6: 4602 mov r2, r0
|
|
8001be8: 460b mov r3, r1
|
|
8001bea: f107 0008 add.w r0, r7, #8
|
|
8001bee: 69f9 ldr r1, [r7, #28]
|
|
8001bf0: 9100 str r1, [sp, #0]
|
|
8001bf2: 491c ldr r1, [pc, #112] @ (8001c64 <main+0x30c>)
|
|
8001bf4: f005 fa0c bl 8007010 <siprintf>
|
|
moveToXY(1, 1);
|
|
8001bf8: 2101 movs r1, #1
|
|
8001bfa: 2001 movs r0, #1
|
|
8001bfc: f7ff fdb8 bl 8001770 <moveToXY>
|
|
lcd_print(str);
|
|
8001c00: f107 0308 add.w r3, r7, #8
|
|
8001c04: 4618 mov r0, r3
|
|
8001c06: f7ff fd41 bl 800168c <lcd_print>
|
|
printf("%s\n\r", str); // Enviar a consola UART
|
|
8001c0a: f107 0308 add.w r3, r7, #8
|
|
8001c0e: 4619 mov r1, r3
|
|
8001c10: 4813 ldr r0, [pc, #76] @ (8001c60 <main+0x308>)
|
|
8001c12: f005 f9eb bl 8006fec <iprintf>
|
|
break;
|
|
8001c16: e06b b.n 8001cf0 <main+0x398>
|
|
8001c18: d4413554 .word 0xd4413554
|
|
8001c1c: 3fe8007d .word 0x3fe8007d
|
|
8001c20: 20000314 .word 0x20000314
|
|
8001c24: 2000028c .word 0x2000028c
|
|
8001c28: 20000004 .word 0x20000004
|
|
8001c2c: 20000008 .word 0x20000008
|
|
8001c30: 2000031c .word 0x2000031c
|
|
8001c34: 2000000c .word 0x2000000c
|
|
8001c38: 20000320 .word 0x20000320
|
|
8001c3c: 20000010 .word 0x20000010
|
|
8001c40: 20000318 .word 0x20000318
|
|
8001c44: 40220000 .word 0x40220000
|
|
8001c48: 40140000 .word 0x40140000
|
|
8001c4c: 40400000 .word 0x40400000
|
|
8001c50: 08009298 .word 0x08009298
|
|
8001c54: 080092a0 .word 0x080092a0
|
|
8001c58: 20000000 .word 0x20000000
|
|
8001c5c: 080092a4 .word 0x080092a4
|
|
8001c60: 080092b8 .word 0x080092b8
|
|
8001c64: 080092c0 .word 0x080092c0
|
|
8001c68: 080092d0 .word 0x080092d0
|
|
|
|
default:
|
|
sprintf(str, "T:%.1f%c H:%.1f%%", tempToShow, tempUnit, ths.hum);
|
|
8001c6c: 6ab8 ldr r0, [r7, #40] @ 0x28
|
|
8001c6e: f7fe fc6b bl 8000548 <__aeabi_f2d>
|
|
8001c72: 4604 mov r4, r0
|
|
8001c74: 460d mov r5, r1
|
|
8001c76: f897 6023 ldrb.w r6, [r7, #35] @ 0x23
|
|
8001c7a: 687b ldr r3, [r7, #4]
|
|
8001c7c: 4618 mov r0, r3
|
|
8001c7e: f7fe fc63 bl 8000548 <__aeabi_f2d>
|
|
8001c82: 4602 mov r2, r0
|
|
8001c84: 460b mov r3, r1
|
|
8001c86: f107 0008 add.w r0, r7, #8
|
|
8001c8a: e9cd 2302 strd r2, r3, [sp, #8]
|
|
8001c8e: 9600 str r6, [sp, #0]
|
|
8001c90: 4622 mov r2, r4
|
|
8001c92: 462b mov r3, r5
|
|
8001c94: 4919 ldr r1, [pc, #100] @ (8001cfc <main+0x3a4>)
|
|
8001c96: f005 f9bb bl 8007010 <siprintf>
|
|
moveToXY(0, 0);
|
|
8001c9a: 2100 movs r1, #0
|
|
8001c9c: 2000 movs r0, #0
|
|
8001c9e: f7ff fd67 bl 8001770 <moveToXY>
|
|
lcd_print(str);
|
|
8001ca2: f107 0308 add.w r3, r7, #8
|
|
8001ca6: 4618 mov r0, r3
|
|
8001ca8: f7ff fcf0 bl 800168c <lcd_print>
|
|
printf("%s\n\r", str); // Enviar a consola UART
|
|
8001cac: f107 0308 add.w r3, r7, #8
|
|
8001cb0: 4619 mov r1, r3
|
|
8001cb2: 4813 ldr r0, [pc, #76] @ (8001d00 <main+0x3a8>)
|
|
8001cb4: f005 f99a bl 8006fec <iprintf>
|
|
|
|
sprintf(str, "Pres: %.1f%s", pressureToShow, pressUnit);
|
|
8001cb8: 6a78 ldr r0, [r7, #36] @ 0x24
|
|
8001cba: f7fe fc45 bl 8000548 <__aeabi_f2d>
|
|
8001cbe: 4602 mov r2, r0
|
|
8001cc0: 460b mov r3, r1
|
|
8001cc2: f107 0008 add.w r0, r7, #8
|
|
8001cc6: 69f9 ldr r1, [r7, #28]
|
|
8001cc8: 9100 str r1, [sp, #0]
|
|
8001cca: 490e ldr r1, [pc, #56] @ (8001d04 <main+0x3ac>)
|
|
8001ccc: f005 f9a0 bl 8007010 <siprintf>
|
|
moveToXY(1, 1);
|
|
8001cd0: 2101 movs r1, #1
|
|
8001cd2: 2001 movs r0, #1
|
|
8001cd4: f7ff fd4c bl 8001770 <moveToXY>
|
|
lcd_print(str);
|
|
8001cd8: f107 0308 add.w r3, r7, #8
|
|
8001cdc: 4618 mov r0, r3
|
|
8001cde: f7ff fcd5 bl 800168c <lcd_print>
|
|
printf("%s\n\r", str); // Enviar a consola UART
|
|
8001ce2: f107 0308 add.w r3, r7, #8
|
|
8001ce6: 4619 mov r1, r3
|
|
8001ce8: 4805 ldr r0, [pc, #20] @ (8001d00 <main+0x3a8>)
|
|
8001cea: f005 f97f bl 8006fec <iprintf>
|
|
break;
|
|
8001cee: bf00 nop
|
|
}
|
|
|
|
|
|
|
|
|
|
HAL_Delay(500);
|
|
8001cf0: f44f 70fa mov.w r0, #500 @ 0x1f4
|
|
8001cf4: f000 fbbe bl 8002474 <HAL_Delay>
|
|
{
|
|
8001cf8: e64d b.n 8001996 <main+0x3e>
|
|
8001cfa: bf00 nop
|
|
8001cfc: 080092e4 .word 0x080092e4
|
|
8001d00: 080092b8 .word 0x080092b8
|
|
8001d04: 080092c0 .word 0x080092c0
|
|
|
|
08001d08 <SystemClock_Config>:
|
|
/**
|
|
* @brief System Clock Configuration
|
|
* @retval None
|
|
*/
|
|
void SystemClock_Config(void)
|
|
{
|
|
8001d08: b580 push {r7, lr}
|
|
8001d0a: b096 sub sp, #88 @ 0x58
|
|
8001d0c: af00 add r7, sp, #0
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
|
8001d0e: f107 0314 add.w r3, r7, #20
|
|
8001d12: 2244 movs r2, #68 @ 0x44
|
|
8001d14: 2100 movs r1, #0
|
|
8001d16: 4618 mov r0, r3
|
|
8001d18: f005 f9df bl 80070da <memset>
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
|
8001d1c: 463b mov r3, r7
|
|
8001d1e: 2200 movs r2, #0
|
|
8001d20: 601a str r2, [r3, #0]
|
|
8001d22: 605a str r2, [r3, #4]
|
|
8001d24: 609a str r2, [r3, #8]
|
|
8001d26: 60da str r2, [r3, #12]
|
|
8001d28: 611a str r2, [r3, #16]
|
|
|
|
/** Configure the main internal regulator output voltage
|
|
*/
|
|
if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK)
|
|
8001d2a: f44f 7000 mov.w r0, #512 @ 0x200
|
|
8001d2e: f001 fd49 bl 80037c4 <HAL_PWREx_ControlVoltageScaling>
|
|
8001d32: 4603 mov r3, r0
|
|
8001d34: 2b00 cmp r3, #0
|
|
8001d36: d001 beq.n 8001d3c <SystemClock_Config+0x34>
|
|
{
|
|
Error_Handler();
|
|
8001d38: f000 f8fe bl 8001f38 <Error_Handler>
|
|
}
|
|
|
|
/** Initializes the RCC Oscillators according to the specified parameters
|
|
* in the RCC_OscInitTypeDef structure.
|
|
*/
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
|
|
8001d3c: 2310 movs r3, #16
|
|
8001d3e: 617b str r3, [r7, #20]
|
|
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
|
|
8001d40: 2301 movs r3, #1
|
|
8001d42: 62fb str r3, [r7, #44] @ 0x2c
|
|
RCC_OscInitStruct.MSICalibrationValue = 0;
|
|
8001d44: 2300 movs r3, #0
|
|
8001d46: 633b str r3, [r7, #48] @ 0x30
|
|
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
|
|
8001d48: 2360 movs r3, #96 @ 0x60
|
|
8001d4a: 637b str r3, [r7, #52] @ 0x34
|
|
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
|
|
8001d4c: 2302 movs r3, #2
|
|
8001d4e: 63fb str r3, [r7, #60] @ 0x3c
|
|
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
|
|
8001d50: 2301 movs r3, #1
|
|
8001d52: 643b str r3, [r7, #64] @ 0x40
|
|
RCC_OscInitStruct.PLL.PLLM = 1;
|
|
8001d54: 2301 movs r3, #1
|
|
8001d56: 647b str r3, [r7, #68] @ 0x44
|
|
RCC_OscInitStruct.PLL.PLLN = 40;
|
|
8001d58: 2328 movs r3, #40 @ 0x28
|
|
8001d5a: 64bb str r3, [r7, #72] @ 0x48
|
|
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV7;
|
|
8001d5c: 2307 movs r3, #7
|
|
8001d5e: 64fb str r3, [r7, #76] @ 0x4c
|
|
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
|
|
8001d60: 2302 movs r3, #2
|
|
8001d62: 653b str r3, [r7, #80] @ 0x50
|
|
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
|
|
8001d64: 2302 movs r3, #2
|
|
8001d66: 657b str r3, [r7, #84] @ 0x54
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
|
8001d68: f107 0314 add.w r3, r7, #20
|
|
8001d6c: 4618 mov r0, r3
|
|
8001d6e: f001 fd7f bl 8003870 <HAL_RCC_OscConfig>
|
|
8001d72: 4603 mov r3, r0
|
|
8001d74: 2b00 cmp r3, #0
|
|
8001d76: d001 beq.n 8001d7c <SystemClock_Config+0x74>
|
|
{
|
|
Error_Handler();
|
|
8001d78: f000 f8de bl 8001f38 <Error_Handler>
|
|
}
|
|
|
|
/** Initializes the CPU, AHB and APB buses clocks
|
|
*/
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
|
8001d7c: 230f movs r3, #15
|
|
8001d7e: 603b str r3, [r7, #0]
|
|
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
|
|
8001d80: 2303 movs r3, #3
|
|
8001d82: 607b str r3, [r7, #4]
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
|
|
8001d84: 2300 movs r3, #0
|
|
8001d86: 60bb str r3, [r7, #8]
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
|
|
8001d88: 2300 movs r3, #0
|
|
8001d8a: 60fb str r3, [r7, #12]
|
|
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
|
|
8001d8c: 2300 movs r3, #0
|
|
8001d8e: 613b str r3, [r7, #16]
|
|
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
|
|
8001d90: 463b mov r3, r7
|
|
8001d92: 2104 movs r1, #4
|
|
8001d94: 4618 mov r0, r3
|
|
8001d96: f002 f947 bl 8004028 <HAL_RCC_ClockConfig>
|
|
8001d9a: 4603 mov r3, r0
|
|
8001d9c: 2b00 cmp r3, #0
|
|
8001d9e: d001 beq.n 8001da4 <SystemClock_Config+0x9c>
|
|
{
|
|
Error_Handler();
|
|
8001da0: f000 f8ca bl 8001f38 <Error_Handler>
|
|
}
|
|
}
|
|
8001da4: bf00 nop
|
|
8001da6: 3758 adds r7, #88 @ 0x58
|
|
8001da8: 46bd mov sp, r7
|
|
8001daa: bd80 pop {r7, pc}
|
|
|
|
08001dac <MX_I2C2_Init>:
|
|
* @brief I2C2 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_I2C2_Init(void)
|
|
{
|
|
8001dac: b580 push {r7, lr}
|
|
8001dae: af00 add r7, sp, #0
|
|
/* USER CODE END I2C2_Init 0 */
|
|
|
|
/* USER CODE BEGIN I2C2_Init 1 */
|
|
|
|
/* USER CODE END I2C2_Init 1 */
|
|
hi2c2.Instance = I2C2;
|
|
8001db0: 4b1b ldr r3, [pc, #108] @ (8001e20 <MX_I2C2_Init+0x74>)
|
|
8001db2: 4a1c ldr r2, [pc, #112] @ (8001e24 <MX_I2C2_Init+0x78>)
|
|
8001db4: 601a str r2, [r3, #0]
|
|
hi2c2.Init.Timing = 0x10D19CE4;
|
|
8001db6: 4b1a ldr r3, [pc, #104] @ (8001e20 <MX_I2C2_Init+0x74>)
|
|
8001db8: 4a1b ldr r2, [pc, #108] @ (8001e28 <MX_I2C2_Init+0x7c>)
|
|
8001dba: 605a str r2, [r3, #4]
|
|
hi2c2.Init.OwnAddress1 = 0;
|
|
8001dbc: 4b18 ldr r3, [pc, #96] @ (8001e20 <MX_I2C2_Init+0x74>)
|
|
8001dbe: 2200 movs r2, #0
|
|
8001dc0: 609a str r2, [r3, #8]
|
|
hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT;
|
|
8001dc2: 4b17 ldr r3, [pc, #92] @ (8001e20 <MX_I2C2_Init+0x74>)
|
|
8001dc4: 2201 movs r2, #1
|
|
8001dc6: 60da str r2, [r3, #12]
|
|
hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE;
|
|
8001dc8: 4b15 ldr r3, [pc, #84] @ (8001e20 <MX_I2C2_Init+0x74>)
|
|
8001dca: 2200 movs r2, #0
|
|
8001dcc: 611a str r2, [r3, #16]
|
|
hi2c2.Init.OwnAddress2 = 0;
|
|
8001dce: 4b14 ldr r3, [pc, #80] @ (8001e20 <MX_I2C2_Init+0x74>)
|
|
8001dd0: 2200 movs r2, #0
|
|
8001dd2: 615a str r2, [r3, #20]
|
|
hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
|
|
8001dd4: 4b12 ldr r3, [pc, #72] @ (8001e20 <MX_I2C2_Init+0x74>)
|
|
8001dd6: 2200 movs r2, #0
|
|
8001dd8: 619a str r2, [r3, #24]
|
|
hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE;
|
|
8001dda: 4b11 ldr r3, [pc, #68] @ (8001e20 <MX_I2C2_Init+0x74>)
|
|
8001ddc: 2200 movs r2, #0
|
|
8001dde: 61da str r2, [r3, #28]
|
|
hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE;
|
|
8001de0: 4b0f ldr r3, [pc, #60] @ (8001e20 <MX_I2C2_Init+0x74>)
|
|
8001de2: 2200 movs r2, #0
|
|
8001de4: 621a str r2, [r3, #32]
|
|
if (HAL_I2C_Init(&hi2c2) != HAL_OK)
|
|
8001de6: 480e ldr r0, [pc, #56] @ (8001e20 <MX_I2C2_Init+0x74>)
|
|
8001de8: f000 feba bl 8002b60 <HAL_I2C_Init>
|
|
8001dec: 4603 mov r3, r0
|
|
8001dee: 2b00 cmp r3, #0
|
|
8001df0: d001 beq.n 8001df6 <MX_I2C2_Init+0x4a>
|
|
{
|
|
Error_Handler();
|
|
8001df2: f000 f8a1 bl 8001f38 <Error_Handler>
|
|
}
|
|
|
|
/** Configure Analogue filter
|
|
*/
|
|
if (HAL_I2CEx_ConfigAnalogFilter(&hi2c2, I2C_ANALOGFILTER_ENABLE) != HAL_OK)
|
|
8001df6: 2100 movs r1, #0
|
|
8001df8: 4809 ldr r0, [pc, #36] @ (8001e20 <MX_I2C2_Init+0x74>)
|
|
8001dfa: f001 fc3d bl 8003678 <HAL_I2CEx_ConfigAnalogFilter>
|
|
8001dfe: 4603 mov r3, r0
|
|
8001e00: 2b00 cmp r3, #0
|
|
8001e02: d001 beq.n 8001e08 <MX_I2C2_Init+0x5c>
|
|
{
|
|
Error_Handler();
|
|
8001e04: f000 f898 bl 8001f38 <Error_Handler>
|
|
}
|
|
|
|
/** Configure Digital filter
|
|
*/
|
|
if (HAL_I2CEx_ConfigDigitalFilter(&hi2c2, 0) != HAL_OK)
|
|
8001e08: 2100 movs r1, #0
|
|
8001e0a: 4805 ldr r0, [pc, #20] @ (8001e20 <MX_I2C2_Init+0x74>)
|
|
8001e0c: f001 fc7f bl 800370e <HAL_I2CEx_ConfigDigitalFilter>
|
|
8001e10: 4603 mov r3, r0
|
|
8001e12: 2b00 cmp r3, #0
|
|
8001e14: d001 beq.n 8001e1a <MX_I2C2_Init+0x6e>
|
|
{
|
|
Error_Handler();
|
|
8001e16: f000 f88f bl 8001f38 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN I2C2_Init 2 */
|
|
|
|
/* USER CODE END I2C2_Init 2 */
|
|
|
|
}
|
|
8001e1a: bf00 nop
|
|
8001e1c: bd80 pop {r7, pc}
|
|
8001e1e: bf00 nop
|
|
8001e20: 20000238 .word 0x20000238
|
|
8001e24: 40005800 .word 0x40005800
|
|
8001e28: 10d19ce4 .word 0x10d19ce4
|
|
|
|
08001e2c <MX_USART1_UART_Init>:
|
|
* @brief USART1 Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_USART1_UART_Init(void)
|
|
{
|
|
8001e2c: b580 push {r7, lr}
|
|
8001e2e: af00 add r7, sp, #0
|
|
/* USER CODE END USART1_Init 0 */
|
|
|
|
/* USER CODE BEGIN USART1_Init 1 */
|
|
|
|
/* USER CODE END USART1_Init 1 */
|
|
huart1.Instance = USART1;
|
|
8001e30: 4b14 ldr r3, [pc, #80] @ (8001e84 <MX_USART1_UART_Init+0x58>)
|
|
8001e32: 4a15 ldr r2, [pc, #84] @ (8001e88 <MX_USART1_UART_Init+0x5c>)
|
|
8001e34: 601a str r2, [r3, #0]
|
|
huart1.Init.BaudRate = 115200;
|
|
8001e36: 4b13 ldr r3, [pc, #76] @ (8001e84 <MX_USART1_UART_Init+0x58>)
|
|
8001e38: f44f 32e1 mov.w r2, #115200 @ 0x1c200
|
|
8001e3c: 605a str r2, [r3, #4]
|
|
huart1.Init.WordLength = UART_WORDLENGTH_8B;
|
|
8001e3e: 4b11 ldr r3, [pc, #68] @ (8001e84 <MX_USART1_UART_Init+0x58>)
|
|
8001e40: 2200 movs r2, #0
|
|
8001e42: 609a str r2, [r3, #8]
|
|
huart1.Init.StopBits = UART_STOPBITS_1;
|
|
8001e44: 4b0f ldr r3, [pc, #60] @ (8001e84 <MX_USART1_UART_Init+0x58>)
|
|
8001e46: 2200 movs r2, #0
|
|
8001e48: 60da str r2, [r3, #12]
|
|
huart1.Init.Parity = UART_PARITY_NONE;
|
|
8001e4a: 4b0e ldr r3, [pc, #56] @ (8001e84 <MX_USART1_UART_Init+0x58>)
|
|
8001e4c: 2200 movs r2, #0
|
|
8001e4e: 611a str r2, [r3, #16]
|
|
huart1.Init.Mode = UART_MODE_TX_RX;
|
|
8001e50: 4b0c ldr r3, [pc, #48] @ (8001e84 <MX_USART1_UART_Init+0x58>)
|
|
8001e52: 220c movs r2, #12
|
|
8001e54: 615a str r2, [r3, #20]
|
|
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
8001e56: 4b0b ldr r3, [pc, #44] @ (8001e84 <MX_USART1_UART_Init+0x58>)
|
|
8001e58: 2200 movs r2, #0
|
|
8001e5a: 619a str r2, [r3, #24]
|
|
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
8001e5c: 4b09 ldr r3, [pc, #36] @ (8001e84 <MX_USART1_UART_Init+0x58>)
|
|
8001e5e: 2200 movs r2, #0
|
|
8001e60: 61da str r2, [r3, #28]
|
|
huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
|
|
8001e62: 4b08 ldr r3, [pc, #32] @ (8001e84 <MX_USART1_UART_Init+0x58>)
|
|
8001e64: 2200 movs r2, #0
|
|
8001e66: 621a str r2, [r3, #32]
|
|
huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
|
|
8001e68: 4b06 ldr r3, [pc, #24] @ (8001e84 <MX_USART1_UART_Init+0x58>)
|
|
8001e6a: 2200 movs r2, #0
|
|
8001e6c: 625a str r2, [r3, #36] @ 0x24
|
|
if (HAL_UART_Init(&huart1) != HAL_OK)
|
|
8001e6e: 4805 ldr r0, [pc, #20] @ (8001e84 <MX_USART1_UART_Init+0x58>)
|
|
8001e70: f002 ffba bl 8004de8 <HAL_UART_Init>
|
|
8001e74: 4603 mov r3, r0
|
|
8001e76: 2b00 cmp r3, #0
|
|
8001e78: d001 beq.n 8001e7e <MX_USART1_UART_Init+0x52>
|
|
{
|
|
Error_Handler();
|
|
8001e7a: f000 f85d bl 8001f38 <Error_Handler>
|
|
}
|
|
/* USER CODE BEGIN USART1_Init 2 */
|
|
|
|
/* USER CODE END USART1_Init 2 */
|
|
|
|
}
|
|
8001e7e: bf00 nop
|
|
8001e80: bd80 pop {r7, pc}
|
|
8001e82: bf00 nop
|
|
8001e84: 2000028c .word 0x2000028c
|
|
8001e88: 40013800 .word 0x40013800
|
|
|
|
08001e8c <MX_GPIO_Init>:
|
|
* @brief GPIO Initialization Function
|
|
* @param None
|
|
* @retval None
|
|
*/
|
|
static void MX_GPIO_Init(void)
|
|
{
|
|
8001e8c: b580 push {r7, lr}
|
|
8001e8e: b088 sub sp, #32
|
|
8001e90: af00 add r7, sp, #0
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8001e92: f107 030c add.w r3, r7, #12
|
|
8001e96: 2200 movs r2, #0
|
|
8001e98: 601a str r2, [r3, #0]
|
|
8001e9a: 605a str r2, [r3, #4]
|
|
8001e9c: 609a str r2, [r3, #8]
|
|
8001e9e: 60da str r2, [r3, #12]
|
|
8001ea0: 611a str r2, [r3, #16]
|
|
/* USER CODE BEGIN MX_GPIO_Init_1 */
|
|
/* USER CODE END MX_GPIO_Init_1 */
|
|
|
|
/* GPIO Ports Clock Enable */
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8001ea2: 4b23 ldr r3, [pc, #140] @ (8001f30 <MX_GPIO_Init+0xa4>)
|
|
8001ea4: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8001ea6: 4a22 ldr r2, [pc, #136] @ (8001f30 <MX_GPIO_Init+0xa4>)
|
|
8001ea8: f043 0301 orr.w r3, r3, #1
|
|
8001eac: 64d3 str r3, [r2, #76] @ 0x4c
|
|
8001eae: 4b20 ldr r3, [pc, #128] @ (8001f30 <MX_GPIO_Init+0xa4>)
|
|
8001eb0: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8001eb2: f003 0301 and.w r3, r3, #1
|
|
8001eb6: 60bb str r3, [r7, #8]
|
|
8001eb8: 68bb ldr r3, [r7, #8]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8001eba: 4b1d ldr r3, [pc, #116] @ (8001f30 <MX_GPIO_Init+0xa4>)
|
|
8001ebc: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8001ebe: 4a1c ldr r2, [pc, #112] @ (8001f30 <MX_GPIO_Init+0xa4>)
|
|
8001ec0: f043 0302 orr.w r3, r3, #2
|
|
8001ec4: 64d3 str r3, [r2, #76] @ 0x4c
|
|
8001ec6: 4b1a ldr r3, [pc, #104] @ (8001f30 <MX_GPIO_Init+0xa4>)
|
|
8001ec8: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8001eca: f003 0302 and.w r3, r3, #2
|
|
8001ece: 607b str r3, [r7, #4]
|
|
8001ed0: 687b ldr r3, [r7, #4]
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOA, Led_LCD_Pin|D4_LCD_Pin|D7_LCD_Pin|E_LCD_Pin, GPIO_PIN_RESET);
|
|
8001ed2: 2200 movs r2, #0
|
|
8001ed4: f248 011c movw r1, #32796 @ 0x801c
|
|
8001ed8: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
8001edc: f000 fe28 bl 8002b30 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pin Output Level */
|
|
HAL_GPIO_WritePin(GPIOB, D6_LCD_Pin|RS_LCD_Pin|D5_LCD_Pin, GPIO_PIN_RESET);
|
|
8001ee0: 2200 movs r2, #0
|
|
8001ee2: 2116 movs r1, #22
|
|
8001ee4: 4813 ldr r0, [pc, #76] @ (8001f34 <MX_GPIO_Init+0xa8>)
|
|
8001ee6: f000 fe23 bl 8002b30 <HAL_GPIO_WritePin>
|
|
|
|
/*Configure GPIO pins : Led_LCD_Pin D4_LCD_Pin D7_LCD_Pin E_LCD_Pin */
|
|
GPIO_InitStruct.Pin = Led_LCD_Pin|D4_LCD_Pin|D7_LCD_Pin|E_LCD_Pin;
|
|
8001eea: f248 031c movw r3, #32796 @ 0x801c
|
|
8001eee: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8001ef0: 2301 movs r3, #1
|
|
8001ef2: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001ef4: 2300 movs r3, #0
|
|
8001ef6: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8001ef8: 2300 movs r3, #0
|
|
8001efa: 61bb str r3, [r7, #24]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8001efc: f107 030c add.w r3, r7, #12
|
|
8001f00: 4619 mov r1, r3
|
|
8001f02: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
|
|
8001f06: f000 fc69 bl 80027dc <HAL_GPIO_Init>
|
|
|
|
/*Configure GPIO pins : D6_LCD_Pin RS_LCD_Pin D5_LCD_Pin */
|
|
GPIO_InitStruct.Pin = D6_LCD_Pin|RS_LCD_Pin|D5_LCD_Pin;
|
|
8001f0a: 2316 movs r3, #22
|
|
8001f0c: 60fb str r3, [r7, #12]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8001f0e: 2301 movs r3, #1
|
|
8001f10: 613b str r3, [r7, #16]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001f12: 2300 movs r3, #0
|
|
8001f14: 617b str r3, [r7, #20]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8001f16: 2300 movs r3, #0
|
|
8001f18: 61bb str r3, [r7, #24]
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8001f1a: f107 030c add.w r3, r7, #12
|
|
8001f1e: 4619 mov r1, r3
|
|
8001f20: 4804 ldr r0, [pc, #16] @ (8001f34 <MX_GPIO_Init+0xa8>)
|
|
8001f22: f000 fc5b bl 80027dc <HAL_GPIO_Init>
|
|
|
|
/* USER CODE BEGIN MX_GPIO_Init_2 */
|
|
/* USER CODE END MX_GPIO_Init_2 */
|
|
}
|
|
8001f26: bf00 nop
|
|
8001f28: 3720 adds r7, #32
|
|
8001f2a: 46bd mov sp, r7
|
|
8001f2c: bd80 pop {r7, pc}
|
|
8001f2e: bf00 nop
|
|
8001f30: 40021000 .word 0x40021000
|
|
8001f34: 48000400 .word 0x48000400
|
|
|
|
08001f38 <Error_Handler>:
|
|
/**
|
|
* @brief This function is executed in case of error occurrence.
|
|
* @retval None
|
|
*/
|
|
void Error_Handler(void)
|
|
{
|
|
8001f38: b480 push {r7}
|
|
8001f3a: af00 add r7, sp, #0
|
|
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
|
|
Can only be executed in Privileged modes.
|
|
*/
|
|
__STATIC_FORCEINLINE void __disable_irq(void)
|
|
{
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
8001f3c: b672 cpsid i
|
|
}
|
|
8001f3e: bf00 nop
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
|
/* User can add his own implementation to report the HAL error return state */
|
|
__disable_irq();
|
|
while (1)
|
|
8001f40: bf00 nop
|
|
8001f42: e7fd b.n 8001f40 <Error_Handler+0x8>
|
|
|
|
08001f44 <HAL_MspInit>:
|
|
/* USER CODE END 0 */
|
|
/**
|
|
* Initializes the Global MSP.
|
|
*/
|
|
void HAL_MspInit(void)
|
|
{
|
|
8001f44: b480 push {r7}
|
|
8001f46: b083 sub sp, #12
|
|
8001f48: af00 add r7, sp, #0
|
|
|
|
/* USER CODE BEGIN MspInit 0 */
|
|
|
|
/* USER CODE END MspInit 0 */
|
|
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
8001f4a: 4b0f ldr r3, [pc, #60] @ (8001f88 <HAL_MspInit+0x44>)
|
|
8001f4c: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8001f4e: 4a0e ldr r2, [pc, #56] @ (8001f88 <HAL_MspInit+0x44>)
|
|
8001f50: f043 0301 orr.w r3, r3, #1
|
|
8001f54: 6613 str r3, [r2, #96] @ 0x60
|
|
8001f56: 4b0c ldr r3, [pc, #48] @ (8001f88 <HAL_MspInit+0x44>)
|
|
8001f58: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8001f5a: f003 0301 and.w r3, r3, #1
|
|
8001f5e: 607b str r3, [r7, #4]
|
|
8001f60: 687b ldr r3, [r7, #4]
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8001f62: 4b09 ldr r3, [pc, #36] @ (8001f88 <HAL_MspInit+0x44>)
|
|
8001f64: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8001f66: 4a08 ldr r2, [pc, #32] @ (8001f88 <HAL_MspInit+0x44>)
|
|
8001f68: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8001f6c: 6593 str r3, [r2, #88] @ 0x58
|
|
8001f6e: 4b06 ldr r3, [pc, #24] @ (8001f88 <HAL_MspInit+0x44>)
|
|
8001f70: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8001f72: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8001f76: 603b str r3, [r7, #0]
|
|
8001f78: 683b ldr r3, [r7, #0]
|
|
/* System interrupt init*/
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
}
|
|
8001f7a: bf00 nop
|
|
8001f7c: 370c adds r7, #12
|
|
8001f7e: 46bd mov sp, r7
|
|
8001f80: f85d 7b04 ldr.w r7, [sp], #4
|
|
8001f84: 4770 bx lr
|
|
8001f86: bf00 nop
|
|
8001f88: 40021000 .word 0x40021000
|
|
|
|
08001f8c <HAL_I2C_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hi2c: I2C handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c)
|
|
{
|
|
8001f8c: b580 push {r7, lr}
|
|
8001f8e: b0ac sub sp, #176 @ 0xb0
|
|
8001f90: af00 add r7, sp, #0
|
|
8001f92: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8001f94: f107 039c add.w r3, r7, #156 @ 0x9c
|
|
8001f98: 2200 movs r2, #0
|
|
8001f9a: 601a str r2, [r3, #0]
|
|
8001f9c: 605a str r2, [r3, #4]
|
|
8001f9e: 609a str r2, [r3, #8]
|
|
8001fa0: 60da str r2, [r3, #12]
|
|
8001fa2: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
|
8001fa4: f107 0314 add.w r3, r7, #20
|
|
8001fa8: 2288 movs r2, #136 @ 0x88
|
|
8001faa: 2100 movs r1, #0
|
|
8001fac: 4618 mov r0, r3
|
|
8001fae: f005 f894 bl 80070da <memset>
|
|
if(hi2c->Instance==I2C2)
|
|
8001fb2: 687b ldr r3, [r7, #4]
|
|
8001fb4: 681b ldr r3, [r3, #0]
|
|
8001fb6: 4a21 ldr r2, [pc, #132] @ (800203c <HAL_I2C_MspInit+0xb0>)
|
|
8001fb8: 4293 cmp r3, r2
|
|
8001fba: d13b bne.n 8002034 <HAL_I2C_MspInit+0xa8>
|
|
|
|
/* USER CODE END I2C2_MspInit 0 */
|
|
|
|
/** Initializes the peripherals clock
|
|
*/
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C2;
|
|
8001fbc: 2380 movs r3, #128 @ 0x80
|
|
8001fbe: 617b str r3, [r7, #20]
|
|
PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_PCLK1;
|
|
8001fc0: 2300 movs r3, #0
|
|
8001fc2: 66bb str r3, [r7, #104] @ 0x68
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
8001fc4: f107 0314 add.w r3, r7, #20
|
|
8001fc8: 4618 mov r0, r3
|
|
8001fca: f002 fa51 bl 8004470 <HAL_RCCEx_PeriphCLKConfig>
|
|
8001fce: 4603 mov r3, r0
|
|
8001fd0: 2b00 cmp r3, #0
|
|
8001fd2: d001 beq.n 8001fd8 <HAL_I2C_MspInit+0x4c>
|
|
{
|
|
Error_Handler();
|
|
8001fd4: f7ff ffb0 bl 8001f38 <Error_Handler>
|
|
}
|
|
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8001fd8: 4b19 ldr r3, [pc, #100] @ (8002040 <HAL_I2C_MspInit+0xb4>)
|
|
8001fda: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8001fdc: 4a18 ldr r2, [pc, #96] @ (8002040 <HAL_I2C_MspInit+0xb4>)
|
|
8001fde: f043 0302 orr.w r3, r3, #2
|
|
8001fe2: 64d3 str r3, [r2, #76] @ 0x4c
|
|
8001fe4: 4b16 ldr r3, [pc, #88] @ (8002040 <HAL_I2C_MspInit+0xb4>)
|
|
8001fe6: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
8001fe8: f003 0302 and.w r3, r3, #2
|
|
8001fec: 613b str r3, [r7, #16]
|
|
8001fee: 693b ldr r3, [r7, #16]
|
|
/**I2C2 GPIO Configuration
|
|
PB10 ------> I2C2_SCL
|
|
PB11 ------> I2C2_SDA
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_10|GPIO_PIN_11;
|
|
8001ff0: f44f 6340 mov.w r3, #3072 @ 0xc00
|
|
8001ff4: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_OD;
|
|
8001ff8: 2312 movs r3, #18
|
|
8001ffa: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001ffe: 2300 movs r3, #0
|
|
8002000: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
8002004: 2303 movs r3, #3
|
|
8002006: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
GPIO_InitStruct.Alternate = GPIO_AF4_I2C2;
|
|
800200a: 2304 movs r3, #4
|
|
800200c: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8002010: f107 039c add.w r3, r7, #156 @ 0x9c
|
|
8002014: 4619 mov r1, r3
|
|
8002016: 480b ldr r0, [pc, #44] @ (8002044 <HAL_I2C_MspInit+0xb8>)
|
|
8002018: f000 fbe0 bl 80027dc <HAL_GPIO_Init>
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_I2C2_CLK_ENABLE();
|
|
800201c: 4b08 ldr r3, [pc, #32] @ (8002040 <HAL_I2C_MspInit+0xb4>)
|
|
800201e: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8002020: 4a07 ldr r2, [pc, #28] @ (8002040 <HAL_I2C_MspInit+0xb4>)
|
|
8002022: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
|
|
8002026: 6593 str r3, [r2, #88] @ 0x58
|
|
8002028: 4b05 ldr r3, [pc, #20] @ (8002040 <HAL_I2C_MspInit+0xb4>)
|
|
800202a: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800202c: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
8002030: 60fb str r3, [r7, #12]
|
|
8002032: 68fb ldr r3, [r7, #12]
|
|
|
|
/* USER CODE END I2C2_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
8002034: bf00 nop
|
|
8002036: 37b0 adds r7, #176 @ 0xb0
|
|
8002038: 46bd mov sp, r7
|
|
800203a: bd80 pop {r7, pc}
|
|
800203c: 40005800 .word 0x40005800
|
|
8002040: 40021000 .word 0x40021000
|
|
8002044: 48000400 .word 0x48000400
|
|
|
|
08002048 <HAL_UART_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param huart: UART handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
|
|
{
|
|
8002048: b580 push {r7, lr}
|
|
800204a: b0ac sub sp, #176 @ 0xb0
|
|
800204c: af00 add r7, sp, #0
|
|
800204e: 6078 str r0, [r7, #4]
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8002050: f107 039c add.w r3, r7, #156 @ 0x9c
|
|
8002054: 2200 movs r2, #0
|
|
8002056: 601a str r2, [r3, #0]
|
|
8002058: 605a str r2, [r3, #4]
|
|
800205a: 609a str r2, [r3, #8]
|
|
800205c: 60da str r2, [r3, #12]
|
|
800205e: 611a str r2, [r3, #16]
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
|
8002060: f107 0314 add.w r3, r7, #20
|
|
8002064: 2288 movs r2, #136 @ 0x88
|
|
8002066: 2100 movs r1, #0
|
|
8002068: 4618 mov r0, r3
|
|
800206a: f005 f836 bl 80070da <memset>
|
|
if(huart->Instance==USART1)
|
|
800206e: 687b ldr r3, [r7, #4]
|
|
8002070: 681b ldr r3, [r3, #0]
|
|
8002072: 4a25 ldr r2, [pc, #148] @ (8002108 <HAL_UART_MspInit+0xc0>)
|
|
8002074: 4293 cmp r3, r2
|
|
8002076: d142 bne.n 80020fe <HAL_UART_MspInit+0xb6>
|
|
|
|
/* USER CODE END USART1_MspInit 0 */
|
|
|
|
/** Initializes the peripherals clock
|
|
*/
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
|
|
8002078: 2301 movs r3, #1
|
|
800207a: 617b str r3, [r7, #20]
|
|
PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
|
|
800207c: 2300 movs r3, #0
|
|
800207e: 64fb str r3, [r7, #76] @ 0x4c
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
8002080: f107 0314 add.w r3, r7, #20
|
|
8002084: 4618 mov r0, r3
|
|
8002086: f002 f9f3 bl 8004470 <HAL_RCCEx_PeriphCLKConfig>
|
|
800208a: 4603 mov r3, r0
|
|
800208c: 2b00 cmp r3, #0
|
|
800208e: d001 beq.n 8002094 <HAL_UART_MspInit+0x4c>
|
|
{
|
|
Error_Handler();
|
|
8002090: f7ff ff52 bl 8001f38 <Error_Handler>
|
|
}
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_USART1_CLK_ENABLE();
|
|
8002094: 4b1d ldr r3, [pc, #116] @ (800210c <HAL_UART_MspInit+0xc4>)
|
|
8002096: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8002098: 4a1c ldr r2, [pc, #112] @ (800210c <HAL_UART_MspInit+0xc4>)
|
|
800209a: f443 4380 orr.w r3, r3, #16384 @ 0x4000
|
|
800209e: 6613 str r3, [r2, #96] @ 0x60
|
|
80020a0: 4b1a ldr r3, [pc, #104] @ (800210c <HAL_UART_MspInit+0xc4>)
|
|
80020a2: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
80020a4: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
80020a8: 613b str r3, [r7, #16]
|
|
80020aa: 693b ldr r3, [r7, #16]
|
|
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
80020ac: 4b17 ldr r3, [pc, #92] @ (800210c <HAL_UART_MspInit+0xc4>)
|
|
80020ae: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80020b0: 4a16 ldr r2, [pc, #88] @ (800210c <HAL_UART_MspInit+0xc4>)
|
|
80020b2: f043 0302 orr.w r3, r3, #2
|
|
80020b6: 64d3 str r3, [r2, #76] @ 0x4c
|
|
80020b8: 4b14 ldr r3, [pc, #80] @ (800210c <HAL_UART_MspInit+0xc4>)
|
|
80020ba: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80020bc: f003 0302 and.w r3, r3, #2
|
|
80020c0: 60fb str r3, [r7, #12]
|
|
80020c2: 68fb ldr r3, [r7, #12]
|
|
/**USART1 GPIO Configuration
|
|
PB6 ------> USART1_TX
|
|
PB7 ------> USART1_RX
|
|
*/
|
|
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
|
|
80020c4: 23c0 movs r3, #192 @ 0xc0
|
|
80020c6: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80020ca: 2302 movs r3, #2
|
|
80020cc: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80020d0: 2300 movs r3, #0
|
|
80020d2: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
|
|
80020d6: 2303 movs r3, #3
|
|
80020d8: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
|
|
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
|
|
80020dc: 2307 movs r3, #7
|
|
80020de: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
80020e2: f107 039c add.w r3, r7, #156 @ 0x9c
|
|
80020e6: 4619 mov r1, r3
|
|
80020e8: 4809 ldr r0, [pc, #36] @ (8002110 <HAL_UART_MspInit+0xc8>)
|
|
80020ea: f000 fb77 bl 80027dc <HAL_GPIO_Init>
|
|
|
|
/* USART1 interrupt Init */
|
|
HAL_NVIC_SetPriority(USART1_IRQn, 0, 0);
|
|
80020ee: 2200 movs r2, #0
|
|
80020f0: 2100 movs r1, #0
|
|
80020f2: 2025 movs r0, #37 @ 0x25
|
|
80020f4: f000 fabd bl 8002672 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(USART1_IRQn);
|
|
80020f8: 2025 movs r0, #37 @ 0x25
|
|
80020fa: f000 fad6 bl 80026aa <HAL_NVIC_EnableIRQ>
|
|
|
|
/* USER CODE END USART1_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
80020fe: bf00 nop
|
|
8002100: 37b0 adds r7, #176 @ 0xb0
|
|
8002102: 46bd mov sp, r7
|
|
8002104: bd80 pop {r7, pc}
|
|
8002106: bf00 nop
|
|
8002108: 40013800 .word 0x40013800
|
|
800210c: 40021000 .word 0x40021000
|
|
8002110: 48000400 .word 0x48000400
|
|
|
|
08002114 <NMI_Handler>:
|
|
/******************************************************************************/
|
|
/**
|
|
* @brief This function handles Non maskable interrupt.
|
|
*/
|
|
void NMI_Handler(void)
|
|
{
|
|
8002114: b480 push {r7}
|
|
8002116: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
while (1)
|
|
8002118: bf00 nop
|
|
800211a: e7fd b.n 8002118 <NMI_Handler+0x4>
|
|
|
|
0800211c <HardFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Hard fault interrupt.
|
|
*/
|
|
void HardFault_Handler(void)
|
|
{
|
|
800211c: b480 push {r7}
|
|
800211e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
8002120: bf00 nop
|
|
8002122: e7fd b.n 8002120 <HardFault_Handler+0x4>
|
|
|
|
08002124 <MemManage_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Memory management fault.
|
|
*/
|
|
void MemManage_Handler(void)
|
|
{
|
|
8002124: b480 push {r7}
|
|
8002126: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
|
|
|
|
/* USER CODE END MemoryManagement_IRQn 0 */
|
|
while (1)
|
|
8002128: bf00 nop
|
|
800212a: e7fd b.n 8002128 <MemManage_Handler+0x4>
|
|
|
|
0800212c <BusFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Prefetch fault, memory access fault.
|
|
*/
|
|
void BusFault_Handler(void)
|
|
{
|
|
800212c: b480 push {r7}
|
|
800212e: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN BusFault_IRQn 0 */
|
|
|
|
/* USER CODE END BusFault_IRQn 0 */
|
|
while (1)
|
|
8002130: bf00 nop
|
|
8002132: e7fd b.n 8002130 <BusFault_Handler+0x4>
|
|
|
|
08002134 <UsageFault_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Undefined instruction or illegal state.
|
|
*/
|
|
void UsageFault_Handler(void)
|
|
{
|
|
8002134: b480 push {r7}
|
|
8002136: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN UsageFault_IRQn 0 */
|
|
|
|
/* USER CODE END UsageFault_IRQn 0 */
|
|
while (1)
|
|
8002138: bf00 nop
|
|
800213a: e7fd b.n 8002138 <UsageFault_Handler+0x4>
|
|
|
|
0800213c <SVC_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System service call via SWI instruction.
|
|
*/
|
|
void SVC_Handler(void)
|
|
{
|
|
800213c: b480 push {r7}
|
|
800213e: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END SVCall_IRQn 0 */
|
|
/* USER CODE BEGIN SVCall_IRQn 1 */
|
|
|
|
/* USER CODE END SVCall_IRQn 1 */
|
|
}
|
|
8002140: bf00 nop
|
|
8002142: 46bd mov sp, r7
|
|
8002144: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002148: 4770 bx lr
|
|
|
|
0800214a <DebugMon_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Debug monitor.
|
|
*/
|
|
void DebugMon_Handler(void)
|
|
{
|
|
800214a: b480 push {r7}
|
|
800214c: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 0 */
|
|
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
|
|
|
|
/* USER CODE END DebugMonitor_IRQn 1 */
|
|
}
|
|
800214e: bf00 nop
|
|
8002150: 46bd mov sp, r7
|
|
8002152: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002156: 4770 bx lr
|
|
|
|
08002158 <PendSV_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pendable request for system service.
|
|
*/
|
|
void PendSV_Handler(void)
|
|
{
|
|
8002158: b480 push {r7}
|
|
800215a: af00 add r7, sp, #0
|
|
|
|
/* USER CODE END PendSV_IRQn 0 */
|
|
/* USER CODE BEGIN PendSV_IRQn 1 */
|
|
|
|
/* USER CODE END PendSV_IRQn 1 */
|
|
}
|
|
800215c: bf00 nop
|
|
800215e: 46bd mov sp, r7
|
|
8002160: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002164: 4770 bx lr
|
|
|
|
08002166 <SysTick_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System tick timer.
|
|
*/
|
|
void SysTick_Handler(void)
|
|
{
|
|
8002166: b580 push {r7, lr}
|
|
8002168: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN SysTick_IRQn 0 */
|
|
|
|
/* USER CODE END SysTick_IRQn 0 */
|
|
HAL_IncTick();
|
|
800216a: f000 f963 bl 8002434 <HAL_IncTick>
|
|
/* USER CODE BEGIN SysTick_IRQn 1 */
|
|
|
|
/* USER CODE END SysTick_IRQn 1 */
|
|
}
|
|
800216e: bf00 nop
|
|
8002170: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08002174 <USART1_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles USART1 global interrupt.
|
|
*/
|
|
void USART1_IRQHandler(void)
|
|
{
|
|
8002174: b580 push {r7, lr}
|
|
8002176: af00 add r7, sp, #0
|
|
/* USER CODE BEGIN USART1_IRQn 0 */
|
|
|
|
/* USER CODE END USART1_IRQn 0 */
|
|
HAL_UART_IRQHandler(&huart1);
|
|
8002178: 4802 ldr r0, [pc, #8] @ (8002184 <USART1_IRQHandler+0x10>)
|
|
800217a: f002 ff59 bl 8005030 <HAL_UART_IRQHandler>
|
|
/* USER CODE BEGIN USART1_IRQn 1 */
|
|
|
|
/* USER CODE END USART1_IRQn 1 */
|
|
}
|
|
800217e: bf00 nop
|
|
8002180: bd80 pop {r7, pc}
|
|
8002182: bf00 nop
|
|
8002184: 2000028c .word 0x2000028c
|
|
|
|
08002188 <_getpid>:
|
|
void initialise_monitor_handles()
|
|
{
|
|
}
|
|
|
|
int _getpid(void)
|
|
{
|
|
8002188: b480 push {r7}
|
|
800218a: af00 add r7, sp, #0
|
|
return 1;
|
|
800218c: 2301 movs r3, #1
|
|
}
|
|
800218e: 4618 mov r0, r3
|
|
8002190: 46bd mov sp, r7
|
|
8002192: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002196: 4770 bx lr
|
|
|
|
08002198 <_kill>:
|
|
|
|
int _kill(int pid, int sig)
|
|
{
|
|
8002198: b580 push {r7, lr}
|
|
800219a: b082 sub sp, #8
|
|
800219c: af00 add r7, sp, #0
|
|
800219e: 6078 str r0, [r7, #4]
|
|
80021a0: 6039 str r1, [r7, #0]
|
|
(void)pid;
|
|
(void)sig;
|
|
errno = EINVAL;
|
|
80021a2: f004 ffed bl 8007180 <__errno>
|
|
80021a6: 4603 mov r3, r0
|
|
80021a8: 2216 movs r2, #22
|
|
80021aa: 601a str r2, [r3, #0]
|
|
return -1;
|
|
80021ac: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
}
|
|
80021b0: 4618 mov r0, r3
|
|
80021b2: 3708 adds r7, #8
|
|
80021b4: 46bd mov sp, r7
|
|
80021b6: bd80 pop {r7, pc}
|
|
|
|
080021b8 <_exit>:
|
|
|
|
void _exit (int status)
|
|
{
|
|
80021b8: b580 push {r7, lr}
|
|
80021ba: b082 sub sp, #8
|
|
80021bc: af00 add r7, sp, #0
|
|
80021be: 6078 str r0, [r7, #4]
|
|
_kill(status, -1);
|
|
80021c0: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
|
|
80021c4: 6878 ldr r0, [r7, #4]
|
|
80021c6: f7ff ffe7 bl 8002198 <_kill>
|
|
while (1) {} /* Make sure we hang here */
|
|
80021ca: bf00 nop
|
|
80021cc: e7fd b.n 80021ca <_exit+0x12>
|
|
|
|
080021ce <_read>:
|
|
}
|
|
|
|
__attribute__((weak)) int _read(int file, char *ptr, int len)
|
|
{
|
|
80021ce: b580 push {r7, lr}
|
|
80021d0: b086 sub sp, #24
|
|
80021d2: af00 add r7, sp, #0
|
|
80021d4: 60f8 str r0, [r7, #12]
|
|
80021d6: 60b9 str r1, [r7, #8]
|
|
80021d8: 607a str r2, [r7, #4]
|
|
(void)file;
|
|
int DataIdx;
|
|
|
|
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
|
80021da: 2300 movs r3, #0
|
|
80021dc: 617b str r3, [r7, #20]
|
|
80021de: e00a b.n 80021f6 <_read+0x28>
|
|
{
|
|
*ptr++ = __io_getchar();
|
|
80021e0: f3af 8000 nop.w
|
|
80021e4: 4601 mov r1, r0
|
|
80021e6: 68bb ldr r3, [r7, #8]
|
|
80021e8: 1c5a adds r2, r3, #1
|
|
80021ea: 60ba str r2, [r7, #8]
|
|
80021ec: b2ca uxtb r2, r1
|
|
80021ee: 701a strb r2, [r3, #0]
|
|
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
|
80021f0: 697b ldr r3, [r7, #20]
|
|
80021f2: 3301 adds r3, #1
|
|
80021f4: 617b str r3, [r7, #20]
|
|
80021f6: 697a ldr r2, [r7, #20]
|
|
80021f8: 687b ldr r3, [r7, #4]
|
|
80021fa: 429a cmp r2, r3
|
|
80021fc: dbf0 blt.n 80021e0 <_read+0x12>
|
|
}
|
|
|
|
return len;
|
|
80021fe: 687b ldr r3, [r7, #4]
|
|
}
|
|
8002200: 4618 mov r0, r3
|
|
8002202: 3718 adds r7, #24
|
|
8002204: 46bd mov sp, r7
|
|
8002206: bd80 pop {r7, pc}
|
|
|
|
08002208 <_write>:
|
|
|
|
__attribute__((weak)) int _write(int file, char *ptr, int len)
|
|
{
|
|
8002208: b580 push {r7, lr}
|
|
800220a: b086 sub sp, #24
|
|
800220c: af00 add r7, sp, #0
|
|
800220e: 60f8 str r0, [r7, #12]
|
|
8002210: 60b9 str r1, [r7, #8]
|
|
8002212: 607a str r2, [r7, #4]
|
|
(void)file;
|
|
int DataIdx;
|
|
|
|
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
|
8002214: 2300 movs r3, #0
|
|
8002216: 617b str r3, [r7, #20]
|
|
8002218: e009 b.n 800222e <_write+0x26>
|
|
{
|
|
__io_putchar(*ptr++);
|
|
800221a: 68bb ldr r3, [r7, #8]
|
|
800221c: 1c5a adds r2, r3, #1
|
|
800221e: 60ba str r2, [r7, #8]
|
|
8002220: 781b ldrb r3, [r3, #0]
|
|
8002222: 4618 mov r0, r3
|
|
8002224: f7ff fb22 bl 800186c <__io_putchar>
|
|
for (DataIdx = 0; DataIdx < len; DataIdx++)
|
|
8002228: 697b ldr r3, [r7, #20]
|
|
800222a: 3301 adds r3, #1
|
|
800222c: 617b str r3, [r7, #20]
|
|
800222e: 697a ldr r2, [r7, #20]
|
|
8002230: 687b ldr r3, [r7, #4]
|
|
8002232: 429a cmp r2, r3
|
|
8002234: dbf1 blt.n 800221a <_write+0x12>
|
|
}
|
|
return len;
|
|
8002236: 687b ldr r3, [r7, #4]
|
|
}
|
|
8002238: 4618 mov r0, r3
|
|
800223a: 3718 adds r7, #24
|
|
800223c: 46bd mov sp, r7
|
|
800223e: bd80 pop {r7, pc}
|
|
|
|
08002240 <_close>:
|
|
|
|
int _close(int file)
|
|
{
|
|
8002240: b480 push {r7}
|
|
8002242: b083 sub sp, #12
|
|
8002244: af00 add r7, sp, #0
|
|
8002246: 6078 str r0, [r7, #4]
|
|
(void)file;
|
|
return -1;
|
|
8002248: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
}
|
|
800224c: 4618 mov r0, r3
|
|
800224e: 370c adds r7, #12
|
|
8002250: 46bd mov sp, r7
|
|
8002252: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002256: 4770 bx lr
|
|
|
|
08002258 <_fstat>:
|
|
|
|
|
|
int _fstat(int file, struct stat *st)
|
|
{
|
|
8002258: b480 push {r7}
|
|
800225a: b083 sub sp, #12
|
|
800225c: af00 add r7, sp, #0
|
|
800225e: 6078 str r0, [r7, #4]
|
|
8002260: 6039 str r1, [r7, #0]
|
|
(void)file;
|
|
st->st_mode = S_IFCHR;
|
|
8002262: 683b ldr r3, [r7, #0]
|
|
8002264: f44f 5200 mov.w r2, #8192 @ 0x2000
|
|
8002268: 605a str r2, [r3, #4]
|
|
return 0;
|
|
800226a: 2300 movs r3, #0
|
|
}
|
|
800226c: 4618 mov r0, r3
|
|
800226e: 370c adds r7, #12
|
|
8002270: 46bd mov sp, r7
|
|
8002272: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002276: 4770 bx lr
|
|
|
|
08002278 <_isatty>:
|
|
|
|
int _isatty(int file)
|
|
{
|
|
8002278: b480 push {r7}
|
|
800227a: b083 sub sp, #12
|
|
800227c: af00 add r7, sp, #0
|
|
800227e: 6078 str r0, [r7, #4]
|
|
(void)file;
|
|
return 1;
|
|
8002280: 2301 movs r3, #1
|
|
}
|
|
8002282: 4618 mov r0, r3
|
|
8002284: 370c adds r7, #12
|
|
8002286: 46bd mov sp, r7
|
|
8002288: f85d 7b04 ldr.w r7, [sp], #4
|
|
800228c: 4770 bx lr
|
|
|
|
0800228e <_lseek>:
|
|
|
|
int _lseek(int file, int ptr, int dir)
|
|
{
|
|
800228e: b480 push {r7}
|
|
8002290: b085 sub sp, #20
|
|
8002292: af00 add r7, sp, #0
|
|
8002294: 60f8 str r0, [r7, #12]
|
|
8002296: 60b9 str r1, [r7, #8]
|
|
8002298: 607a str r2, [r7, #4]
|
|
(void)file;
|
|
(void)ptr;
|
|
(void)dir;
|
|
return 0;
|
|
800229a: 2300 movs r3, #0
|
|
}
|
|
800229c: 4618 mov r0, r3
|
|
800229e: 3714 adds r7, #20
|
|
80022a0: 46bd mov sp, r7
|
|
80022a2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80022a6: 4770 bx lr
|
|
|
|
080022a8 <_sbrk>:
|
|
*
|
|
* @param incr Memory size
|
|
* @return Pointer to allocated memory
|
|
*/
|
|
void *_sbrk(ptrdiff_t incr)
|
|
{
|
|
80022a8: b580 push {r7, lr}
|
|
80022aa: b086 sub sp, #24
|
|
80022ac: af00 add r7, sp, #0
|
|
80022ae: 6078 str r0, [r7, #4]
|
|
extern uint8_t _end; /* Symbol defined in the linker script */
|
|
extern uint8_t _estack; /* Symbol defined in the linker script */
|
|
extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */
|
|
const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size;
|
|
80022b0: 4a14 ldr r2, [pc, #80] @ (8002304 <_sbrk+0x5c>)
|
|
80022b2: 4b15 ldr r3, [pc, #84] @ (8002308 <_sbrk+0x60>)
|
|
80022b4: 1ad3 subs r3, r2, r3
|
|
80022b6: 617b str r3, [r7, #20]
|
|
const uint8_t *max_heap = (uint8_t *)stack_limit;
|
|
80022b8: 697b ldr r3, [r7, #20]
|
|
80022ba: 613b str r3, [r7, #16]
|
|
uint8_t *prev_heap_end;
|
|
|
|
/* Initialize heap end at first call */
|
|
if (NULL == __sbrk_heap_end)
|
|
80022bc: 4b13 ldr r3, [pc, #76] @ (800230c <_sbrk+0x64>)
|
|
80022be: 681b ldr r3, [r3, #0]
|
|
80022c0: 2b00 cmp r3, #0
|
|
80022c2: d102 bne.n 80022ca <_sbrk+0x22>
|
|
{
|
|
__sbrk_heap_end = &_end;
|
|
80022c4: 4b11 ldr r3, [pc, #68] @ (800230c <_sbrk+0x64>)
|
|
80022c6: 4a12 ldr r2, [pc, #72] @ (8002310 <_sbrk+0x68>)
|
|
80022c8: 601a str r2, [r3, #0]
|
|
}
|
|
|
|
/* Protect heap from growing into the reserved MSP stack */
|
|
if (__sbrk_heap_end + incr > max_heap)
|
|
80022ca: 4b10 ldr r3, [pc, #64] @ (800230c <_sbrk+0x64>)
|
|
80022cc: 681a ldr r2, [r3, #0]
|
|
80022ce: 687b ldr r3, [r7, #4]
|
|
80022d0: 4413 add r3, r2
|
|
80022d2: 693a ldr r2, [r7, #16]
|
|
80022d4: 429a cmp r2, r3
|
|
80022d6: d207 bcs.n 80022e8 <_sbrk+0x40>
|
|
{
|
|
errno = ENOMEM;
|
|
80022d8: f004 ff52 bl 8007180 <__errno>
|
|
80022dc: 4603 mov r3, r0
|
|
80022de: 220c movs r2, #12
|
|
80022e0: 601a str r2, [r3, #0]
|
|
return (void *)-1;
|
|
80022e2: f04f 33ff mov.w r3, #4294967295 @ 0xffffffff
|
|
80022e6: e009 b.n 80022fc <_sbrk+0x54>
|
|
}
|
|
|
|
prev_heap_end = __sbrk_heap_end;
|
|
80022e8: 4b08 ldr r3, [pc, #32] @ (800230c <_sbrk+0x64>)
|
|
80022ea: 681b ldr r3, [r3, #0]
|
|
80022ec: 60fb str r3, [r7, #12]
|
|
__sbrk_heap_end += incr;
|
|
80022ee: 4b07 ldr r3, [pc, #28] @ (800230c <_sbrk+0x64>)
|
|
80022f0: 681a ldr r2, [r3, #0]
|
|
80022f2: 687b ldr r3, [r7, #4]
|
|
80022f4: 4413 add r3, r2
|
|
80022f6: 4a05 ldr r2, [pc, #20] @ (800230c <_sbrk+0x64>)
|
|
80022f8: 6013 str r3, [r2, #0]
|
|
|
|
return (void *)prev_heap_end;
|
|
80022fa: 68fb ldr r3, [r7, #12]
|
|
}
|
|
80022fc: 4618 mov r0, r3
|
|
80022fe: 3718 adds r7, #24
|
|
8002300: 46bd mov sp, r7
|
|
8002302: bd80 pop {r7, pc}
|
|
8002304: 20018000 .word 0x20018000
|
|
8002308: 00000400 .word 0x00000400
|
|
800230c: 20000324 .word 0x20000324
|
|
8002310: 20000478 .word 0x20000478
|
|
|
|
08002314 <SystemInit>:
|
|
* @brief Setup the microcontroller system.
|
|
* @retval None
|
|
*/
|
|
|
|
void SystemInit(void)
|
|
{
|
|
8002314: b480 push {r7}
|
|
8002316: af00 add r7, sp, #0
|
|
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
|
|
#endif
|
|
|
|
/* FPU settings ------------------------------------------------------------*/
|
|
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
|
|
SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
|
|
8002318: 4b06 ldr r3, [pc, #24] @ (8002334 <SystemInit+0x20>)
|
|
800231a: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
800231e: 4a05 ldr r2, [pc, #20] @ (8002334 <SystemInit+0x20>)
|
|
8002320: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
|
|
8002324: f8c2 3088 str.w r3, [r2, #136] @ 0x88
|
|
#endif
|
|
}
|
|
8002328: bf00 nop
|
|
800232a: 46bd mov sp, r7
|
|
800232c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002330: 4770 bx lr
|
|
8002332: bf00 nop
|
|
8002334: e000ed00 .word 0xe000ed00
|
|
|
|
08002338 <Reset_Handler>:
|
|
|
|
.section .text.Reset_Handler
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
ldr sp, =_estack /* Set stack pointer */
|
|
8002338: f8df d034 ldr.w sp, [pc, #52] @ 8002370 <LoopForever+0x2>
|
|
|
|
/* Call the clock system initialization function.*/
|
|
bl SystemInit
|
|
800233c: f7ff ffea bl 8002314 <SystemInit>
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
ldr r0, =_sdata
|
|
8002340: 480c ldr r0, [pc, #48] @ (8002374 <LoopForever+0x6>)
|
|
ldr r1, =_edata
|
|
8002342: 490d ldr r1, [pc, #52] @ (8002378 <LoopForever+0xa>)
|
|
ldr r2, =_sidata
|
|
8002344: 4a0d ldr r2, [pc, #52] @ (800237c <LoopForever+0xe>)
|
|
movs r3, #0
|
|
8002346: 2300 movs r3, #0
|
|
b LoopCopyDataInit
|
|
8002348: e002 b.n 8002350 <LoopCopyDataInit>
|
|
|
|
0800234a <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r4, [r2, r3]
|
|
800234a: 58d4 ldr r4, [r2, r3]
|
|
str r4, [r0, r3]
|
|
800234c: 50c4 str r4, [r0, r3]
|
|
adds r3, r3, #4
|
|
800234e: 3304 adds r3, #4
|
|
|
|
08002350 <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
adds r4, r0, r3
|
|
8002350: 18c4 adds r4, r0, r3
|
|
cmp r4, r1
|
|
8002352: 428c cmp r4, r1
|
|
bcc CopyDataInit
|
|
8002354: d3f9 bcc.n 800234a <CopyDataInit>
|
|
|
|
/* Zero fill the bss segment. */
|
|
ldr r2, =_sbss
|
|
8002356: 4a0a ldr r2, [pc, #40] @ (8002380 <LoopForever+0x12>)
|
|
ldr r4, =_ebss
|
|
8002358: 4c0a ldr r4, [pc, #40] @ (8002384 <LoopForever+0x16>)
|
|
movs r3, #0
|
|
800235a: 2300 movs r3, #0
|
|
b LoopFillZerobss
|
|
800235c: e001 b.n 8002362 <LoopFillZerobss>
|
|
|
|
0800235e <FillZerobss>:
|
|
|
|
FillZerobss:
|
|
str r3, [r2]
|
|
800235e: 6013 str r3, [r2, #0]
|
|
adds r2, r2, #4
|
|
8002360: 3204 adds r2, #4
|
|
|
|
08002362 <LoopFillZerobss>:
|
|
|
|
LoopFillZerobss:
|
|
cmp r2, r4
|
|
8002362: 42a2 cmp r2, r4
|
|
bcc FillZerobss
|
|
8002364: d3fb bcc.n 800235e <FillZerobss>
|
|
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
8002366: f004 ff11 bl 800718c <__libc_init_array>
|
|
/* Call the application's entry point.*/
|
|
bl main
|
|
800236a: f7ff faf5 bl 8001958 <main>
|
|
|
|
0800236e <LoopForever>:
|
|
|
|
LoopForever:
|
|
b LoopForever
|
|
800236e: e7fe b.n 800236e <LoopForever>
|
|
ldr sp, =_estack /* Set stack pointer */
|
|
8002370: 20018000 .word 0x20018000
|
|
ldr r0, =_sdata
|
|
8002374: 20000000 .word 0x20000000
|
|
ldr r1, =_edata
|
|
8002378: 200001e8 .word 0x200001e8
|
|
ldr r2, =_sidata
|
|
800237c: 080096c4 .word 0x080096c4
|
|
ldr r2, =_sbss
|
|
8002380: 200001e8 .word 0x200001e8
|
|
ldr r4, =_ebss
|
|
8002384: 20000478 .word 0x20000478
|
|
|
|
08002388 <ADC1_2_IRQHandler>:
|
|
* @retval : None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
8002388: e7fe b.n 8002388 <ADC1_2_IRQHandler>
|
|
|
|
0800238a <HAL_Init>:
|
|
* each 1ms in the SysTick_Handler() interrupt handler.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_Init(void)
|
|
{
|
|
800238a: b580 push {r7, lr}
|
|
800238c: b082 sub sp, #8
|
|
800238e: af00 add r7, sp, #0
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8002390: 2300 movs r3, #0
|
|
8002392: 71fb strb r3, [r7, #7]
|
|
#if (PREFETCH_ENABLE != 0)
|
|
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
|
|
#endif /* PREFETCH_ENABLE */
|
|
|
|
/* Set Interrupt Group Priority */
|
|
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
|
|
8002394: 2003 movs r0, #3
|
|
8002396: f000 f961 bl 800265c <HAL_NVIC_SetPriorityGrouping>
|
|
|
|
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */
|
|
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
|
|
800239a: 200f movs r0, #15
|
|
800239c: f000 f80e bl 80023bc <HAL_InitTick>
|
|
80023a0: 4603 mov r3, r0
|
|
80023a2: 2b00 cmp r3, #0
|
|
80023a4: d002 beq.n 80023ac <HAL_Init+0x22>
|
|
{
|
|
status = HAL_ERROR;
|
|
80023a6: 2301 movs r3, #1
|
|
80023a8: 71fb strb r3, [r7, #7]
|
|
80023aa: e001 b.n 80023b0 <HAL_Init+0x26>
|
|
}
|
|
else
|
|
{
|
|
/* Init the low level hardware */
|
|
HAL_MspInit();
|
|
80023ac: f7ff fdca bl 8001f44 <HAL_MspInit>
|
|
}
|
|
|
|
/* Return function status */
|
|
return status;
|
|
80023b0: 79fb ldrb r3, [r7, #7]
|
|
}
|
|
80023b2: 4618 mov r0, r3
|
|
80023b4: 3708 adds r7, #8
|
|
80023b6: 46bd mov sp, r7
|
|
80023b8: bd80 pop {r7, pc}
|
|
...
|
|
|
|
080023bc <HAL_InitTick>:
|
|
* implementation in user file.
|
|
* @param TickPriority Tick interrupt priority.
|
|
* @retval HAL status
|
|
*/
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
80023bc: b580 push {r7, lr}
|
|
80023be: b084 sub sp, #16
|
|
80023c0: af00 add r7, sp, #0
|
|
80023c2: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80023c4: 2300 movs r3, #0
|
|
80023c6: 73fb strb r3, [r7, #15]
|
|
|
|
/* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that doesn't take the value zero)*/
|
|
if ((uint32_t)uwTickFreq != 0U)
|
|
80023c8: 4b17 ldr r3, [pc, #92] @ (8002428 <HAL_InitTick+0x6c>)
|
|
80023ca: 781b ldrb r3, [r3, #0]
|
|
80023cc: 2b00 cmp r3, #0
|
|
80023ce: d023 beq.n 8002418 <HAL_InitTick+0x5c>
|
|
{
|
|
/*Configure the SysTick to have interrupt in 1ms time basis*/
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / (uint32_t)uwTickFreq)) == 0U)
|
|
80023d0: 4b16 ldr r3, [pc, #88] @ (800242c <HAL_InitTick+0x70>)
|
|
80023d2: 681a ldr r2, [r3, #0]
|
|
80023d4: 4b14 ldr r3, [pc, #80] @ (8002428 <HAL_InitTick+0x6c>)
|
|
80023d6: 781b ldrb r3, [r3, #0]
|
|
80023d8: 4619 mov r1, r3
|
|
80023da: f44f 737a mov.w r3, #1000 @ 0x3e8
|
|
80023de: fbb3 f3f1 udiv r3, r3, r1
|
|
80023e2: fbb2 f3f3 udiv r3, r2, r3
|
|
80023e6: 4618 mov r0, r3
|
|
80023e8: f000 f96d bl 80026c6 <HAL_SYSTICK_Config>
|
|
80023ec: 4603 mov r3, r0
|
|
80023ee: 2b00 cmp r3, #0
|
|
80023f0: d10f bne.n 8002412 <HAL_InitTick+0x56>
|
|
{
|
|
/* Configure the SysTick IRQ priority */
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
80023f2: 687b ldr r3, [r7, #4]
|
|
80023f4: 2b0f cmp r3, #15
|
|
80023f6: d809 bhi.n 800240c <HAL_InitTick+0x50>
|
|
{
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
|
80023f8: 2200 movs r2, #0
|
|
80023fa: 6879 ldr r1, [r7, #4]
|
|
80023fc: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8002400: f000 f937 bl 8002672 <HAL_NVIC_SetPriority>
|
|
uwTickPrio = TickPriority;
|
|
8002404: 4a0a ldr r2, [pc, #40] @ (8002430 <HAL_InitTick+0x74>)
|
|
8002406: 687b ldr r3, [r7, #4]
|
|
8002408: 6013 str r3, [r2, #0]
|
|
800240a: e007 b.n 800241c <HAL_InitTick+0x60>
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
800240c: 2301 movs r3, #1
|
|
800240e: 73fb strb r3, [r7, #15]
|
|
8002410: e004 b.n 800241c <HAL_InitTick+0x60>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
8002412: 2301 movs r3, #1
|
|
8002414: 73fb strb r3, [r7, #15]
|
|
8002416: e001 b.n 800241c <HAL_InitTick+0x60>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
8002418: 2301 movs r3, #1
|
|
800241a: 73fb strb r3, [r7, #15]
|
|
}
|
|
|
|
/* Return function status */
|
|
return status;
|
|
800241c: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
800241e: 4618 mov r0, r3
|
|
8002420: 3710 adds r7, #16
|
|
8002422: 46bd mov sp, r7
|
|
8002424: bd80 pop {r7, pc}
|
|
8002426: bf00 nop
|
|
8002428: 2000001c .word 0x2000001c
|
|
800242c: 20000014 .word 0x20000014
|
|
8002430: 20000018 .word 0x20000018
|
|
|
|
08002434 <HAL_IncTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_IncTick(void)
|
|
{
|
|
8002434: b480 push {r7}
|
|
8002436: af00 add r7, sp, #0
|
|
uwTick += (uint32_t)uwTickFreq;
|
|
8002438: 4b06 ldr r3, [pc, #24] @ (8002454 <HAL_IncTick+0x20>)
|
|
800243a: 781b ldrb r3, [r3, #0]
|
|
800243c: 461a mov r2, r3
|
|
800243e: 4b06 ldr r3, [pc, #24] @ (8002458 <HAL_IncTick+0x24>)
|
|
8002440: 681b ldr r3, [r3, #0]
|
|
8002442: 4413 add r3, r2
|
|
8002444: 4a04 ldr r2, [pc, #16] @ (8002458 <HAL_IncTick+0x24>)
|
|
8002446: 6013 str r3, [r2, #0]
|
|
}
|
|
8002448: bf00 nop
|
|
800244a: 46bd mov sp, r7
|
|
800244c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002450: 4770 bx lr
|
|
8002452: bf00 nop
|
|
8002454: 2000001c .word 0x2000001c
|
|
8002458: 20000328 .word 0x20000328
|
|
|
|
0800245c <HAL_GetTick>:
|
|
* @note This function is declared as __weak to be overwritten in case of other
|
|
* implementations in user file.
|
|
* @retval tick value
|
|
*/
|
|
__weak uint32_t HAL_GetTick(void)
|
|
{
|
|
800245c: b480 push {r7}
|
|
800245e: af00 add r7, sp, #0
|
|
return uwTick;
|
|
8002460: 4b03 ldr r3, [pc, #12] @ (8002470 <HAL_GetTick+0x14>)
|
|
8002462: 681b ldr r3, [r3, #0]
|
|
}
|
|
8002464: 4618 mov r0, r3
|
|
8002466: 46bd mov sp, r7
|
|
8002468: f85d 7b04 ldr.w r7, [sp], #4
|
|
800246c: 4770 bx lr
|
|
800246e: bf00 nop
|
|
8002470: 20000328 .word 0x20000328
|
|
|
|
08002474 <HAL_Delay>:
|
|
* implementations in user file.
|
|
* @param Delay specifies the delay time length, in milliseconds.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_Delay(uint32_t Delay)
|
|
{
|
|
8002474: b580 push {r7, lr}
|
|
8002476: b084 sub sp, #16
|
|
8002478: af00 add r7, sp, #0
|
|
800247a: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart = HAL_GetTick();
|
|
800247c: f7ff ffee bl 800245c <HAL_GetTick>
|
|
8002480: 60b8 str r0, [r7, #8]
|
|
uint32_t wait = Delay;
|
|
8002482: 687b ldr r3, [r7, #4]
|
|
8002484: 60fb str r3, [r7, #12]
|
|
|
|
/* Add a period to guaranty minimum wait */
|
|
if (wait < HAL_MAX_DELAY)
|
|
8002486: 68fb ldr r3, [r7, #12]
|
|
8002488: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
800248c: d005 beq.n 800249a <HAL_Delay+0x26>
|
|
{
|
|
wait += (uint32_t)uwTickFreq;
|
|
800248e: 4b0a ldr r3, [pc, #40] @ (80024b8 <HAL_Delay+0x44>)
|
|
8002490: 781b ldrb r3, [r3, #0]
|
|
8002492: 461a mov r2, r3
|
|
8002494: 68fb ldr r3, [r7, #12]
|
|
8002496: 4413 add r3, r2
|
|
8002498: 60fb str r3, [r7, #12]
|
|
}
|
|
|
|
while ((HAL_GetTick() - tickstart) < wait)
|
|
800249a: bf00 nop
|
|
800249c: f7ff ffde bl 800245c <HAL_GetTick>
|
|
80024a0: 4602 mov r2, r0
|
|
80024a2: 68bb ldr r3, [r7, #8]
|
|
80024a4: 1ad3 subs r3, r2, r3
|
|
80024a6: 68fa ldr r2, [r7, #12]
|
|
80024a8: 429a cmp r2, r3
|
|
80024aa: d8f7 bhi.n 800249c <HAL_Delay+0x28>
|
|
{
|
|
}
|
|
}
|
|
80024ac: bf00 nop
|
|
80024ae: bf00 nop
|
|
80024b0: 3710 adds r7, #16
|
|
80024b2: 46bd mov sp, r7
|
|
80024b4: bd80 pop {r7, pc}
|
|
80024b6: bf00 nop
|
|
80024b8: 2000001c .word 0x2000001c
|
|
|
|
080024bc <__NVIC_SetPriorityGrouping>:
|
|
In case of a conflict between priority grouping and available
|
|
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
|
\param [in] PriorityGroup Priority grouping field.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
80024bc: b480 push {r7}
|
|
80024be: b085 sub sp, #20
|
|
80024c0: af00 add r7, sp, #0
|
|
80024c2: 6078 str r0, [r7, #4]
|
|
uint32_t reg_value;
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
80024c4: 687b ldr r3, [r7, #4]
|
|
80024c6: f003 0307 and.w r3, r3, #7
|
|
80024ca: 60fb str r3, [r7, #12]
|
|
|
|
reg_value = SCB->AIRCR; /* read old register configuration */
|
|
80024cc: 4b0c ldr r3, [pc, #48] @ (8002500 <__NVIC_SetPriorityGrouping+0x44>)
|
|
80024ce: 68db ldr r3, [r3, #12]
|
|
80024d0: 60bb str r3, [r7, #8]
|
|
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
|
|
80024d2: 68ba ldr r2, [r7, #8]
|
|
80024d4: f64f 03ff movw r3, #63743 @ 0xf8ff
|
|
80024d8: 4013 ands r3, r2
|
|
80024da: 60bb str r3, [r7, #8]
|
|
reg_value = (reg_value |
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
|
|
80024dc: 68fb ldr r3, [r7, #12]
|
|
80024de: 021a lsls r2, r3, #8
|
|
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
80024e0: 68bb ldr r3, [r7, #8]
|
|
80024e2: 4313 orrs r3, r2
|
|
reg_value = (reg_value |
|
|
80024e4: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
|
|
80024e8: f443 3300 orr.w r3, r3, #131072 @ 0x20000
|
|
80024ec: 60bb str r3, [r7, #8]
|
|
SCB->AIRCR = reg_value;
|
|
80024ee: 4a04 ldr r2, [pc, #16] @ (8002500 <__NVIC_SetPriorityGrouping+0x44>)
|
|
80024f0: 68bb ldr r3, [r7, #8]
|
|
80024f2: 60d3 str r3, [r2, #12]
|
|
}
|
|
80024f4: bf00 nop
|
|
80024f6: 3714 adds r7, #20
|
|
80024f8: 46bd mov sp, r7
|
|
80024fa: f85d 7b04 ldr.w r7, [sp], #4
|
|
80024fe: 4770 bx lr
|
|
8002500: e000ed00 .word 0xe000ed00
|
|
|
|
08002504 <__NVIC_GetPriorityGrouping>:
|
|
\brief Get Priority Grouping
|
|
\details Reads the priority grouping field from the NVIC Interrupt Controller.
|
|
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
|
|
*/
|
|
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
|
|
{
|
|
8002504: b480 push {r7}
|
|
8002506: af00 add r7, sp, #0
|
|
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
|
|
8002508: 4b04 ldr r3, [pc, #16] @ (800251c <__NVIC_GetPriorityGrouping+0x18>)
|
|
800250a: 68db ldr r3, [r3, #12]
|
|
800250c: 0a1b lsrs r3, r3, #8
|
|
800250e: f003 0307 and.w r3, r3, #7
|
|
}
|
|
8002512: 4618 mov r0, r3
|
|
8002514: 46bd mov sp, r7
|
|
8002516: f85d 7b04 ldr.w r7, [sp], #4
|
|
800251a: 4770 bx lr
|
|
800251c: e000ed00 .word 0xe000ed00
|
|
|
|
08002520 <__NVIC_EnableIRQ>:
|
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
|
\param [in] IRQn Device specific interrupt number.
|
|
\note IRQn must not be negative.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
8002520: b480 push {r7}
|
|
8002522: b083 sub sp, #12
|
|
8002524: af00 add r7, sp, #0
|
|
8002526: 4603 mov r3, r0
|
|
8002528: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
800252a: f997 3007 ldrsb.w r3, [r7, #7]
|
|
800252e: 2b00 cmp r3, #0
|
|
8002530: db0b blt.n 800254a <__NVIC_EnableIRQ+0x2a>
|
|
{
|
|
__COMPILER_BARRIER();
|
|
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
8002532: 79fb ldrb r3, [r7, #7]
|
|
8002534: f003 021f and.w r2, r3, #31
|
|
8002538: 4907 ldr r1, [pc, #28] @ (8002558 <__NVIC_EnableIRQ+0x38>)
|
|
800253a: f997 3007 ldrsb.w r3, [r7, #7]
|
|
800253e: 095b lsrs r3, r3, #5
|
|
8002540: 2001 movs r0, #1
|
|
8002542: fa00 f202 lsl.w r2, r0, r2
|
|
8002546: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
__COMPILER_BARRIER();
|
|
}
|
|
}
|
|
800254a: bf00 nop
|
|
800254c: 370c adds r7, #12
|
|
800254e: 46bd mov sp, r7
|
|
8002550: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002554: 4770 bx lr
|
|
8002556: bf00 nop
|
|
8002558: e000e100 .word 0xe000e100
|
|
|
|
0800255c <__NVIC_SetPriority>:
|
|
\param [in] IRQn Interrupt number.
|
|
\param [in] priority Priority to set.
|
|
\note The priority cannot be set for every processor exception.
|
|
*/
|
|
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
|
{
|
|
800255c: b480 push {r7}
|
|
800255e: b083 sub sp, #12
|
|
8002560: af00 add r7, sp, #0
|
|
8002562: 4603 mov r3, r0
|
|
8002564: 6039 str r1, [r7, #0]
|
|
8002566: 71fb strb r3, [r7, #7]
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8002568: f997 3007 ldrsb.w r3, [r7, #7]
|
|
800256c: 2b00 cmp r3, #0
|
|
800256e: db0a blt.n 8002586 <__NVIC_SetPriority+0x2a>
|
|
{
|
|
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8002570: 683b ldr r3, [r7, #0]
|
|
8002572: b2da uxtb r2, r3
|
|
8002574: 490c ldr r1, [pc, #48] @ (80025a8 <__NVIC_SetPriority+0x4c>)
|
|
8002576: f997 3007 ldrsb.w r3, [r7, #7]
|
|
800257a: 0112 lsls r2, r2, #4
|
|
800257c: b2d2 uxtb r2, r2
|
|
800257e: 440b add r3, r1
|
|
8002580: f883 2300 strb.w r2, [r3, #768] @ 0x300
|
|
}
|
|
else
|
|
{
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
}
|
|
}
|
|
8002584: e00a b.n 800259c <__NVIC_SetPriority+0x40>
|
|
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
|
|
8002586: 683b ldr r3, [r7, #0]
|
|
8002588: b2da uxtb r2, r3
|
|
800258a: 4908 ldr r1, [pc, #32] @ (80025ac <__NVIC_SetPriority+0x50>)
|
|
800258c: 79fb ldrb r3, [r7, #7]
|
|
800258e: f003 030f and.w r3, r3, #15
|
|
8002592: 3b04 subs r3, #4
|
|
8002594: 0112 lsls r2, r2, #4
|
|
8002596: b2d2 uxtb r2, r2
|
|
8002598: 440b add r3, r1
|
|
800259a: 761a strb r2, [r3, #24]
|
|
}
|
|
800259c: bf00 nop
|
|
800259e: 370c adds r7, #12
|
|
80025a0: 46bd mov sp, r7
|
|
80025a2: f85d 7b04 ldr.w r7, [sp], #4
|
|
80025a6: 4770 bx lr
|
|
80025a8: e000e100 .word 0xe000e100
|
|
80025ac: e000ed00 .word 0xe000ed00
|
|
|
|
080025b0 <NVIC_EncodePriority>:
|
|
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
|
\param [in] SubPriority Subpriority value (starting from 0).
|
|
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
|
*/
|
|
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
80025b0: b480 push {r7}
|
|
80025b2: b089 sub sp, #36 @ 0x24
|
|
80025b4: af00 add r7, sp, #0
|
|
80025b6: 60f8 str r0, [r7, #12]
|
|
80025b8: 60b9 str r1, [r7, #8]
|
|
80025ba: 607a str r2, [r7, #4]
|
|
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
|
80025bc: 68fb ldr r3, [r7, #12]
|
|
80025be: f003 0307 and.w r3, r3, #7
|
|
80025c2: 61fb str r3, [r7, #28]
|
|
uint32_t PreemptPriorityBits;
|
|
uint32_t SubPriorityBits;
|
|
|
|
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
|
80025c4: 69fb ldr r3, [r7, #28]
|
|
80025c6: f1c3 0307 rsb r3, r3, #7
|
|
80025ca: 2b04 cmp r3, #4
|
|
80025cc: bf28 it cs
|
|
80025ce: 2304 movcs r3, #4
|
|
80025d0: 61bb str r3, [r7, #24]
|
|
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
|
80025d2: 69fb ldr r3, [r7, #28]
|
|
80025d4: 3304 adds r3, #4
|
|
80025d6: 2b06 cmp r3, #6
|
|
80025d8: d902 bls.n 80025e0 <NVIC_EncodePriority+0x30>
|
|
80025da: 69fb ldr r3, [r7, #28]
|
|
80025dc: 3b03 subs r3, #3
|
|
80025de: e000 b.n 80025e2 <NVIC_EncodePriority+0x32>
|
|
80025e0: 2300 movs r3, #0
|
|
80025e2: 617b str r3, [r7, #20]
|
|
|
|
return (
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
80025e4: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
80025e8: 69bb ldr r3, [r7, #24]
|
|
80025ea: fa02 f303 lsl.w r3, r2, r3
|
|
80025ee: 43da mvns r2, r3
|
|
80025f0: 68bb ldr r3, [r7, #8]
|
|
80025f2: 401a ands r2, r3
|
|
80025f4: 697b ldr r3, [r7, #20]
|
|
80025f6: 409a lsls r2, r3
|
|
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
|
80025f8: f04f 31ff mov.w r1, #4294967295 @ 0xffffffff
|
|
80025fc: 697b ldr r3, [r7, #20]
|
|
80025fe: fa01 f303 lsl.w r3, r1, r3
|
|
8002602: 43d9 mvns r1, r3
|
|
8002604: 687b ldr r3, [r7, #4]
|
|
8002606: 400b ands r3, r1
|
|
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
|
8002608: 4313 orrs r3, r2
|
|
);
|
|
}
|
|
800260a: 4618 mov r0, r3
|
|
800260c: 3724 adds r7, #36 @ 0x24
|
|
800260e: 46bd mov sp, r7
|
|
8002610: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002614: 4770 bx lr
|
|
...
|
|
|
|
08002618 <SysTick_Config>:
|
|
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
|
must contain a vendor-specific implementation of this function.
|
|
*/
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
{
|
|
8002618: b580 push {r7, lr}
|
|
800261a: b082 sub sp, #8
|
|
800261c: af00 add r7, sp, #0
|
|
800261e: 6078 str r0, [r7, #4]
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
|
8002620: 687b ldr r3, [r7, #4]
|
|
8002622: 3b01 subs r3, #1
|
|
8002624: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
8002628: d301 bcc.n 800262e <SysTick_Config+0x16>
|
|
{
|
|
return (1UL); /* Reload value impossible */
|
|
800262a: 2301 movs r3, #1
|
|
800262c: e00f b.n 800264e <SysTick_Config+0x36>
|
|
}
|
|
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|
800262e: 4a0a ldr r2, [pc, #40] @ (8002658 <SysTick_Config+0x40>)
|
|
8002630: 687b ldr r3, [r7, #4]
|
|
8002632: 3b01 subs r3, #1
|
|
8002634: 6053 str r3, [r2, #4]
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
|
8002636: 210f movs r1, #15
|
|
8002638: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
800263c: f7ff ff8e bl 800255c <__NVIC_SetPriority>
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
8002640: 4b05 ldr r3, [pc, #20] @ (8002658 <SysTick_Config+0x40>)
|
|
8002642: 2200 movs r2, #0
|
|
8002644: 609a str r2, [r3, #8]
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
8002646: 4b04 ldr r3, [pc, #16] @ (8002658 <SysTick_Config+0x40>)
|
|
8002648: 2207 movs r2, #7
|
|
800264a: 601a str r2, [r3, #0]
|
|
SysTick_CTRL_TICKINT_Msk |
|
|
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
|
return (0UL); /* Function successful */
|
|
800264c: 2300 movs r3, #0
|
|
}
|
|
800264e: 4618 mov r0, r3
|
|
8002650: 3708 adds r7, #8
|
|
8002652: 46bd mov sp, r7
|
|
8002654: bd80 pop {r7, pc}
|
|
8002656: bf00 nop
|
|
8002658: e000e010 .word 0xe000e010
|
|
|
|
0800265c <HAL_NVIC_SetPriorityGrouping>:
|
|
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
|
|
* The pending IRQ priority will be managed only by the subpriority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
|
|
{
|
|
800265c: b580 push {r7, lr}
|
|
800265e: b082 sub sp, #8
|
|
8002660: af00 add r7, sp, #0
|
|
8002662: 6078 str r0, [r7, #4]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
|
|
|
|
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
|
|
NVIC_SetPriorityGrouping(PriorityGroup);
|
|
8002664: 6878 ldr r0, [r7, #4]
|
|
8002666: f7ff ff29 bl 80024bc <__NVIC_SetPriorityGrouping>
|
|
}
|
|
800266a: bf00 nop
|
|
800266c: 3708 adds r7, #8
|
|
800266e: 46bd mov sp, r7
|
|
8002670: bd80 pop {r7, pc}
|
|
|
|
08002672 <HAL_NVIC_SetPriority>:
|
|
* This parameter can be a value between 0 and 15
|
|
* A lower priority value indicates a higher priority.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8002672: b580 push {r7, lr}
|
|
8002674: b086 sub sp, #24
|
|
8002676: af00 add r7, sp, #0
|
|
8002678: 4603 mov r3, r0
|
|
800267a: 60b9 str r1, [r7, #8]
|
|
800267c: 607a str r2, [r7, #4]
|
|
800267e: 73fb strb r3, [r7, #15]
|
|
uint32_t prioritygroup = 0x00;
|
|
8002680: 2300 movs r3, #0
|
|
8002682: 617b str r3, [r7, #20]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
|
|
prioritygroup = NVIC_GetPriorityGrouping();
|
|
8002684: f7ff ff3e bl 8002504 <__NVIC_GetPriorityGrouping>
|
|
8002688: 6178 str r0, [r7, #20]
|
|
|
|
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
|
|
800268a: 687a ldr r2, [r7, #4]
|
|
800268c: 68b9 ldr r1, [r7, #8]
|
|
800268e: 6978 ldr r0, [r7, #20]
|
|
8002690: f7ff ff8e bl 80025b0 <NVIC_EncodePriority>
|
|
8002694: 4602 mov r2, r0
|
|
8002696: f997 300f ldrsb.w r3, [r7, #15]
|
|
800269a: 4611 mov r1, r2
|
|
800269c: 4618 mov r0, r3
|
|
800269e: f7ff ff5d bl 800255c <__NVIC_SetPriority>
|
|
}
|
|
80026a2: bf00 nop
|
|
80026a4: 3718 adds r7, #24
|
|
80026a6: 46bd mov sp, r7
|
|
80026a8: bd80 pop {r7, pc}
|
|
|
|
080026aa <HAL_NVIC_EnableIRQ>:
|
|
* This parameter can be an enumerator of IRQn_Type enumeration
|
|
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h))
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
|
|
{
|
|
80026aa: b580 push {r7, lr}
|
|
80026ac: b082 sub sp, #8
|
|
80026ae: af00 add r7, sp, #0
|
|
80026b0: 4603 mov r3, r0
|
|
80026b2: 71fb strb r3, [r7, #7]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
|
|
|
/* Enable interrupt */
|
|
NVIC_EnableIRQ(IRQn);
|
|
80026b4: f997 3007 ldrsb.w r3, [r7, #7]
|
|
80026b8: 4618 mov r0, r3
|
|
80026ba: f7ff ff31 bl 8002520 <__NVIC_EnableIRQ>
|
|
}
|
|
80026be: bf00 nop
|
|
80026c0: 3708 adds r7, #8
|
|
80026c2: 46bd mov sp, r7
|
|
80026c4: bd80 pop {r7, pc}
|
|
|
|
080026c6 <HAL_SYSTICK_Config>:
|
|
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
|
|
* @retval status: - 0 Function succeeded.
|
|
* - 1 Function failed.
|
|
*/
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
|
{
|
|
80026c6: b580 push {r7, lr}
|
|
80026c8: b082 sub sp, #8
|
|
80026ca: af00 add r7, sp, #0
|
|
80026cc: 6078 str r0, [r7, #4]
|
|
return SysTick_Config(TicksNumb);
|
|
80026ce: 6878 ldr r0, [r7, #4]
|
|
80026d0: f7ff ffa2 bl 8002618 <SysTick_Config>
|
|
80026d4: 4603 mov r3, r0
|
|
}
|
|
80026d6: 4618 mov r0, r3
|
|
80026d8: 3708 adds r7, #8
|
|
80026da: 46bd mov sp, r7
|
|
80026dc: bd80 pop {r7, pc}
|
|
|
|
080026de <HAL_DMA_Abort>:
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
|
|
{
|
|
80026de: b480 push {r7}
|
|
80026e0: b085 sub sp, #20
|
|
80026e2: af00 add r7, sp, #0
|
|
80026e4: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80026e6: 2300 movs r3, #0
|
|
80026e8: 73fb strb r3, [r7, #15]
|
|
|
|
/* Check the DMA peripheral state */
|
|
if (hdma->State != HAL_DMA_STATE_BUSY)
|
|
80026ea: 687b ldr r3, [r7, #4]
|
|
80026ec: f893 3025 ldrb.w r3, [r3, #37] @ 0x25
|
|
80026f0: b2db uxtb r3, r3
|
|
80026f2: 2b02 cmp r3, #2
|
|
80026f4: d008 beq.n 8002708 <HAL_DMA_Abort+0x2a>
|
|
{
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
|
80026f6: 687b ldr r3, [r7, #4]
|
|
80026f8: 2204 movs r2, #4
|
|
80026fa: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
80026fc: 687b ldr r3, [r7, #4]
|
|
80026fe: 2200 movs r2, #0
|
|
8002700: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
return HAL_ERROR;
|
|
8002704: 2301 movs r3, #1
|
|
8002706: e022 b.n 800274e <HAL_DMA_Abort+0x70>
|
|
}
|
|
else
|
|
{
|
|
/* Disable DMA IT */
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|
8002708: 687b ldr r3, [r7, #4]
|
|
800270a: 681b ldr r3, [r3, #0]
|
|
800270c: 681a ldr r2, [r3, #0]
|
|
800270e: 687b ldr r3, [r7, #4]
|
|
8002710: 681b ldr r3, [r3, #0]
|
|
8002712: f022 020e bic.w r2, r2, #14
|
|
8002716: 601a str r2, [r3, #0]
|
|
/* disable the DMAMUX sync overrun IT*/
|
|
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
|
|
#endif /* DMAMUX1 */
|
|
|
|
/* Disable the channel */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
8002718: 687b ldr r3, [r7, #4]
|
|
800271a: 681b ldr r3, [r3, #0]
|
|
800271c: 681a ldr r2, [r3, #0]
|
|
800271e: 687b ldr r3, [r7, #4]
|
|
8002720: 681b ldr r3, [r3, #0]
|
|
8002722: f022 0201 bic.w r2, r2, #1
|
|
8002726: 601a str r2, [r3, #0]
|
|
|
|
/* Clear all flags */
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
|
|
8002728: 687b ldr r3, [r7, #4]
|
|
800272a: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800272c: f003 021c and.w r2, r3, #28
|
|
8002730: 687b ldr r3, [r7, #4]
|
|
8002732: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8002734: 2101 movs r1, #1
|
|
8002736: fa01 f202 lsl.w r2, r1, r2
|
|
800273a: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
#endif /* DMAMUX1 */
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
800273c: 687b ldr r3, [r7, #4]
|
|
800273e: 2201 movs r2, #1
|
|
8002740: f883 2025 strb.w r2, [r3, #37] @ 0x25
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
8002744: 687b ldr r3, [r7, #4]
|
|
8002746: 2200 movs r2, #0
|
|
8002748: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
return status;
|
|
800274c: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
}
|
|
800274e: 4618 mov r0, r3
|
|
8002750: 3714 adds r7, #20
|
|
8002752: 46bd mov sp, r7
|
|
8002754: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002758: 4770 bx lr
|
|
|
|
0800275a <HAL_DMA_Abort_IT>:
|
|
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Channel.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
|
|
{
|
|
800275a: b580 push {r7, lr}
|
|
800275c: b084 sub sp, #16
|
|
800275e: af00 add r7, sp, #0
|
|
8002760: 6078 str r0, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8002762: 2300 movs r3, #0
|
|
8002764: 73fb strb r3, [r7, #15]
|
|
|
|
if (HAL_DMA_STATE_BUSY != hdma->State)
|
|
8002766: 687b ldr r3, [r7, #4]
|
|
8002768: f893 3025 ldrb.w r3, [r3, #37] @ 0x25
|
|
800276c: b2db uxtb r3, r3
|
|
800276e: 2b02 cmp r3, #2
|
|
8002770: d005 beq.n 800277e <HAL_DMA_Abort_IT+0x24>
|
|
{
|
|
/* no transfer ongoing */
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
|
8002772: 687b ldr r3, [r7, #4]
|
|
8002774: 2204 movs r2, #4
|
|
8002776: 63da str r2, [r3, #60] @ 0x3c
|
|
|
|
status = HAL_ERROR;
|
|
8002778: 2301 movs r3, #1
|
|
800277a: 73fb strb r3, [r7, #15]
|
|
800277c: e029 b.n 80027d2 <HAL_DMA_Abort_IT+0x78>
|
|
}
|
|
else
|
|
{
|
|
/* Disable DMA IT */
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|
800277e: 687b ldr r3, [r7, #4]
|
|
8002780: 681b ldr r3, [r3, #0]
|
|
8002782: 681a ldr r2, [r3, #0]
|
|
8002784: 687b ldr r3, [r7, #4]
|
|
8002786: 681b ldr r3, [r3, #0]
|
|
8002788: f022 020e bic.w r2, r2, #14
|
|
800278c: 601a str r2, [r3, #0]
|
|
|
|
/* Disable the channel */
|
|
__HAL_DMA_DISABLE(hdma);
|
|
800278e: 687b ldr r3, [r7, #4]
|
|
8002790: 681b ldr r3, [r3, #0]
|
|
8002792: 681a ldr r2, [r3, #0]
|
|
8002794: 687b ldr r3, [r7, #4]
|
|
8002796: 681b ldr r3, [r3, #0]
|
|
8002798: f022 0201 bic.w r2, r2, #1
|
|
800279c: 601a str r2, [r3, #0]
|
|
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
|
|
}
|
|
|
|
#else
|
|
/* Clear all flags */
|
|
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
|
|
800279e: 687b ldr r3, [r7, #4]
|
|
80027a0: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80027a2: f003 021c and.w r2, r3, #28
|
|
80027a6: 687b ldr r3, [r7, #4]
|
|
80027a8: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80027aa: 2101 movs r1, #1
|
|
80027ac: fa01 f202 lsl.w r2, r1, r2
|
|
80027b0: 605a str r2, [r3, #4]
|
|
#endif /* DMAMUX1 */
|
|
|
|
/* Change the DMA state */
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
80027b2: 687b ldr r3, [r7, #4]
|
|
80027b4: 2201 movs r2, #1
|
|
80027b6: f883 2025 strb.w r2, [r3, #37] @ 0x25
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hdma);
|
|
80027ba: 687b ldr r3, [r7, #4]
|
|
80027bc: 2200 movs r2, #0
|
|
80027be: f883 2024 strb.w r2, [r3, #36] @ 0x24
|
|
|
|
/* Call User Abort callback */
|
|
if (hdma->XferAbortCallback != NULL)
|
|
80027c2: 687b ldr r3, [r7, #4]
|
|
80027c4: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80027c6: 2b00 cmp r3, #0
|
|
80027c8: d003 beq.n 80027d2 <HAL_DMA_Abort_IT+0x78>
|
|
{
|
|
hdma->XferAbortCallback(hdma);
|
|
80027ca: 687b ldr r3, [r7, #4]
|
|
80027cc: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
80027ce: 6878 ldr r0, [r7, #4]
|
|
80027d0: 4798 blx r3
|
|
}
|
|
}
|
|
return status;
|
|
80027d2: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
80027d4: 4618 mov r0, r3
|
|
80027d6: 3710 adds r7, #16
|
|
80027d8: 46bd mov sp, r7
|
|
80027da: bd80 pop {r7, pc}
|
|
|
|
080027dc <HAL_GPIO_Init>:
|
|
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
|
|
* the configuration information for the specified GPIO peripheral.
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
|
|
{
|
|
80027dc: b480 push {r7}
|
|
80027de: b087 sub sp, #28
|
|
80027e0: af00 add r7, sp, #0
|
|
80027e2: 6078 str r0, [r7, #4]
|
|
80027e4: 6039 str r1, [r7, #0]
|
|
uint32_t position = 0x00u;
|
|
80027e6: 2300 movs r3, #0
|
|
80027e8: 617b str r3, [r7, #20]
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
|
|
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
|
|
|
|
/* Configure the port pins */
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
80027ea: e17f b.n 8002aec <HAL_GPIO_Init+0x310>
|
|
{
|
|
/* Get current io position */
|
|
iocurrent = (GPIO_Init->Pin) & (1uL << position);
|
|
80027ec: 683b ldr r3, [r7, #0]
|
|
80027ee: 681a ldr r2, [r3, #0]
|
|
80027f0: 2101 movs r1, #1
|
|
80027f2: 697b ldr r3, [r7, #20]
|
|
80027f4: fa01 f303 lsl.w r3, r1, r3
|
|
80027f8: 4013 ands r3, r2
|
|
80027fa: 60fb str r3, [r7, #12]
|
|
|
|
if (iocurrent != 0x00u)
|
|
80027fc: 68fb ldr r3, [r7, #12]
|
|
80027fe: 2b00 cmp r3, #0
|
|
8002800: f000 8171 beq.w 8002ae6 <HAL_GPIO_Init+0x30a>
|
|
{
|
|
/*--------------------- GPIO Mode Configuration ------------------------*/
|
|
/* In case of Output or Alternate function mode selection */
|
|
if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
|
|
8002804: 683b ldr r3, [r7, #0]
|
|
8002806: 685b ldr r3, [r3, #4]
|
|
8002808: f003 0303 and.w r3, r3, #3
|
|
800280c: 2b01 cmp r3, #1
|
|
800280e: d005 beq.n 800281c <HAL_GPIO_Init+0x40>
|
|
8002810: 683b ldr r3, [r7, #0]
|
|
8002812: 685b ldr r3, [r3, #4]
|
|
8002814: f003 0303 and.w r3, r3, #3
|
|
8002818: 2b02 cmp r3, #2
|
|
800281a: d130 bne.n 800287e <HAL_GPIO_Init+0xa2>
|
|
{
|
|
/* Check the Speed parameter */
|
|
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
|
|
|
|
/* Configure the IO Speed */
|
|
temp = GPIOx->OSPEEDR;
|
|
800281c: 687b ldr r3, [r7, #4]
|
|
800281e: 689b ldr r3, [r3, #8]
|
|
8002820: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2u));
|
|
8002822: 697b ldr r3, [r7, #20]
|
|
8002824: 005b lsls r3, r3, #1
|
|
8002826: 2203 movs r2, #3
|
|
8002828: fa02 f303 lsl.w r3, r2, r3
|
|
800282c: 43db mvns r3, r3
|
|
800282e: 693a ldr r2, [r7, #16]
|
|
8002830: 4013 ands r3, r2
|
|
8002832: 613b str r3, [r7, #16]
|
|
temp |= (GPIO_Init->Speed << (position * 2u));
|
|
8002834: 683b ldr r3, [r7, #0]
|
|
8002836: 68da ldr r2, [r3, #12]
|
|
8002838: 697b ldr r3, [r7, #20]
|
|
800283a: 005b lsls r3, r3, #1
|
|
800283c: fa02 f303 lsl.w r3, r2, r3
|
|
8002840: 693a ldr r2, [r7, #16]
|
|
8002842: 4313 orrs r3, r2
|
|
8002844: 613b str r3, [r7, #16]
|
|
GPIOx->OSPEEDR = temp;
|
|
8002846: 687b ldr r3, [r7, #4]
|
|
8002848: 693a ldr r2, [r7, #16]
|
|
800284a: 609a str r2, [r3, #8]
|
|
|
|
/* Configure the IO Output Type */
|
|
temp = GPIOx->OTYPER;
|
|
800284c: 687b ldr r3, [r7, #4]
|
|
800284e: 685b ldr r3, [r3, #4]
|
|
8002850: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_OTYPER_OT0 << position) ;
|
|
8002852: 2201 movs r2, #1
|
|
8002854: 697b ldr r3, [r7, #20]
|
|
8002856: fa02 f303 lsl.w r3, r2, r3
|
|
800285a: 43db mvns r3, r3
|
|
800285c: 693a ldr r2, [r7, #16]
|
|
800285e: 4013 ands r3, r2
|
|
8002860: 613b str r3, [r7, #16]
|
|
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
|
|
8002862: 683b ldr r3, [r7, #0]
|
|
8002864: 685b ldr r3, [r3, #4]
|
|
8002866: 091b lsrs r3, r3, #4
|
|
8002868: f003 0201 and.w r2, r3, #1
|
|
800286c: 697b ldr r3, [r7, #20]
|
|
800286e: fa02 f303 lsl.w r3, r2, r3
|
|
8002872: 693a ldr r2, [r7, #16]
|
|
8002874: 4313 orrs r3, r2
|
|
8002876: 613b str r3, [r7, #16]
|
|
GPIOx->OTYPER = temp;
|
|
8002878: 687b ldr r3, [r7, #4]
|
|
800287a: 693a ldr r2, [r7, #16]
|
|
800287c: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx)
|
|
|
|
/* In case of Analog mode, check if ADC control mode is selected */
|
|
if((GPIO_Init->Mode & GPIO_MODE_ANALOG) == GPIO_MODE_ANALOG)
|
|
800287e: 683b ldr r3, [r7, #0]
|
|
8002880: 685b ldr r3, [r3, #4]
|
|
8002882: f003 0303 and.w r3, r3, #3
|
|
8002886: 2b03 cmp r3, #3
|
|
8002888: d118 bne.n 80028bc <HAL_GPIO_Init+0xe0>
|
|
{
|
|
/* Configure the IO Output Type */
|
|
temp = GPIOx->ASCR;
|
|
800288a: 687b ldr r3, [r7, #4]
|
|
800288c: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
800288e: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_ASCR_ASC0 << position) ;
|
|
8002890: 2201 movs r2, #1
|
|
8002892: 697b ldr r3, [r7, #20]
|
|
8002894: fa02 f303 lsl.w r3, r2, r3
|
|
8002898: 43db mvns r3, r3
|
|
800289a: 693a ldr r2, [r7, #16]
|
|
800289c: 4013 ands r3, r2
|
|
800289e: 613b str r3, [r7, #16]
|
|
temp |= (((GPIO_Init->Mode & GPIO_MODE_ANALOG_ADC_CONTROL) >> 3) << position);
|
|
80028a0: 683b ldr r3, [r7, #0]
|
|
80028a2: 685b ldr r3, [r3, #4]
|
|
80028a4: 08db lsrs r3, r3, #3
|
|
80028a6: f003 0201 and.w r2, r3, #1
|
|
80028aa: 697b ldr r3, [r7, #20]
|
|
80028ac: fa02 f303 lsl.w r3, r2, r3
|
|
80028b0: 693a ldr r2, [r7, #16]
|
|
80028b2: 4313 orrs r3, r2
|
|
80028b4: 613b str r3, [r7, #16]
|
|
GPIOx->ASCR = temp;
|
|
80028b6: 687b ldr r3, [r7, #4]
|
|
80028b8: 693a ldr r2, [r7, #16]
|
|
80028ba: 62da str r2, [r3, #44] @ 0x2c
|
|
}
|
|
|
|
#endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx */
|
|
|
|
/* Activate the Pull-up or Pull down resistor for the current IO */
|
|
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
|
|
80028bc: 683b ldr r3, [r7, #0]
|
|
80028be: 685b ldr r3, [r3, #4]
|
|
80028c0: f003 0303 and.w r3, r3, #3
|
|
80028c4: 2b03 cmp r3, #3
|
|
80028c6: d017 beq.n 80028f8 <HAL_GPIO_Init+0x11c>
|
|
{
|
|
/* Check the Pull parameter */
|
|
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
|
|
|
|
temp = GPIOx->PUPDR;
|
|
80028c8: 687b ldr r3, [r7, #4]
|
|
80028ca: 68db ldr r3, [r3, #12]
|
|
80028cc: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
|
|
80028ce: 697b ldr r3, [r7, #20]
|
|
80028d0: 005b lsls r3, r3, #1
|
|
80028d2: 2203 movs r2, #3
|
|
80028d4: fa02 f303 lsl.w r3, r2, r3
|
|
80028d8: 43db mvns r3, r3
|
|
80028da: 693a ldr r2, [r7, #16]
|
|
80028dc: 4013 ands r3, r2
|
|
80028de: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Pull) << (position * 2U));
|
|
80028e0: 683b ldr r3, [r7, #0]
|
|
80028e2: 689a ldr r2, [r3, #8]
|
|
80028e4: 697b ldr r3, [r7, #20]
|
|
80028e6: 005b lsls r3, r3, #1
|
|
80028e8: fa02 f303 lsl.w r3, r2, r3
|
|
80028ec: 693a ldr r2, [r7, #16]
|
|
80028ee: 4313 orrs r3, r2
|
|
80028f0: 613b str r3, [r7, #16]
|
|
GPIOx->PUPDR = temp;
|
|
80028f2: 687b ldr r3, [r7, #4]
|
|
80028f4: 693a ldr r2, [r7, #16]
|
|
80028f6: 60da str r2, [r3, #12]
|
|
}
|
|
|
|
/* In case of Alternate function mode selection */
|
|
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
|
|
80028f8: 683b ldr r3, [r7, #0]
|
|
80028fa: 685b ldr r3, [r3, #4]
|
|
80028fc: f003 0303 and.w r3, r3, #3
|
|
8002900: 2b02 cmp r3, #2
|
|
8002902: d123 bne.n 800294c <HAL_GPIO_Init+0x170>
|
|
/* Check the Alternate function parameters */
|
|
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
|
|
|
|
/* Configure Alternate function mapped with the current IO */
|
|
temp = GPIOx->AFR[position >> 3u];
|
|
8002904: 697b ldr r3, [r7, #20]
|
|
8002906: 08da lsrs r2, r3, #3
|
|
8002908: 687b ldr r3, [r7, #4]
|
|
800290a: 3208 adds r2, #8
|
|
800290c: f853 3022 ldr.w r3, [r3, r2, lsl #2]
|
|
8002910: 613b str r3, [r7, #16]
|
|
temp &= ~(0xFu << ((position & 0x07u) * 4u));
|
|
8002912: 697b ldr r3, [r7, #20]
|
|
8002914: f003 0307 and.w r3, r3, #7
|
|
8002918: 009b lsls r3, r3, #2
|
|
800291a: 220f movs r2, #15
|
|
800291c: fa02 f303 lsl.w r3, r2, r3
|
|
8002920: 43db mvns r3, r3
|
|
8002922: 693a ldr r2, [r7, #16]
|
|
8002924: 4013 ands r3, r2
|
|
8002926: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Alternate) << ((position & 0x07u) * 4u));
|
|
8002928: 683b ldr r3, [r7, #0]
|
|
800292a: 691a ldr r2, [r3, #16]
|
|
800292c: 697b ldr r3, [r7, #20]
|
|
800292e: f003 0307 and.w r3, r3, #7
|
|
8002932: 009b lsls r3, r3, #2
|
|
8002934: fa02 f303 lsl.w r3, r2, r3
|
|
8002938: 693a ldr r2, [r7, #16]
|
|
800293a: 4313 orrs r3, r2
|
|
800293c: 613b str r3, [r7, #16]
|
|
GPIOx->AFR[position >> 3u] = temp;
|
|
800293e: 697b ldr r3, [r7, #20]
|
|
8002940: 08da lsrs r2, r3, #3
|
|
8002942: 687b ldr r3, [r7, #4]
|
|
8002944: 3208 adds r2, #8
|
|
8002946: 6939 ldr r1, [r7, #16]
|
|
8002948: f843 1022 str.w r1, [r3, r2, lsl #2]
|
|
}
|
|
|
|
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
|
|
temp = GPIOx->MODER;
|
|
800294c: 687b ldr r3, [r7, #4]
|
|
800294e: 681b ldr r3, [r3, #0]
|
|
8002950: 613b str r3, [r7, #16]
|
|
temp &= ~(GPIO_MODER_MODE0 << (position * 2u));
|
|
8002952: 697b ldr r3, [r7, #20]
|
|
8002954: 005b lsls r3, r3, #1
|
|
8002956: 2203 movs r2, #3
|
|
8002958: fa02 f303 lsl.w r3, r2, r3
|
|
800295c: 43db mvns r3, r3
|
|
800295e: 693a ldr r2, [r7, #16]
|
|
8002960: 4013 ands r3, r2
|
|
8002962: 613b str r3, [r7, #16]
|
|
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2u));
|
|
8002964: 683b ldr r3, [r7, #0]
|
|
8002966: 685b ldr r3, [r3, #4]
|
|
8002968: f003 0203 and.w r2, r3, #3
|
|
800296c: 697b ldr r3, [r7, #20]
|
|
800296e: 005b lsls r3, r3, #1
|
|
8002970: fa02 f303 lsl.w r3, r2, r3
|
|
8002974: 693a ldr r2, [r7, #16]
|
|
8002976: 4313 orrs r3, r2
|
|
8002978: 613b str r3, [r7, #16]
|
|
GPIOx->MODER = temp;
|
|
800297a: 687b ldr r3, [r7, #4]
|
|
800297c: 693a ldr r2, [r7, #16]
|
|
800297e: 601a str r2, [r3, #0]
|
|
|
|
/*--------------------- EXTI Mode Configuration ------------------------*/
|
|
/* Configure the External Interrupt or event for the current IO */
|
|
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
|
|
8002980: 683b ldr r3, [r7, #0]
|
|
8002982: 685b ldr r3, [r3, #4]
|
|
8002984: f403 3340 and.w r3, r3, #196608 @ 0x30000
|
|
8002988: 2b00 cmp r3, #0
|
|
800298a: f000 80ac beq.w 8002ae6 <HAL_GPIO_Init+0x30a>
|
|
{
|
|
/* Enable SYSCFG Clock */
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
800298e: 4b5f ldr r3, [pc, #380] @ (8002b0c <HAL_GPIO_Init+0x330>)
|
|
8002990: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8002992: 4a5e ldr r2, [pc, #376] @ (8002b0c <HAL_GPIO_Init+0x330>)
|
|
8002994: f043 0301 orr.w r3, r3, #1
|
|
8002998: 6613 str r3, [r2, #96] @ 0x60
|
|
800299a: 4b5c ldr r3, [pc, #368] @ (8002b0c <HAL_GPIO_Init+0x330>)
|
|
800299c: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800299e: f003 0301 and.w r3, r3, #1
|
|
80029a2: 60bb str r3, [r7, #8]
|
|
80029a4: 68bb ldr r3, [r7, #8]
|
|
|
|
temp = SYSCFG->EXTICR[position >> 2u];
|
|
80029a6: 4a5a ldr r2, [pc, #360] @ (8002b10 <HAL_GPIO_Init+0x334>)
|
|
80029a8: 697b ldr r3, [r7, #20]
|
|
80029aa: 089b lsrs r3, r3, #2
|
|
80029ac: 3302 adds r3, #2
|
|
80029ae: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
80029b2: 613b str r3, [r7, #16]
|
|
temp &= ~(0x0FuL << (4u * (position & 0x03u)));
|
|
80029b4: 697b ldr r3, [r7, #20]
|
|
80029b6: f003 0303 and.w r3, r3, #3
|
|
80029ba: 009b lsls r3, r3, #2
|
|
80029bc: 220f movs r2, #15
|
|
80029be: fa02 f303 lsl.w r3, r2, r3
|
|
80029c2: 43db mvns r3, r3
|
|
80029c4: 693a ldr r2, [r7, #16]
|
|
80029c6: 4013 ands r3, r2
|
|
80029c8: 613b str r3, [r7, #16]
|
|
temp |= (GPIO_GET_INDEX(GPIOx) << (4u * (position & 0x03u)));
|
|
80029ca: 687b ldr r3, [r7, #4]
|
|
80029cc: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000
|
|
80029d0: d025 beq.n 8002a1e <HAL_GPIO_Init+0x242>
|
|
80029d2: 687b ldr r3, [r7, #4]
|
|
80029d4: 4a4f ldr r2, [pc, #316] @ (8002b14 <HAL_GPIO_Init+0x338>)
|
|
80029d6: 4293 cmp r3, r2
|
|
80029d8: d01f beq.n 8002a1a <HAL_GPIO_Init+0x23e>
|
|
80029da: 687b ldr r3, [r7, #4]
|
|
80029dc: 4a4e ldr r2, [pc, #312] @ (8002b18 <HAL_GPIO_Init+0x33c>)
|
|
80029de: 4293 cmp r3, r2
|
|
80029e0: d019 beq.n 8002a16 <HAL_GPIO_Init+0x23a>
|
|
80029e2: 687b ldr r3, [r7, #4]
|
|
80029e4: 4a4d ldr r2, [pc, #308] @ (8002b1c <HAL_GPIO_Init+0x340>)
|
|
80029e6: 4293 cmp r3, r2
|
|
80029e8: d013 beq.n 8002a12 <HAL_GPIO_Init+0x236>
|
|
80029ea: 687b ldr r3, [r7, #4]
|
|
80029ec: 4a4c ldr r2, [pc, #304] @ (8002b20 <HAL_GPIO_Init+0x344>)
|
|
80029ee: 4293 cmp r3, r2
|
|
80029f0: d00d beq.n 8002a0e <HAL_GPIO_Init+0x232>
|
|
80029f2: 687b ldr r3, [r7, #4]
|
|
80029f4: 4a4b ldr r2, [pc, #300] @ (8002b24 <HAL_GPIO_Init+0x348>)
|
|
80029f6: 4293 cmp r3, r2
|
|
80029f8: d007 beq.n 8002a0a <HAL_GPIO_Init+0x22e>
|
|
80029fa: 687b ldr r3, [r7, #4]
|
|
80029fc: 4a4a ldr r2, [pc, #296] @ (8002b28 <HAL_GPIO_Init+0x34c>)
|
|
80029fe: 4293 cmp r3, r2
|
|
8002a00: d101 bne.n 8002a06 <HAL_GPIO_Init+0x22a>
|
|
8002a02: 2306 movs r3, #6
|
|
8002a04: e00c b.n 8002a20 <HAL_GPIO_Init+0x244>
|
|
8002a06: 2307 movs r3, #7
|
|
8002a08: e00a b.n 8002a20 <HAL_GPIO_Init+0x244>
|
|
8002a0a: 2305 movs r3, #5
|
|
8002a0c: e008 b.n 8002a20 <HAL_GPIO_Init+0x244>
|
|
8002a0e: 2304 movs r3, #4
|
|
8002a10: e006 b.n 8002a20 <HAL_GPIO_Init+0x244>
|
|
8002a12: 2303 movs r3, #3
|
|
8002a14: e004 b.n 8002a20 <HAL_GPIO_Init+0x244>
|
|
8002a16: 2302 movs r3, #2
|
|
8002a18: e002 b.n 8002a20 <HAL_GPIO_Init+0x244>
|
|
8002a1a: 2301 movs r3, #1
|
|
8002a1c: e000 b.n 8002a20 <HAL_GPIO_Init+0x244>
|
|
8002a1e: 2300 movs r3, #0
|
|
8002a20: 697a ldr r2, [r7, #20]
|
|
8002a22: f002 0203 and.w r2, r2, #3
|
|
8002a26: 0092 lsls r2, r2, #2
|
|
8002a28: 4093 lsls r3, r2
|
|
8002a2a: 693a ldr r2, [r7, #16]
|
|
8002a2c: 4313 orrs r3, r2
|
|
8002a2e: 613b str r3, [r7, #16]
|
|
SYSCFG->EXTICR[position >> 2u] = temp;
|
|
8002a30: 4937 ldr r1, [pc, #220] @ (8002b10 <HAL_GPIO_Init+0x334>)
|
|
8002a32: 697b ldr r3, [r7, #20]
|
|
8002a34: 089b lsrs r3, r3, #2
|
|
8002a36: 3302 adds r3, #2
|
|
8002a38: 693a ldr r2, [r7, #16]
|
|
8002a3a: f841 2023 str.w r2, [r1, r3, lsl #2]
|
|
|
|
/* Clear Rising Falling edge configuration */
|
|
temp = EXTI->RTSR1;
|
|
8002a3e: 4b3b ldr r3, [pc, #236] @ (8002b2c <HAL_GPIO_Init+0x350>)
|
|
8002a40: 689b ldr r3, [r3, #8]
|
|
8002a42: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8002a44: 68fb ldr r3, [r7, #12]
|
|
8002a46: 43db mvns r3, r3
|
|
8002a48: 693a ldr r2, [r7, #16]
|
|
8002a4a: 4013 ands r3, r2
|
|
8002a4c: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u)
|
|
8002a4e: 683b ldr r3, [r7, #0]
|
|
8002a50: 685b ldr r3, [r3, #4]
|
|
8002a52: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
8002a56: 2b00 cmp r3, #0
|
|
8002a58: d003 beq.n 8002a62 <HAL_GPIO_Init+0x286>
|
|
{
|
|
temp |= iocurrent;
|
|
8002a5a: 693a ldr r2, [r7, #16]
|
|
8002a5c: 68fb ldr r3, [r7, #12]
|
|
8002a5e: 4313 orrs r3, r2
|
|
8002a60: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->RTSR1 = temp;
|
|
8002a62: 4a32 ldr r2, [pc, #200] @ (8002b2c <HAL_GPIO_Init+0x350>)
|
|
8002a64: 693b ldr r3, [r7, #16]
|
|
8002a66: 6093 str r3, [r2, #8]
|
|
|
|
temp = EXTI->FTSR1;
|
|
8002a68: 4b30 ldr r3, [pc, #192] @ (8002b2c <HAL_GPIO_Init+0x350>)
|
|
8002a6a: 68db ldr r3, [r3, #12]
|
|
8002a6c: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8002a6e: 68fb ldr r3, [r7, #12]
|
|
8002a70: 43db mvns r3, r3
|
|
8002a72: 693a ldr r2, [r7, #16]
|
|
8002a74: 4013 ands r3, r2
|
|
8002a76: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u)
|
|
8002a78: 683b ldr r3, [r7, #0]
|
|
8002a7a: 685b ldr r3, [r3, #4]
|
|
8002a7c: f403 1300 and.w r3, r3, #2097152 @ 0x200000
|
|
8002a80: 2b00 cmp r3, #0
|
|
8002a82: d003 beq.n 8002a8c <HAL_GPIO_Init+0x2b0>
|
|
{
|
|
temp |= iocurrent;
|
|
8002a84: 693a ldr r2, [r7, #16]
|
|
8002a86: 68fb ldr r3, [r7, #12]
|
|
8002a88: 4313 orrs r3, r2
|
|
8002a8a: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->FTSR1 = temp;
|
|
8002a8c: 4a27 ldr r2, [pc, #156] @ (8002b2c <HAL_GPIO_Init+0x350>)
|
|
8002a8e: 693b ldr r3, [r7, #16]
|
|
8002a90: 60d3 str r3, [r2, #12]
|
|
|
|
/* Clear EXTI line configuration */
|
|
temp = EXTI->EMR1;
|
|
8002a92: 4b26 ldr r3, [pc, #152] @ (8002b2c <HAL_GPIO_Init+0x350>)
|
|
8002a94: 685b ldr r3, [r3, #4]
|
|
8002a96: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8002a98: 68fb ldr r3, [r7, #12]
|
|
8002a9a: 43db mvns r3, r3
|
|
8002a9c: 693a ldr r2, [r7, #16]
|
|
8002a9e: 4013 ands r3, r2
|
|
8002aa0: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u)
|
|
8002aa2: 683b ldr r3, [r7, #0]
|
|
8002aa4: 685b ldr r3, [r3, #4]
|
|
8002aa6: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8002aaa: 2b00 cmp r3, #0
|
|
8002aac: d003 beq.n 8002ab6 <HAL_GPIO_Init+0x2da>
|
|
{
|
|
temp |= iocurrent;
|
|
8002aae: 693a ldr r2, [r7, #16]
|
|
8002ab0: 68fb ldr r3, [r7, #12]
|
|
8002ab2: 4313 orrs r3, r2
|
|
8002ab4: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->EMR1 = temp;
|
|
8002ab6: 4a1d ldr r2, [pc, #116] @ (8002b2c <HAL_GPIO_Init+0x350>)
|
|
8002ab8: 693b ldr r3, [r7, #16]
|
|
8002aba: 6053 str r3, [r2, #4]
|
|
|
|
temp = EXTI->IMR1;
|
|
8002abc: 4b1b ldr r3, [pc, #108] @ (8002b2c <HAL_GPIO_Init+0x350>)
|
|
8002abe: 681b ldr r3, [r3, #0]
|
|
8002ac0: 613b str r3, [r7, #16]
|
|
temp &= ~(iocurrent);
|
|
8002ac2: 68fb ldr r3, [r7, #12]
|
|
8002ac4: 43db mvns r3, r3
|
|
8002ac6: 693a ldr r2, [r7, #16]
|
|
8002ac8: 4013 ands r3, r2
|
|
8002aca: 613b str r3, [r7, #16]
|
|
if ((GPIO_Init->Mode & EXTI_IT) != 0x00u)
|
|
8002acc: 683b ldr r3, [r7, #0]
|
|
8002ace: 685b ldr r3, [r3, #4]
|
|
8002ad0: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8002ad4: 2b00 cmp r3, #0
|
|
8002ad6: d003 beq.n 8002ae0 <HAL_GPIO_Init+0x304>
|
|
{
|
|
temp |= iocurrent;
|
|
8002ad8: 693a ldr r2, [r7, #16]
|
|
8002ada: 68fb ldr r3, [r7, #12]
|
|
8002adc: 4313 orrs r3, r2
|
|
8002ade: 613b str r3, [r7, #16]
|
|
}
|
|
EXTI->IMR1 = temp;
|
|
8002ae0: 4a12 ldr r2, [pc, #72] @ (8002b2c <HAL_GPIO_Init+0x350>)
|
|
8002ae2: 693b ldr r3, [r7, #16]
|
|
8002ae4: 6013 str r3, [r2, #0]
|
|
}
|
|
}
|
|
|
|
position++;
|
|
8002ae6: 697b ldr r3, [r7, #20]
|
|
8002ae8: 3301 adds r3, #1
|
|
8002aea: 617b str r3, [r7, #20]
|
|
while (((GPIO_Init->Pin) >> position) != 0x00u)
|
|
8002aec: 683b ldr r3, [r7, #0]
|
|
8002aee: 681a ldr r2, [r3, #0]
|
|
8002af0: 697b ldr r3, [r7, #20]
|
|
8002af2: fa22 f303 lsr.w r3, r2, r3
|
|
8002af6: 2b00 cmp r3, #0
|
|
8002af8: f47f ae78 bne.w 80027ec <HAL_GPIO_Init+0x10>
|
|
}
|
|
}
|
|
8002afc: bf00 nop
|
|
8002afe: bf00 nop
|
|
8002b00: 371c adds r7, #28
|
|
8002b02: 46bd mov sp, r7
|
|
8002b04: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002b08: 4770 bx lr
|
|
8002b0a: bf00 nop
|
|
8002b0c: 40021000 .word 0x40021000
|
|
8002b10: 40010000 .word 0x40010000
|
|
8002b14: 48000400 .word 0x48000400
|
|
8002b18: 48000800 .word 0x48000800
|
|
8002b1c: 48000c00 .word 0x48000c00
|
|
8002b20: 48001000 .word 0x48001000
|
|
8002b24: 48001400 .word 0x48001400
|
|
8002b28: 48001800 .word 0x48001800
|
|
8002b2c: 40010400 .word 0x40010400
|
|
|
|
08002b30 <HAL_GPIO_WritePin>:
|
|
* @arg GPIO_PIN_RESET: to clear the port pin
|
|
* @arg GPIO_PIN_SET: to set the port pin
|
|
* @retval None
|
|
*/
|
|
void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
|
|
{
|
|
8002b30: b480 push {r7}
|
|
8002b32: b083 sub sp, #12
|
|
8002b34: af00 add r7, sp, #0
|
|
8002b36: 6078 str r0, [r7, #4]
|
|
8002b38: 460b mov r3, r1
|
|
8002b3a: 807b strh r3, [r7, #2]
|
|
8002b3c: 4613 mov r3, r2
|
|
8002b3e: 707b strb r3, [r7, #1]
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
|
|
|
if(PinState != GPIO_PIN_RESET)
|
|
8002b40: 787b ldrb r3, [r7, #1]
|
|
8002b42: 2b00 cmp r3, #0
|
|
8002b44: d003 beq.n 8002b4e <HAL_GPIO_WritePin+0x1e>
|
|
{
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin;
|
|
8002b46: 887a ldrh r2, [r7, #2]
|
|
8002b48: 687b ldr r3, [r7, #4]
|
|
8002b4a: 619a str r2, [r3, #24]
|
|
}
|
|
else
|
|
{
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
|
}
|
|
}
|
|
8002b4c: e002 b.n 8002b54 <HAL_GPIO_WritePin+0x24>
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
|
8002b4e: 887a ldrh r2, [r7, #2]
|
|
8002b50: 687b ldr r3, [r7, #4]
|
|
8002b52: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
8002b54: bf00 nop
|
|
8002b56: 370c adds r7, #12
|
|
8002b58: 46bd mov sp, r7
|
|
8002b5a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8002b5e: 4770 bx lr
|
|
|
|
08002b60 <HAL_I2C_Init>:
|
|
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
|
* the configuration information for the specified I2C.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
8002b60: b580 push {r7, lr}
|
|
8002b62: b082 sub sp, #8
|
|
8002b64: af00 add r7, sp, #0
|
|
8002b66: 6078 str r0, [r7, #4]
|
|
/* Check the I2C handle allocation */
|
|
if (hi2c == NULL)
|
|
8002b68: 687b ldr r3, [r7, #4]
|
|
8002b6a: 2b00 cmp r3, #0
|
|
8002b6c: d101 bne.n 8002b72 <HAL_I2C_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8002b6e: 2301 movs r3, #1
|
|
8002b70: e08d b.n 8002c8e <HAL_I2C_Init+0x12e>
|
|
assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
|
|
assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
|
|
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
|
|
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_RESET)
|
|
8002b72: 687b ldr r3, [r7, #4]
|
|
8002b74: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8002b78: b2db uxtb r3, r3
|
|
8002b7a: 2b00 cmp r3, #0
|
|
8002b7c: d106 bne.n 8002b8c <HAL_I2C_Init+0x2c>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
hi2c->Lock = HAL_UNLOCKED;
|
|
8002b7e: 687b ldr r3, [r7, #4]
|
|
8002b80: 2200 movs r2, #0
|
|
8002b82: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
|
|
hi2c->MspInitCallback(hi2c);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
|
|
HAL_I2C_MspInit(hi2c);
|
|
8002b86: 6878 ldr r0, [r7, #4]
|
|
8002b88: f7ff fa00 bl 8001f8c <HAL_I2C_MspInit>
|
|
#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
8002b8c: 687b ldr r3, [r7, #4]
|
|
8002b8e: 2224 movs r2, #36 @ 0x24
|
|
8002b90: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
8002b94: 687b ldr r3, [r7, #4]
|
|
8002b96: 681b ldr r3, [r3, #0]
|
|
8002b98: 681a ldr r2, [r3, #0]
|
|
8002b9a: 687b ldr r3, [r7, #4]
|
|
8002b9c: 681b ldr r3, [r3, #0]
|
|
8002b9e: f022 0201 bic.w r2, r2, #1
|
|
8002ba2: 601a str r2, [r3, #0]
|
|
|
|
/*---------------------------- I2Cx TIMINGR Configuration ------------------*/
|
|
/* Configure I2Cx: Frequency range */
|
|
hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
|
|
8002ba4: 687b ldr r3, [r7, #4]
|
|
8002ba6: 685a ldr r2, [r3, #4]
|
|
8002ba8: 687b ldr r3, [r7, #4]
|
|
8002baa: 681b ldr r3, [r3, #0]
|
|
8002bac: f022 6270 bic.w r2, r2, #251658240 @ 0xf000000
|
|
8002bb0: 611a str r2, [r3, #16]
|
|
|
|
/*---------------------------- I2Cx OAR1 Configuration ---------------------*/
|
|
/* Disable Own Address1 before set the Own Address1 configuration */
|
|
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
|
|
8002bb2: 687b ldr r3, [r7, #4]
|
|
8002bb4: 681b ldr r3, [r3, #0]
|
|
8002bb6: 689a ldr r2, [r3, #8]
|
|
8002bb8: 687b ldr r3, [r7, #4]
|
|
8002bba: 681b ldr r3, [r3, #0]
|
|
8002bbc: f422 4200 bic.w r2, r2, #32768 @ 0x8000
|
|
8002bc0: 609a str r2, [r3, #8]
|
|
|
|
/* Configure I2Cx: Own Address1 and ack own address1 mode */
|
|
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
|
|
8002bc2: 687b ldr r3, [r7, #4]
|
|
8002bc4: 68db ldr r3, [r3, #12]
|
|
8002bc6: 2b01 cmp r3, #1
|
|
8002bc8: d107 bne.n 8002bda <HAL_I2C_Init+0x7a>
|
|
{
|
|
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
|
|
8002bca: 687b ldr r3, [r7, #4]
|
|
8002bcc: 689a ldr r2, [r3, #8]
|
|
8002bce: 687b ldr r3, [r7, #4]
|
|
8002bd0: 681b ldr r3, [r3, #0]
|
|
8002bd2: f442 4200 orr.w r2, r2, #32768 @ 0x8000
|
|
8002bd6: 609a str r2, [r3, #8]
|
|
8002bd8: e006 b.n 8002be8 <HAL_I2C_Init+0x88>
|
|
}
|
|
else /* I2C_ADDRESSINGMODE_10BIT */
|
|
{
|
|
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
|
|
8002bda: 687b ldr r3, [r7, #4]
|
|
8002bdc: 689a ldr r2, [r3, #8]
|
|
8002bde: 687b ldr r3, [r7, #4]
|
|
8002be0: 681b ldr r3, [r3, #0]
|
|
8002be2: f442 4204 orr.w r2, r2, #33792 @ 0x8400
|
|
8002be6: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
|
|
/* Configure I2Cx: Addressing Master mode */
|
|
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
|
|
8002be8: 687b ldr r3, [r7, #4]
|
|
8002bea: 68db ldr r3, [r3, #12]
|
|
8002bec: 2b02 cmp r3, #2
|
|
8002bee: d108 bne.n 8002c02 <HAL_I2C_Init+0xa2>
|
|
{
|
|
SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
|
|
8002bf0: 687b ldr r3, [r7, #4]
|
|
8002bf2: 681b ldr r3, [r3, #0]
|
|
8002bf4: 685a ldr r2, [r3, #4]
|
|
8002bf6: 687b ldr r3, [r7, #4]
|
|
8002bf8: 681b ldr r3, [r3, #0]
|
|
8002bfa: f442 6200 orr.w r2, r2, #2048 @ 0x800
|
|
8002bfe: 605a str r2, [r3, #4]
|
|
8002c00: e007 b.n 8002c12 <HAL_I2C_Init+0xb2>
|
|
}
|
|
else
|
|
{
|
|
/* Clear the I2C ADD10 bit */
|
|
CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
|
|
8002c02: 687b ldr r3, [r7, #4]
|
|
8002c04: 681b ldr r3, [r3, #0]
|
|
8002c06: 685a ldr r2, [r3, #4]
|
|
8002c08: 687b ldr r3, [r7, #4]
|
|
8002c0a: 681b ldr r3, [r3, #0]
|
|
8002c0c: f422 6200 bic.w r2, r2, #2048 @ 0x800
|
|
8002c10: 605a str r2, [r3, #4]
|
|
}
|
|
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
|
|
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
|
|
8002c12: 687b ldr r3, [r7, #4]
|
|
8002c14: 681b ldr r3, [r3, #0]
|
|
8002c16: 685b ldr r3, [r3, #4]
|
|
8002c18: 687a ldr r2, [r7, #4]
|
|
8002c1a: 6812 ldr r2, [r2, #0]
|
|
8002c1c: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
|
|
8002c20: f443 4300 orr.w r3, r3, #32768 @ 0x8000
|
|
8002c24: 6053 str r3, [r2, #4]
|
|
|
|
/*---------------------------- I2Cx OAR2 Configuration ---------------------*/
|
|
/* Disable Own Address2 before set the Own Address2 configuration */
|
|
hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
|
|
8002c26: 687b ldr r3, [r7, #4]
|
|
8002c28: 681b ldr r3, [r3, #0]
|
|
8002c2a: 68da ldr r2, [r3, #12]
|
|
8002c2c: 687b ldr r3, [r7, #4]
|
|
8002c2e: 681b ldr r3, [r3, #0]
|
|
8002c30: f422 4200 bic.w r2, r2, #32768 @ 0x8000
|
|
8002c34: 60da str r2, [r3, #12]
|
|
|
|
/* Configure I2Cx: Dual mode and Own Address2 */
|
|
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
|
|
8002c36: 687b ldr r3, [r7, #4]
|
|
8002c38: 691a ldr r2, [r3, #16]
|
|
8002c3a: 687b ldr r3, [r7, #4]
|
|
8002c3c: 695b ldr r3, [r3, #20]
|
|
8002c3e: ea42 0103 orr.w r1, r2, r3
|
|
(hi2c->Init.OwnAddress2Masks << 8));
|
|
8002c42: 687b ldr r3, [r7, #4]
|
|
8002c44: 699b ldr r3, [r3, #24]
|
|
8002c46: 021a lsls r2, r3, #8
|
|
hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \
|
|
8002c48: 687b ldr r3, [r7, #4]
|
|
8002c4a: 681b ldr r3, [r3, #0]
|
|
8002c4c: 430a orrs r2, r1
|
|
8002c4e: 60da str r2, [r3, #12]
|
|
|
|
/*---------------------------- I2Cx CR1 Configuration ----------------------*/
|
|
/* Configure I2Cx: Generalcall and NoStretch mode */
|
|
hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
|
|
8002c50: 687b ldr r3, [r7, #4]
|
|
8002c52: 69d9 ldr r1, [r3, #28]
|
|
8002c54: 687b ldr r3, [r7, #4]
|
|
8002c56: 6a1a ldr r2, [r3, #32]
|
|
8002c58: 687b ldr r3, [r7, #4]
|
|
8002c5a: 681b ldr r3, [r3, #0]
|
|
8002c5c: 430a orrs r2, r1
|
|
8002c5e: 601a str r2, [r3, #0]
|
|
|
|
/* Enable the selected I2C peripheral */
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
8002c60: 687b ldr r3, [r7, #4]
|
|
8002c62: 681b ldr r3, [r3, #0]
|
|
8002c64: 681a ldr r2, [r3, #0]
|
|
8002c66: 687b ldr r3, [r7, #4]
|
|
8002c68: 681b ldr r3, [r3, #0]
|
|
8002c6a: f042 0201 orr.w r2, r2, #1
|
|
8002c6e: 601a str r2, [r3, #0]
|
|
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
8002c70: 687b ldr r3, [r7, #4]
|
|
8002c72: 2200 movs r2, #0
|
|
8002c74: 645a str r2, [r3, #68] @ 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8002c76: 687b ldr r3, [r7, #4]
|
|
8002c78: 2220 movs r2, #32
|
|
8002c7a: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->PreviousState = I2C_STATE_NONE;
|
|
8002c7e: 687b ldr r3, [r7, #4]
|
|
8002c80: 2200 movs r2, #0
|
|
8002c82: 631a str r2, [r3, #48] @ 0x30
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8002c84: 687b ldr r3, [r7, #4]
|
|
8002c86: 2200 movs r2, #0
|
|
8002c88: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
return HAL_OK;
|
|
8002c8c: 2300 movs r3, #0
|
|
}
|
|
8002c8e: 4618 mov r0, r3
|
|
8002c90: 3708 adds r7, #8
|
|
8002c92: 46bd mov sp, r7
|
|
8002c94: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08002c98 <HAL_I2C_Mem_Write>:
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
|
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
{
|
|
8002c98: b580 push {r7, lr}
|
|
8002c9a: b088 sub sp, #32
|
|
8002c9c: af02 add r7, sp, #8
|
|
8002c9e: 60f8 str r0, [r7, #12]
|
|
8002ca0: 4608 mov r0, r1
|
|
8002ca2: 4611 mov r1, r2
|
|
8002ca4: 461a mov r2, r3
|
|
8002ca6: 4603 mov r3, r0
|
|
8002ca8: 817b strh r3, [r7, #10]
|
|
8002caa: 460b mov r3, r1
|
|
8002cac: 813b strh r3, [r7, #8]
|
|
8002cae: 4613 mov r3, r2
|
|
8002cb0: 80fb strh r3, [r7, #6]
|
|
uint32_t tickstart;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
8002cb2: 68fb ldr r3, [r7, #12]
|
|
8002cb4: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8002cb8: b2db uxtb r3, r3
|
|
8002cba: 2b20 cmp r3, #32
|
|
8002cbc: f040 80f9 bne.w 8002eb2 <HAL_I2C_Mem_Write+0x21a>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8002cc0: 6a3b ldr r3, [r7, #32]
|
|
8002cc2: 2b00 cmp r3, #0
|
|
8002cc4: d002 beq.n 8002ccc <HAL_I2C_Mem_Write+0x34>
|
|
8002cc6: 8cbb ldrh r3, [r7, #36] @ 0x24
|
|
8002cc8: 2b00 cmp r3, #0
|
|
8002cca: d105 bne.n 8002cd8 <HAL_I2C_Mem_Write+0x40>
|
|
{
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
|
|
8002ccc: 68fb ldr r3, [r7, #12]
|
|
8002cce: f44f 7200 mov.w r2, #512 @ 0x200
|
|
8002cd2: 645a str r2, [r3, #68] @ 0x44
|
|
return HAL_ERROR;
|
|
8002cd4: 2301 movs r3, #1
|
|
8002cd6: e0ed b.n 8002eb4 <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
8002cd8: 68fb ldr r3, [r7, #12]
|
|
8002cda: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
8002cde: 2b01 cmp r3, #1
|
|
8002ce0: d101 bne.n 8002ce6 <HAL_I2C_Mem_Write+0x4e>
|
|
8002ce2: 2302 movs r3, #2
|
|
8002ce4: e0e6 b.n 8002eb4 <HAL_I2C_Mem_Write+0x21c>
|
|
8002ce6: 68fb ldr r3, [r7, #12]
|
|
8002ce8: 2201 movs r2, #1
|
|
8002cea: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Init tickstart for timeout management*/
|
|
tickstart = HAL_GetTick();
|
|
8002cee: f7ff fbb5 bl 800245c <HAL_GetTick>
|
|
8002cf2: 6178 str r0, [r7, #20]
|
|
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
|
|
8002cf4: 697b ldr r3, [r7, #20]
|
|
8002cf6: 9300 str r3, [sp, #0]
|
|
8002cf8: 2319 movs r3, #25
|
|
8002cfa: 2201 movs r2, #1
|
|
8002cfc: f44f 4100 mov.w r1, #32768 @ 0x8000
|
|
8002d00: 68f8 ldr r0, [r7, #12]
|
|
8002d02: f000 fac3 bl 800328c <I2C_WaitOnFlagUntilTimeout>
|
|
8002d06: 4603 mov r3, r0
|
|
8002d08: 2b00 cmp r3, #0
|
|
8002d0a: d001 beq.n 8002d10 <HAL_I2C_Mem_Write+0x78>
|
|
{
|
|
return HAL_ERROR;
|
|
8002d0c: 2301 movs r3, #1
|
|
8002d0e: e0d1 b.n 8002eb4 <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY_TX;
|
|
8002d10: 68fb ldr r3, [r7, #12]
|
|
8002d12: 2221 movs r2, #33 @ 0x21
|
|
8002d14: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_MEM;
|
|
8002d18: 68fb ldr r3, [r7, #12]
|
|
8002d1a: 2240 movs r2, #64 @ 0x40
|
|
8002d1c: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
8002d20: 68fb ldr r3, [r7, #12]
|
|
8002d22: 2200 movs r2, #0
|
|
8002d24: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* Prepare transfer parameters */
|
|
hi2c->pBuffPtr = pData;
|
|
8002d26: 68fb ldr r3, [r7, #12]
|
|
8002d28: 6a3a ldr r2, [r7, #32]
|
|
8002d2a: 625a str r2, [r3, #36] @ 0x24
|
|
hi2c->XferCount = Size;
|
|
8002d2c: 68fb ldr r3, [r7, #12]
|
|
8002d2e: 8cba ldrh r2, [r7, #36] @ 0x24
|
|
8002d30: 855a strh r2, [r3, #42] @ 0x2a
|
|
hi2c->XferISR = NULL;
|
|
8002d32: 68fb ldr r3, [r7, #12]
|
|
8002d34: 2200 movs r2, #0
|
|
8002d36: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Send Slave Address and Memory Address */
|
|
if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
|
|
8002d38: 88f8 ldrh r0, [r7, #6]
|
|
8002d3a: 893a ldrh r2, [r7, #8]
|
|
8002d3c: 8979 ldrh r1, [r7, #10]
|
|
8002d3e: 697b ldr r3, [r7, #20]
|
|
8002d40: 9301 str r3, [sp, #4]
|
|
8002d42: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8002d44: 9300 str r3, [sp, #0]
|
|
8002d46: 4603 mov r3, r0
|
|
8002d48: 68f8 ldr r0, [r7, #12]
|
|
8002d4a: f000 f9d3 bl 80030f4 <I2C_RequestMemoryWrite>
|
|
8002d4e: 4603 mov r3, r0
|
|
8002d50: 2b00 cmp r3, #0
|
|
8002d52: d005 beq.n 8002d60 <HAL_I2C_Mem_Write+0xc8>
|
|
{
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8002d54: 68fb ldr r3, [r7, #12]
|
|
8002d56: 2200 movs r2, #0
|
|
8002d58: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
return HAL_ERROR;
|
|
8002d5c: 2301 movs r3, #1
|
|
8002d5e: e0a9 b.n 8002eb4 <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
|
|
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
8002d60: 68fb ldr r3, [r7, #12]
|
|
8002d62: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8002d64: b29b uxth r3, r3
|
|
8002d66: 2bff cmp r3, #255 @ 0xff
|
|
8002d68: d90e bls.n 8002d88 <HAL_I2C_Mem_Write+0xf0>
|
|
{
|
|
hi2c->XferSize = MAX_NBYTE_SIZE;
|
|
8002d6a: 68fb ldr r3, [r7, #12]
|
|
8002d6c: 22ff movs r2, #255 @ 0xff
|
|
8002d6e: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
|
|
8002d70: 68fb ldr r3, [r7, #12]
|
|
8002d72: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8002d74: b2da uxtb r2, r3
|
|
8002d76: 8979 ldrh r1, [r7, #10]
|
|
8002d78: 2300 movs r3, #0
|
|
8002d7a: 9300 str r3, [sp, #0]
|
|
8002d7c: f04f 7380 mov.w r3, #16777216 @ 0x1000000
|
|
8002d80: 68f8 ldr r0, [r7, #12]
|
|
8002d82: f000 fc47 bl 8003614 <I2C_TransferConfig>
|
|
8002d86: e00f b.n 8002da8 <HAL_I2C_Mem_Write+0x110>
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
8002d88: 68fb ldr r3, [r7, #12]
|
|
8002d8a: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8002d8c: b29a uxth r2, r3
|
|
8002d8e: 68fb ldr r3, [r7, #12]
|
|
8002d90: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
|
|
8002d92: 68fb ldr r3, [r7, #12]
|
|
8002d94: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8002d96: b2da uxtb r2, r3
|
|
8002d98: 8979 ldrh r1, [r7, #10]
|
|
8002d9a: 2300 movs r3, #0
|
|
8002d9c: 9300 str r3, [sp, #0]
|
|
8002d9e: f04f 7300 mov.w r3, #33554432 @ 0x2000000
|
|
8002da2: 68f8 ldr r0, [r7, #12]
|
|
8002da4: f000 fc36 bl 8003614 <I2C_TransferConfig>
|
|
}
|
|
|
|
do
|
|
{
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
|
|
8002da8: 697a ldr r2, [r7, #20]
|
|
8002daa: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
8002dac: 68f8 ldr r0, [r7, #12]
|
|
8002dae: f000 fac6 bl 800333e <I2C_WaitOnTXISFlagUntilTimeout>
|
|
8002db2: 4603 mov r3, r0
|
|
8002db4: 2b00 cmp r3, #0
|
|
8002db6: d001 beq.n 8002dbc <HAL_I2C_Mem_Write+0x124>
|
|
{
|
|
return HAL_ERROR;
|
|
8002db8: 2301 movs r3, #1
|
|
8002dba: e07b b.n 8002eb4 <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
|
|
/* Write data to TXDR */
|
|
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
|
|
8002dbc: 68fb ldr r3, [r7, #12]
|
|
8002dbe: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8002dc0: 781a ldrb r2, [r3, #0]
|
|
8002dc2: 68fb ldr r3, [r7, #12]
|
|
8002dc4: 681b ldr r3, [r3, #0]
|
|
8002dc6: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
/* Increment Buffer pointer */
|
|
hi2c->pBuffPtr++;
|
|
8002dc8: 68fb ldr r3, [r7, #12]
|
|
8002dca: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8002dcc: 1c5a adds r2, r3, #1
|
|
8002dce: 68fb ldr r3, [r7, #12]
|
|
8002dd0: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
hi2c->XferCount--;
|
|
8002dd2: 68fb ldr r3, [r7, #12]
|
|
8002dd4: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8002dd6: b29b uxth r3, r3
|
|
8002dd8: 3b01 subs r3, #1
|
|
8002dda: b29a uxth r2, r3
|
|
8002ddc: 68fb ldr r3, [r7, #12]
|
|
8002dde: 855a strh r2, [r3, #42] @ 0x2a
|
|
hi2c->XferSize--;
|
|
8002de0: 68fb ldr r3, [r7, #12]
|
|
8002de2: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8002de4: 3b01 subs r3, #1
|
|
8002de6: b29a uxth r2, r3
|
|
8002de8: 68fb ldr r3, [r7, #12]
|
|
8002dea: 851a strh r2, [r3, #40] @ 0x28
|
|
|
|
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
|
|
8002dec: 68fb ldr r3, [r7, #12]
|
|
8002dee: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8002df0: b29b uxth r3, r3
|
|
8002df2: 2b00 cmp r3, #0
|
|
8002df4: d034 beq.n 8002e60 <HAL_I2C_Mem_Write+0x1c8>
|
|
8002df6: 68fb ldr r3, [r7, #12]
|
|
8002df8: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8002dfa: 2b00 cmp r3, #0
|
|
8002dfc: d130 bne.n 8002e60 <HAL_I2C_Mem_Write+0x1c8>
|
|
{
|
|
/* Wait until TCR flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
|
|
8002dfe: 697b ldr r3, [r7, #20]
|
|
8002e00: 9300 str r3, [sp, #0]
|
|
8002e02: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8002e04: 2200 movs r2, #0
|
|
8002e06: 2180 movs r1, #128 @ 0x80
|
|
8002e08: 68f8 ldr r0, [r7, #12]
|
|
8002e0a: f000 fa3f bl 800328c <I2C_WaitOnFlagUntilTimeout>
|
|
8002e0e: 4603 mov r3, r0
|
|
8002e10: 2b00 cmp r3, #0
|
|
8002e12: d001 beq.n 8002e18 <HAL_I2C_Mem_Write+0x180>
|
|
{
|
|
return HAL_ERROR;
|
|
8002e14: 2301 movs r3, #1
|
|
8002e16: e04d b.n 8002eb4 <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
8002e18: 68fb ldr r3, [r7, #12]
|
|
8002e1a: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8002e1c: b29b uxth r3, r3
|
|
8002e1e: 2bff cmp r3, #255 @ 0xff
|
|
8002e20: d90e bls.n 8002e40 <HAL_I2C_Mem_Write+0x1a8>
|
|
{
|
|
hi2c->XferSize = MAX_NBYTE_SIZE;
|
|
8002e22: 68fb ldr r3, [r7, #12]
|
|
8002e24: 22ff movs r2, #255 @ 0xff
|
|
8002e26: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
|
|
8002e28: 68fb ldr r3, [r7, #12]
|
|
8002e2a: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8002e2c: b2da uxtb r2, r3
|
|
8002e2e: 8979 ldrh r1, [r7, #10]
|
|
8002e30: 2300 movs r3, #0
|
|
8002e32: 9300 str r3, [sp, #0]
|
|
8002e34: f04f 7380 mov.w r3, #16777216 @ 0x1000000
|
|
8002e38: 68f8 ldr r0, [r7, #12]
|
|
8002e3a: f000 fbeb bl 8003614 <I2C_TransferConfig>
|
|
8002e3e: e00f b.n 8002e60 <HAL_I2C_Mem_Write+0x1c8>
|
|
I2C_NO_STARTSTOP);
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
8002e40: 68fb ldr r3, [r7, #12]
|
|
8002e42: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8002e44: b29a uxth r2, r3
|
|
8002e46: 68fb ldr r3, [r7, #12]
|
|
8002e48: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
|
|
8002e4a: 68fb ldr r3, [r7, #12]
|
|
8002e4c: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8002e4e: b2da uxtb r2, r3
|
|
8002e50: 8979 ldrh r1, [r7, #10]
|
|
8002e52: 2300 movs r3, #0
|
|
8002e54: 9300 str r3, [sp, #0]
|
|
8002e56: f04f 7300 mov.w r3, #33554432 @ 0x2000000
|
|
8002e5a: 68f8 ldr r0, [r7, #12]
|
|
8002e5c: f000 fbda bl 8003614 <I2C_TransferConfig>
|
|
I2C_NO_STARTSTOP);
|
|
}
|
|
}
|
|
|
|
} while (hi2c->XferCount > 0U);
|
|
8002e60: 68fb ldr r3, [r7, #12]
|
|
8002e62: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8002e64: b29b uxth r3, r3
|
|
8002e66: 2b00 cmp r3, #0
|
|
8002e68: d19e bne.n 8002da8 <HAL_I2C_Mem_Write+0x110>
|
|
|
|
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
|
|
/* Wait until STOPF flag is reset */
|
|
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
|
|
8002e6a: 697a ldr r2, [r7, #20]
|
|
8002e6c: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
8002e6e: 68f8 ldr r0, [r7, #12]
|
|
8002e70: f000 faac bl 80033cc <I2C_WaitOnSTOPFlagUntilTimeout>
|
|
8002e74: 4603 mov r3, r0
|
|
8002e76: 2b00 cmp r3, #0
|
|
8002e78: d001 beq.n 8002e7e <HAL_I2C_Mem_Write+0x1e6>
|
|
{
|
|
return HAL_ERROR;
|
|
8002e7a: 2301 movs r3, #1
|
|
8002e7c: e01a b.n 8002eb4 <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
|
|
/* Clear STOP Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
|
8002e7e: 68fb ldr r3, [r7, #12]
|
|
8002e80: 681b ldr r3, [r3, #0]
|
|
8002e82: 2220 movs r2, #32
|
|
8002e84: 61da str r2, [r3, #28]
|
|
|
|
/* Clear Configuration Register 2 */
|
|
I2C_RESET_CR2(hi2c);
|
|
8002e86: 68fb ldr r3, [r7, #12]
|
|
8002e88: 681b ldr r3, [r3, #0]
|
|
8002e8a: 6859 ldr r1, [r3, #4]
|
|
8002e8c: 68fb ldr r3, [r7, #12]
|
|
8002e8e: 681a ldr r2, [r3, #0]
|
|
8002e90: 4b0a ldr r3, [pc, #40] @ (8002ebc <HAL_I2C_Mem_Write+0x224>)
|
|
8002e92: 400b ands r3, r1
|
|
8002e94: 6053 str r3, [r2, #4]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8002e96: 68fb ldr r3, [r7, #12]
|
|
8002e98: 2220 movs r2, #32
|
|
8002e9a: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8002e9e: 68fb ldr r3, [r7, #12]
|
|
8002ea0: 2200 movs r2, #0
|
|
8002ea2: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8002ea6: 68fb ldr r3, [r7, #12]
|
|
8002ea8: 2200 movs r2, #0
|
|
8002eaa: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_OK;
|
|
8002eae: 2300 movs r3, #0
|
|
8002eb0: e000 b.n 8002eb4 <HAL_I2C_Mem_Write+0x21c>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8002eb2: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8002eb4: 4618 mov r0, r3
|
|
8002eb6: 3718 adds r7, #24
|
|
8002eb8: 46bd mov sp, r7
|
|
8002eba: bd80 pop {r7, pc}
|
|
8002ebc: fe00e800 .word 0xfe00e800
|
|
|
|
08002ec0 <HAL_I2C_Mem_Read>:
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress,
|
|
uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
{
|
|
8002ec0: b580 push {r7, lr}
|
|
8002ec2: b088 sub sp, #32
|
|
8002ec4: af02 add r7, sp, #8
|
|
8002ec6: 60f8 str r0, [r7, #12]
|
|
8002ec8: 4608 mov r0, r1
|
|
8002eca: 4611 mov r1, r2
|
|
8002ecc: 461a mov r2, r3
|
|
8002ece: 4603 mov r3, r0
|
|
8002ed0: 817b strh r3, [r7, #10]
|
|
8002ed2: 460b mov r3, r1
|
|
8002ed4: 813b strh r3, [r7, #8]
|
|
8002ed6: 4613 mov r3, r2
|
|
8002ed8: 80fb strh r3, [r7, #6]
|
|
uint32_t tickstart;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
8002eda: 68fb ldr r3, [r7, #12]
|
|
8002edc: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8002ee0: b2db uxtb r3, r3
|
|
8002ee2: 2b20 cmp r3, #32
|
|
8002ee4: f040 80fd bne.w 80030e2 <HAL_I2C_Mem_Read+0x222>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8002ee8: 6a3b ldr r3, [r7, #32]
|
|
8002eea: 2b00 cmp r3, #0
|
|
8002eec: d002 beq.n 8002ef4 <HAL_I2C_Mem_Read+0x34>
|
|
8002eee: 8cbb ldrh r3, [r7, #36] @ 0x24
|
|
8002ef0: 2b00 cmp r3, #0
|
|
8002ef2: d105 bne.n 8002f00 <HAL_I2C_Mem_Read+0x40>
|
|
{
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM;
|
|
8002ef4: 68fb ldr r3, [r7, #12]
|
|
8002ef6: f44f 7200 mov.w r2, #512 @ 0x200
|
|
8002efa: 645a str r2, [r3, #68] @ 0x44
|
|
return HAL_ERROR;
|
|
8002efc: 2301 movs r3, #1
|
|
8002efe: e0f1 b.n 80030e4 <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
8002f00: 68fb ldr r3, [r7, #12]
|
|
8002f02: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
8002f06: 2b01 cmp r3, #1
|
|
8002f08: d101 bne.n 8002f0e <HAL_I2C_Mem_Read+0x4e>
|
|
8002f0a: 2302 movs r3, #2
|
|
8002f0c: e0ea b.n 80030e4 <HAL_I2C_Mem_Read+0x224>
|
|
8002f0e: 68fb ldr r3, [r7, #12]
|
|
8002f10: 2201 movs r2, #1
|
|
8002f12: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
/* Init tickstart for timeout management*/
|
|
tickstart = HAL_GetTick();
|
|
8002f16: f7ff faa1 bl 800245c <HAL_GetTick>
|
|
8002f1a: 6178 str r0, [r7, #20]
|
|
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
|
|
8002f1c: 697b ldr r3, [r7, #20]
|
|
8002f1e: 9300 str r3, [sp, #0]
|
|
8002f20: 2319 movs r3, #25
|
|
8002f22: 2201 movs r2, #1
|
|
8002f24: f44f 4100 mov.w r1, #32768 @ 0x8000
|
|
8002f28: 68f8 ldr r0, [r7, #12]
|
|
8002f2a: f000 f9af bl 800328c <I2C_WaitOnFlagUntilTimeout>
|
|
8002f2e: 4603 mov r3, r0
|
|
8002f30: 2b00 cmp r3, #0
|
|
8002f32: d001 beq.n 8002f38 <HAL_I2C_Mem_Read+0x78>
|
|
{
|
|
return HAL_ERROR;
|
|
8002f34: 2301 movs r3, #1
|
|
8002f36: e0d5 b.n 80030e4 <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY_RX;
|
|
8002f38: 68fb ldr r3, [r7, #12]
|
|
8002f3a: 2222 movs r2, #34 @ 0x22
|
|
8002f3c: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_MEM;
|
|
8002f40: 68fb ldr r3, [r7, #12]
|
|
8002f42: 2240 movs r2, #64 @ 0x40
|
|
8002f44: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
|
8002f48: 68fb ldr r3, [r7, #12]
|
|
8002f4a: 2200 movs r2, #0
|
|
8002f4c: 645a str r2, [r3, #68] @ 0x44
|
|
|
|
/* Prepare transfer parameters */
|
|
hi2c->pBuffPtr = pData;
|
|
8002f4e: 68fb ldr r3, [r7, #12]
|
|
8002f50: 6a3a ldr r2, [r7, #32]
|
|
8002f52: 625a str r2, [r3, #36] @ 0x24
|
|
hi2c->XferCount = Size;
|
|
8002f54: 68fb ldr r3, [r7, #12]
|
|
8002f56: 8cba ldrh r2, [r7, #36] @ 0x24
|
|
8002f58: 855a strh r2, [r3, #42] @ 0x2a
|
|
hi2c->XferISR = NULL;
|
|
8002f5a: 68fb ldr r3, [r7, #12]
|
|
8002f5c: 2200 movs r2, #0
|
|
8002f5e: 635a str r2, [r3, #52] @ 0x34
|
|
|
|
/* Send Slave Address and Memory Address */
|
|
if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
|
|
8002f60: 88f8 ldrh r0, [r7, #6]
|
|
8002f62: 893a ldrh r2, [r7, #8]
|
|
8002f64: 8979 ldrh r1, [r7, #10]
|
|
8002f66: 697b ldr r3, [r7, #20]
|
|
8002f68: 9301 str r3, [sp, #4]
|
|
8002f6a: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8002f6c: 9300 str r3, [sp, #0]
|
|
8002f6e: 4603 mov r3, r0
|
|
8002f70: 68f8 ldr r0, [r7, #12]
|
|
8002f72: f000 f913 bl 800319c <I2C_RequestMemoryRead>
|
|
8002f76: 4603 mov r3, r0
|
|
8002f78: 2b00 cmp r3, #0
|
|
8002f7a: d005 beq.n 8002f88 <HAL_I2C_Mem_Read+0xc8>
|
|
{
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
8002f7c: 68fb ldr r3, [r7, #12]
|
|
8002f7e: 2200 movs r2, #0
|
|
8002f80: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
return HAL_ERROR;
|
|
8002f84: 2301 movs r3, #1
|
|
8002f86: e0ad b.n 80030e4 <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
|
|
/* Send Slave Address */
|
|
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
8002f88: 68fb ldr r3, [r7, #12]
|
|
8002f8a: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8002f8c: b29b uxth r3, r3
|
|
8002f8e: 2bff cmp r3, #255 @ 0xff
|
|
8002f90: d90e bls.n 8002fb0 <HAL_I2C_Mem_Read+0xf0>
|
|
{
|
|
hi2c->XferSize = 1U;
|
|
8002f92: 68fb ldr r3, [r7, #12]
|
|
8002f94: 2201 movs r2, #1
|
|
8002f96: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
|
|
8002f98: 68fb ldr r3, [r7, #12]
|
|
8002f9a: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8002f9c: b2da uxtb r2, r3
|
|
8002f9e: 8979 ldrh r1, [r7, #10]
|
|
8002fa0: 4b52 ldr r3, [pc, #328] @ (80030ec <HAL_I2C_Mem_Read+0x22c>)
|
|
8002fa2: 9300 str r3, [sp, #0]
|
|
8002fa4: f04f 7380 mov.w r3, #16777216 @ 0x1000000
|
|
8002fa8: 68f8 ldr r0, [r7, #12]
|
|
8002faa: f000 fb33 bl 8003614 <I2C_TransferConfig>
|
|
8002fae: e00f b.n 8002fd0 <HAL_I2C_Mem_Read+0x110>
|
|
I2C_GENERATE_START_READ);
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
8002fb0: 68fb ldr r3, [r7, #12]
|
|
8002fb2: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8002fb4: b29a uxth r2, r3
|
|
8002fb6: 68fb ldr r3, [r7, #12]
|
|
8002fb8: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
|
|
8002fba: 68fb ldr r3, [r7, #12]
|
|
8002fbc: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8002fbe: b2da uxtb r2, r3
|
|
8002fc0: 8979 ldrh r1, [r7, #10]
|
|
8002fc2: 4b4a ldr r3, [pc, #296] @ (80030ec <HAL_I2C_Mem_Read+0x22c>)
|
|
8002fc4: 9300 str r3, [sp, #0]
|
|
8002fc6: f04f 7300 mov.w r3, #33554432 @ 0x2000000
|
|
8002fca: 68f8 ldr r0, [r7, #12]
|
|
8002fcc: f000 fb22 bl 8003614 <I2C_TransferConfig>
|
|
}
|
|
|
|
do
|
|
{
|
|
/* Wait until RXNE flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
|
|
8002fd0: 697b ldr r3, [r7, #20]
|
|
8002fd2: 9300 str r3, [sp, #0]
|
|
8002fd4: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8002fd6: 2200 movs r2, #0
|
|
8002fd8: 2104 movs r1, #4
|
|
8002fda: 68f8 ldr r0, [r7, #12]
|
|
8002fdc: f000 f956 bl 800328c <I2C_WaitOnFlagUntilTimeout>
|
|
8002fe0: 4603 mov r3, r0
|
|
8002fe2: 2b00 cmp r3, #0
|
|
8002fe4: d001 beq.n 8002fea <HAL_I2C_Mem_Read+0x12a>
|
|
{
|
|
return HAL_ERROR;
|
|
8002fe6: 2301 movs r3, #1
|
|
8002fe8: e07c b.n 80030e4 <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
|
|
/* Read data from RXDR */
|
|
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
|
|
8002fea: 68fb ldr r3, [r7, #12]
|
|
8002fec: 681b ldr r3, [r3, #0]
|
|
8002fee: 6a5a ldr r2, [r3, #36] @ 0x24
|
|
8002ff0: 68fb ldr r3, [r7, #12]
|
|
8002ff2: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8002ff4: b2d2 uxtb r2, r2
|
|
8002ff6: 701a strb r2, [r3, #0]
|
|
|
|
/* Increment Buffer pointer */
|
|
hi2c->pBuffPtr++;
|
|
8002ff8: 68fb ldr r3, [r7, #12]
|
|
8002ffa: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8002ffc: 1c5a adds r2, r3, #1
|
|
8002ffe: 68fb ldr r3, [r7, #12]
|
|
8003000: 625a str r2, [r3, #36] @ 0x24
|
|
|
|
hi2c->XferSize--;
|
|
8003002: 68fb ldr r3, [r7, #12]
|
|
8003004: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
8003006: 3b01 subs r3, #1
|
|
8003008: b29a uxth r2, r3
|
|
800300a: 68fb ldr r3, [r7, #12]
|
|
800300c: 851a strh r2, [r3, #40] @ 0x28
|
|
hi2c->XferCount--;
|
|
800300e: 68fb ldr r3, [r7, #12]
|
|
8003010: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8003012: b29b uxth r3, r3
|
|
8003014: 3b01 subs r3, #1
|
|
8003016: b29a uxth r2, r3
|
|
8003018: 68fb ldr r3, [r7, #12]
|
|
800301a: 855a strh r2, [r3, #42] @ 0x2a
|
|
|
|
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
|
|
800301c: 68fb ldr r3, [r7, #12]
|
|
800301e: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8003020: b29b uxth r3, r3
|
|
8003022: 2b00 cmp r3, #0
|
|
8003024: d034 beq.n 8003090 <HAL_I2C_Mem_Read+0x1d0>
|
|
8003026: 68fb ldr r3, [r7, #12]
|
|
8003028: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
800302a: 2b00 cmp r3, #0
|
|
800302c: d130 bne.n 8003090 <HAL_I2C_Mem_Read+0x1d0>
|
|
{
|
|
/* Wait until TCR flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
|
|
800302e: 697b ldr r3, [r7, #20]
|
|
8003030: 9300 str r3, [sp, #0]
|
|
8003032: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8003034: 2200 movs r2, #0
|
|
8003036: 2180 movs r1, #128 @ 0x80
|
|
8003038: 68f8 ldr r0, [r7, #12]
|
|
800303a: f000 f927 bl 800328c <I2C_WaitOnFlagUntilTimeout>
|
|
800303e: 4603 mov r3, r0
|
|
8003040: 2b00 cmp r3, #0
|
|
8003042: d001 beq.n 8003048 <HAL_I2C_Mem_Read+0x188>
|
|
{
|
|
return HAL_ERROR;
|
|
8003044: 2301 movs r3, #1
|
|
8003046: e04d b.n 80030e4 <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
|
|
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
|
8003048: 68fb ldr r3, [r7, #12]
|
|
800304a: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
800304c: b29b uxth r3, r3
|
|
800304e: 2bff cmp r3, #255 @ 0xff
|
|
8003050: d90e bls.n 8003070 <HAL_I2C_Mem_Read+0x1b0>
|
|
{
|
|
hi2c->XferSize = 1U;
|
|
8003052: 68fb ldr r3, [r7, #12]
|
|
8003054: 2201 movs r2, #1
|
|
8003056: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
|
|
8003058: 68fb ldr r3, [r7, #12]
|
|
800305a: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
800305c: b2da uxtb r2, r3
|
|
800305e: 8979 ldrh r1, [r7, #10]
|
|
8003060: 2300 movs r3, #0
|
|
8003062: 9300 str r3, [sp, #0]
|
|
8003064: f04f 7380 mov.w r3, #16777216 @ 0x1000000
|
|
8003068: 68f8 ldr r0, [r7, #12]
|
|
800306a: f000 fad3 bl 8003614 <I2C_TransferConfig>
|
|
800306e: e00f b.n 8003090 <HAL_I2C_Mem_Read+0x1d0>
|
|
I2C_NO_STARTSTOP);
|
|
}
|
|
else
|
|
{
|
|
hi2c->XferSize = hi2c->XferCount;
|
|
8003070: 68fb ldr r3, [r7, #12]
|
|
8003072: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8003074: b29a uxth r2, r3
|
|
8003076: 68fb ldr r3, [r7, #12]
|
|
8003078: 851a strh r2, [r3, #40] @ 0x28
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
|
|
800307a: 68fb ldr r3, [r7, #12]
|
|
800307c: 8d1b ldrh r3, [r3, #40] @ 0x28
|
|
800307e: b2da uxtb r2, r3
|
|
8003080: 8979 ldrh r1, [r7, #10]
|
|
8003082: 2300 movs r3, #0
|
|
8003084: 9300 str r3, [sp, #0]
|
|
8003086: f04f 7300 mov.w r3, #33554432 @ 0x2000000
|
|
800308a: 68f8 ldr r0, [r7, #12]
|
|
800308c: f000 fac2 bl 8003614 <I2C_TransferConfig>
|
|
I2C_NO_STARTSTOP);
|
|
}
|
|
}
|
|
} while (hi2c->XferCount > 0U);
|
|
8003090: 68fb ldr r3, [r7, #12]
|
|
8003092: 8d5b ldrh r3, [r3, #42] @ 0x2a
|
|
8003094: b29b uxth r3, r3
|
|
8003096: 2b00 cmp r3, #0
|
|
8003098: d19a bne.n 8002fd0 <HAL_I2C_Mem_Read+0x110>
|
|
|
|
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
|
|
/* Wait until STOPF flag is reset */
|
|
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
|
|
800309a: 697a ldr r2, [r7, #20]
|
|
800309c: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
800309e: 68f8 ldr r0, [r7, #12]
|
|
80030a0: f000 f994 bl 80033cc <I2C_WaitOnSTOPFlagUntilTimeout>
|
|
80030a4: 4603 mov r3, r0
|
|
80030a6: 2b00 cmp r3, #0
|
|
80030a8: d001 beq.n 80030ae <HAL_I2C_Mem_Read+0x1ee>
|
|
{
|
|
return HAL_ERROR;
|
|
80030aa: 2301 movs r3, #1
|
|
80030ac: e01a b.n 80030e4 <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
|
|
/* Clear STOP Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
|
80030ae: 68fb ldr r3, [r7, #12]
|
|
80030b0: 681b ldr r3, [r3, #0]
|
|
80030b2: 2220 movs r2, #32
|
|
80030b4: 61da str r2, [r3, #28]
|
|
|
|
/* Clear Configuration Register 2 */
|
|
I2C_RESET_CR2(hi2c);
|
|
80030b6: 68fb ldr r3, [r7, #12]
|
|
80030b8: 681b ldr r3, [r3, #0]
|
|
80030ba: 6859 ldr r1, [r3, #4]
|
|
80030bc: 68fb ldr r3, [r7, #12]
|
|
80030be: 681a ldr r2, [r3, #0]
|
|
80030c0: 4b0b ldr r3, [pc, #44] @ (80030f0 <HAL_I2C_Mem_Read+0x230>)
|
|
80030c2: 400b ands r3, r1
|
|
80030c4: 6053 str r3, [r2, #4]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
80030c6: 68fb ldr r3, [r7, #12]
|
|
80030c8: 2220 movs r2, #32
|
|
80030ca: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
80030ce: 68fb ldr r3, [r7, #12]
|
|
80030d0: 2200 movs r2, #0
|
|
80030d2: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
80030d6: 68fb ldr r3, [r7, #12]
|
|
80030d8: 2200 movs r2, #0
|
|
80030da: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_OK;
|
|
80030de: 2300 movs r3, #0
|
|
80030e0: e000 b.n 80030e4 <HAL_I2C_Mem_Read+0x224>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
80030e2: 2302 movs r3, #2
|
|
}
|
|
}
|
|
80030e4: 4618 mov r0, r3
|
|
80030e6: 3718 adds r7, #24
|
|
80030e8: 46bd mov sp, r7
|
|
80030ea: bd80 pop {r7, pc}
|
|
80030ec: 80002400 .word 0x80002400
|
|
80030f0: fe00e800 .word 0xfe00e800
|
|
|
|
080030f4 <I2C_RequestMemoryWrite>:
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
|
|
uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
|
|
uint32_t Tickstart)
|
|
{
|
|
80030f4: b580 push {r7, lr}
|
|
80030f6: b086 sub sp, #24
|
|
80030f8: af02 add r7, sp, #8
|
|
80030fa: 60f8 str r0, [r7, #12]
|
|
80030fc: 4608 mov r0, r1
|
|
80030fe: 4611 mov r1, r2
|
|
8003100: 461a mov r2, r3
|
|
8003102: 4603 mov r3, r0
|
|
8003104: 817b strh r3, [r7, #10]
|
|
8003106: 460b mov r3, r1
|
|
8003108: 813b strh r3, [r7, #8]
|
|
800310a: 4613 mov r3, r2
|
|
800310c: 80fb strh r3, [r7, #6]
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
|
|
800310e: 88fb ldrh r3, [r7, #6]
|
|
8003110: b2da uxtb r2, r3
|
|
8003112: 8979 ldrh r1, [r7, #10]
|
|
8003114: 4b20 ldr r3, [pc, #128] @ (8003198 <I2C_RequestMemoryWrite+0xa4>)
|
|
8003116: 9300 str r3, [sp, #0]
|
|
8003118: f04f 7380 mov.w r3, #16777216 @ 0x1000000
|
|
800311c: 68f8 ldr r0, [r7, #12]
|
|
800311e: f000 fa79 bl 8003614 <I2C_TransferConfig>
|
|
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
8003122: 69fa ldr r2, [r7, #28]
|
|
8003124: 69b9 ldr r1, [r7, #24]
|
|
8003126: 68f8 ldr r0, [r7, #12]
|
|
8003128: f000 f909 bl 800333e <I2C_WaitOnTXISFlagUntilTimeout>
|
|
800312c: 4603 mov r3, r0
|
|
800312e: 2b00 cmp r3, #0
|
|
8003130: d001 beq.n 8003136 <I2C_RequestMemoryWrite+0x42>
|
|
{
|
|
return HAL_ERROR;
|
|
8003132: 2301 movs r3, #1
|
|
8003134: e02c b.n 8003190 <I2C_RequestMemoryWrite+0x9c>
|
|
}
|
|
|
|
/* If Memory address size is 8Bit */
|
|
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
|
|
8003136: 88fb ldrh r3, [r7, #6]
|
|
8003138: 2b01 cmp r3, #1
|
|
800313a: d105 bne.n 8003148 <I2C_RequestMemoryWrite+0x54>
|
|
{
|
|
/* Send Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
|
|
800313c: 893b ldrh r3, [r7, #8]
|
|
800313e: b2da uxtb r2, r3
|
|
8003140: 68fb ldr r3, [r7, #12]
|
|
8003142: 681b ldr r3, [r3, #0]
|
|
8003144: 629a str r2, [r3, #40] @ 0x28
|
|
8003146: e015 b.n 8003174 <I2C_RequestMemoryWrite+0x80>
|
|
}
|
|
/* If Memory address size is 16Bit */
|
|
else
|
|
{
|
|
/* Send MSB of Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
|
|
8003148: 893b ldrh r3, [r7, #8]
|
|
800314a: 0a1b lsrs r3, r3, #8
|
|
800314c: b29b uxth r3, r3
|
|
800314e: b2da uxtb r2, r3
|
|
8003150: 68fb ldr r3, [r7, #12]
|
|
8003152: 681b ldr r3, [r3, #0]
|
|
8003154: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
8003156: 69fa ldr r2, [r7, #28]
|
|
8003158: 69b9 ldr r1, [r7, #24]
|
|
800315a: 68f8 ldr r0, [r7, #12]
|
|
800315c: f000 f8ef bl 800333e <I2C_WaitOnTXISFlagUntilTimeout>
|
|
8003160: 4603 mov r3, r0
|
|
8003162: 2b00 cmp r3, #0
|
|
8003164: d001 beq.n 800316a <I2C_RequestMemoryWrite+0x76>
|
|
{
|
|
return HAL_ERROR;
|
|
8003166: 2301 movs r3, #1
|
|
8003168: e012 b.n 8003190 <I2C_RequestMemoryWrite+0x9c>
|
|
}
|
|
|
|
/* Send LSB of Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
|
|
800316a: 893b ldrh r3, [r7, #8]
|
|
800316c: b2da uxtb r2, r3
|
|
800316e: 68fb ldr r3, [r7, #12]
|
|
8003170: 681b ldr r3, [r3, #0]
|
|
8003172: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
|
|
/* Wait until TCR flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
|
|
8003174: 69fb ldr r3, [r7, #28]
|
|
8003176: 9300 str r3, [sp, #0]
|
|
8003178: 69bb ldr r3, [r7, #24]
|
|
800317a: 2200 movs r2, #0
|
|
800317c: 2180 movs r1, #128 @ 0x80
|
|
800317e: 68f8 ldr r0, [r7, #12]
|
|
8003180: f000 f884 bl 800328c <I2C_WaitOnFlagUntilTimeout>
|
|
8003184: 4603 mov r3, r0
|
|
8003186: 2b00 cmp r3, #0
|
|
8003188: d001 beq.n 800318e <I2C_RequestMemoryWrite+0x9a>
|
|
{
|
|
return HAL_ERROR;
|
|
800318a: 2301 movs r3, #1
|
|
800318c: e000 b.n 8003190 <I2C_RequestMemoryWrite+0x9c>
|
|
}
|
|
|
|
return HAL_OK;
|
|
800318e: 2300 movs r3, #0
|
|
}
|
|
8003190: 4618 mov r0, r3
|
|
8003192: 3710 adds r7, #16
|
|
8003194: 46bd mov sp, r7
|
|
8003196: bd80 pop {r7, pc}
|
|
8003198: 80002000 .word 0x80002000
|
|
|
|
0800319c <I2C_RequestMemoryRead>:
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
|
|
uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout,
|
|
uint32_t Tickstart)
|
|
{
|
|
800319c: b580 push {r7, lr}
|
|
800319e: b086 sub sp, #24
|
|
80031a0: af02 add r7, sp, #8
|
|
80031a2: 60f8 str r0, [r7, #12]
|
|
80031a4: 4608 mov r0, r1
|
|
80031a6: 4611 mov r1, r2
|
|
80031a8: 461a mov r2, r3
|
|
80031aa: 4603 mov r3, r0
|
|
80031ac: 817b strh r3, [r7, #10]
|
|
80031ae: 460b mov r3, r1
|
|
80031b0: 813b strh r3, [r7, #8]
|
|
80031b2: 4613 mov r3, r2
|
|
80031b4: 80fb strh r3, [r7, #6]
|
|
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
|
|
80031b6: 88fb ldrh r3, [r7, #6]
|
|
80031b8: b2da uxtb r2, r3
|
|
80031ba: 8979 ldrh r1, [r7, #10]
|
|
80031bc: 4b20 ldr r3, [pc, #128] @ (8003240 <I2C_RequestMemoryRead+0xa4>)
|
|
80031be: 9300 str r3, [sp, #0]
|
|
80031c0: 2300 movs r3, #0
|
|
80031c2: 68f8 ldr r0, [r7, #12]
|
|
80031c4: f000 fa26 bl 8003614 <I2C_TransferConfig>
|
|
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
80031c8: 69fa ldr r2, [r7, #28]
|
|
80031ca: 69b9 ldr r1, [r7, #24]
|
|
80031cc: 68f8 ldr r0, [r7, #12]
|
|
80031ce: f000 f8b6 bl 800333e <I2C_WaitOnTXISFlagUntilTimeout>
|
|
80031d2: 4603 mov r3, r0
|
|
80031d4: 2b00 cmp r3, #0
|
|
80031d6: d001 beq.n 80031dc <I2C_RequestMemoryRead+0x40>
|
|
{
|
|
return HAL_ERROR;
|
|
80031d8: 2301 movs r3, #1
|
|
80031da: e02c b.n 8003236 <I2C_RequestMemoryRead+0x9a>
|
|
}
|
|
|
|
/* If Memory address size is 8Bit */
|
|
if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
|
|
80031dc: 88fb ldrh r3, [r7, #6]
|
|
80031de: 2b01 cmp r3, #1
|
|
80031e0: d105 bne.n 80031ee <I2C_RequestMemoryRead+0x52>
|
|
{
|
|
/* Send Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
|
|
80031e2: 893b ldrh r3, [r7, #8]
|
|
80031e4: b2da uxtb r2, r3
|
|
80031e6: 68fb ldr r3, [r7, #12]
|
|
80031e8: 681b ldr r3, [r3, #0]
|
|
80031ea: 629a str r2, [r3, #40] @ 0x28
|
|
80031ec: e015 b.n 800321a <I2C_RequestMemoryRead+0x7e>
|
|
}
|
|
/* If Memory address size is 16Bit */
|
|
else
|
|
{
|
|
/* Send MSB of Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
|
|
80031ee: 893b ldrh r3, [r7, #8]
|
|
80031f0: 0a1b lsrs r3, r3, #8
|
|
80031f2: b29b uxth r3, r3
|
|
80031f4: b2da uxtb r2, r3
|
|
80031f6: 68fb ldr r3, [r7, #12]
|
|
80031f8: 681b ldr r3, [r3, #0]
|
|
80031fa: 629a str r2, [r3, #40] @ 0x28
|
|
|
|
/* Wait until TXIS flag is set */
|
|
if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
80031fc: 69fa ldr r2, [r7, #28]
|
|
80031fe: 69b9 ldr r1, [r7, #24]
|
|
8003200: 68f8 ldr r0, [r7, #12]
|
|
8003202: f000 f89c bl 800333e <I2C_WaitOnTXISFlagUntilTimeout>
|
|
8003206: 4603 mov r3, r0
|
|
8003208: 2b00 cmp r3, #0
|
|
800320a: d001 beq.n 8003210 <I2C_RequestMemoryRead+0x74>
|
|
{
|
|
return HAL_ERROR;
|
|
800320c: 2301 movs r3, #1
|
|
800320e: e012 b.n 8003236 <I2C_RequestMemoryRead+0x9a>
|
|
}
|
|
|
|
/* Send LSB of Memory Address */
|
|
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
|
|
8003210: 893b ldrh r3, [r7, #8]
|
|
8003212: b2da uxtb r2, r3
|
|
8003214: 68fb ldr r3, [r7, #12]
|
|
8003216: 681b ldr r3, [r3, #0]
|
|
8003218: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
|
|
/* Wait until TC flag is set */
|
|
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
|
|
800321a: 69fb ldr r3, [r7, #28]
|
|
800321c: 9300 str r3, [sp, #0]
|
|
800321e: 69bb ldr r3, [r7, #24]
|
|
8003220: 2200 movs r2, #0
|
|
8003222: 2140 movs r1, #64 @ 0x40
|
|
8003224: 68f8 ldr r0, [r7, #12]
|
|
8003226: f000 f831 bl 800328c <I2C_WaitOnFlagUntilTimeout>
|
|
800322a: 4603 mov r3, r0
|
|
800322c: 2b00 cmp r3, #0
|
|
800322e: d001 beq.n 8003234 <I2C_RequestMemoryRead+0x98>
|
|
{
|
|
return HAL_ERROR;
|
|
8003230: 2301 movs r3, #1
|
|
8003232: e000 b.n 8003236 <I2C_RequestMemoryRead+0x9a>
|
|
}
|
|
|
|
return HAL_OK;
|
|
8003234: 2300 movs r3, #0
|
|
}
|
|
8003236: 4618 mov r0, r3
|
|
8003238: 3710 adds r7, #16
|
|
800323a: 46bd mov sp, r7
|
|
800323c: bd80 pop {r7, pc}
|
|
800323e: bf00 nop
|
|
8003240: 80002000 .word 0x80002000
|
|
|
|
08003244 <I2C_Flush_TXDR>:
|
|
* @brief I2C Tx data register flush process.
|
|
* @param hi2c I2C handle.
|
|
* @retval None
|
|
*/
|
|
static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
|
|
{
|
|
8003244: b480 push {r7}
|
|
8003246: b083 sub sp, #12
|
|
8003248: af00 add r7, sp, #0
|
|
800324a: 6078 str r0, [r7, #4]
|
|
/* If a pending TXIS flag is set */
|
|
/* Write a dummy data in TXDR to clear it */
|
|
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
|
|
800324c: 687b ldr r3, [r7, #4]
|
|
800324e: 681b ldr r3, [r3, #0]
|
|
8003250: 699b ldr r3, [r3, #24]
|
|
8003252: f003 0302 and.w r3, r3, #2
|
|
8003256: 2b02 cmp r3, #2
|
|
8003258: d103 bne.n 8003262 <I2C_Flush_TXDR+0x1e>
|
|
{
|
|
hi2c->Instance->TXDR = 0x00U;
|
|
800325a: 687b ldr r3, [r7, #4]
|
|
800325c: 681b ldr r3, [r3, #0]
|
|
800325e: 2200 movs r2, #0
|
|
8003260: 629a str r2, [r3, #40] @ 0x28
|
|
}
|
|
|
|
/* Flush TX register if not empty */
|
|
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
|
|
8003262: 687b ldr r3, [r7, #4]
|
|
8003264: 681b ldr r3, [r3, #0]
|
|
8003266: 699b ldr r3, [r3, #24]
|
|
8003268: f003 0301 and.w r3, r3, #1
|
|
800326c: 2b01 cmp r3, #1
|
|
800326e: d007 beq.n 8003280 <I2C_Flush_TXDR+0x3c>
|
|
{
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
|
|
8003270: 687b ldr r3, [r7, #4]
|
|
8003272: 681b ldr r3, [r3, #0]
|
|
8003274: 699a ldr r2, [r3, #24]
|
|
8003276: 687b ldr r3, [r7, #4]
|
|
8003278: 681b ldr r3, [r3, #0]
|
|
800327a: f042 0201 orr.w r2, r2, #1
|
|
800327e: 619a str r2, [r3, #24]
|
|
}
|
|
}
|
|
8003280: bf00 nop
|
|
8003282: 370c adds r7, #12
|
|
8003284: 46bd mov sp, r7
|
|
8003286: f85d 7b04 ldr.w r7, [sp], #4
|
|
800328a: 4770 bx lr
|
|
|
|
0800328c <I2C_WaitOnFlagUntilTimeout>:
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status,
|
|
uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
800328c: b580 push {r7, lr}
|
|
800328e: b084 sub sp, #16
|
|
8003290: af00 add r7, sp, #0
|
|
8003292: 60f8 str r0, [r7, #12]
|
|
8003294: 60b9 str r1, [r7, #8]
|
|
8003296: 603b str r3, [r7, #0]
|
|
8003298: 4613 mov r3, r2
|
|
800329a: 71fb strb r3, [r7, #7]
|
|
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
|
|
800329c: e03b b.n 8003316 <I2C_WaitOnFlagUntilTimeout+0x8a>
|
|
{
|
|
/* Check if an error is detected */
|
|
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
800329e: 69ba ldr r2, [r7, #24]
|
|
80032a0: 6839 ldr r1, [r7, #0]
|
|
80032a2: 68f8 ldr r0, [r7, #12]
|
|
80032a4: f000 f8d6 bl 8003454 <I2C_IsErrorOccurred>
|
|
80032a8: 4603 mov r3, r0
|
|
80032aa: 2b00 cmp r3, #0
|
|
80032ac: d001 beq.n 80032b2 <I2C_WaitOnFlagUntilTimeout+0x26>
|
|
{
|
|
return HAL_ERROR;
|
|
80032ae: 2301 movs r3, #1
|
|
80032b0: e041 b.n 8003336 <I2C_WaitOnFlagUntilTimeout+0xaa>
|
|
}
|
|
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
80032b2: 683b ldr r3, [r7, #0]
|
|
80032b4: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
80032b8: d02d beq.n 8003316 <I2C_WaitOnFlagUntilTimeout+0x8a>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
80032ba: f7ff f8cf bl 800245c <HAL_GetTick>
|
|
80032be: 4602 mov r2, r0
|
|
80032c0: 69bb ldr r3, [r7, #24]
|
|
80032c2: 1ad3 subs r3, r2, r3
|
|
80032c4: 683a ldr r2, [r7, #0]
|
|
80032c6: 429a cmp r2, r3
|
|
80032c8: d302 bcc.n 80032d0 <I2C_WaitOnFlagUntilTimeout+0x44>
|
|
80032ca: 683b ldr r3, [r7, #0]
|
|
80032cc: 2b00 cmp r3, #0
|
|
80032ce: d122 bne.n 8003316 <I2C_WaitOnFlagUntilTimeout+0x8a>
|
|
{
|
|
if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status))
|
|
80032d0: 68fb ldr r3, [r7, #12]
|
|
80032d2: 681b ldr r3, [r3, #0]
|
|
80032d4: 699a ldr r2, [r3, #24]
|
|
80032d6: 68bb ldr r3, [r7, #8]
|
|
80032d8: 4013 ands r3, r2
|
|
80032da: 68ba ldr r2, [r7, #8]
|
|
80032dc: 429a cmp r2, r3
|
|
80032de: bf0c ite eq
|
|
80032e0: 2301 moveq r3, #1
|
|
80032e2: 2300 movne r3, #0
|
|
80032e4: b2db uxtb r3, r3
|
|
80032e6: 461a mov r2, r3
|
|
80032e8: 79fb ldrb r3, [r7, #7]
|
|
80032ea: 429a cmp r2, r3
|
|
80032ec: d113 bne.n 8003316 <I2C_WaitOnFlagUntilTimeout+0x8a>
|
|
{
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
|
80032ee: 68fb ldr r3, [r7, #12]
|
|
80032f0: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
80032f2: f043 0220 orr.w r2, r3, #32
|
|
80032f6: 68fb ldr r3, [r7, #12]
|
|
80032f8: 645a str r2, [r3, #68] @ 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
80032fa: 68fb ldr r3, [r7, #12]
|
|
80032fc: 2220 movs r2, #32
|
|
80032fe: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8003302: 68fb ldr r3, [r7, #12]
|
|
8003304: 2200 movs r2, #0
|
|
8003306: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
800330a: 68fb ldr r3, [r7, #12]
|
|
800330c: 2200 movs r2, #0
|
|
800330e: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
return HAL_ERROR;
|
|
8003312: 2301 movs r3, #1
|
|
8003314: e00f b.n 8003336 <I2C_WaitOnFlagUntilTimeout+0xaa>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
|
|
8003316: 68fb ldr r3, [r7, #12]
|
|
8003318: 681b ldr r3, [r3, #0]
|
|
800331a: 699a ldr r2, [r3, #24]
|
|
800331c: 68bb ldr r3, [r7, #8]
|
|
800331e: 4013 ands r3, r2
|
|
8003320: 68ba ldr r2, [r7, #8]
|
|
8003322: 429a cmp r2, r3
|
|
8003324: bf0c ite eq
|
|
8003326: 2301 moveq r3, #1
|
|
8003328: 2300 movne r3, #0
|
|
800332a: b2db uxtb r3, r3
|
|
800332c: 461a mov r2, r3
|
|
800332e: 79fb ldrb r3, [r7, #7]
|
|
8003330: 429a cmp r2, r3
|
|
8003332: d0b4 beq.n 800329e <I2C_WaitOnFlagUntilTimeout+0x12>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8003334: 2300 movs r3, #0
|
|
}
|
|
8003336: 4618 mov r0, r3
|
|
8003338: 3710 adds r7, #16
|
|
800333a: 46bd mov sp, r7
|
|
800333c: bd80 pop {r7, pc}
|
|
|
|
0800333e <I2C_WaitOnTXISFlagUntilTimeout>:
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
|
|
uint32_t Tickstart)
|
|
{
|
|
800333e: b580 push {r7, lr}
|
|
8003340: b084 sub sp, #16
|
|
8003342: af00 add r7, sp, #0
|
|
8003344: 60f8 str r0, [r7, #12]
|
|
8003346: 60b9 str r1, [r7, #8]
|
|
8003348: 607a str r2, [r7, #4]
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
|
|
800334a: e033 b.n 80033b4 <I2C_WaitOnTXISFlagUntilTimeout+0x76>
|
|
{
|
|
/* Check if an error is detected */
|
|
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
800334c: 687a ldr r2, [r7, #4]
|
|
800334e: 68b9 ldr r1, [r7, #8]
|
|
8003350: 68f8 ldr r0, [r7, #12]
|
|
8003352: f000 f87f bl 8003454 <I2C_IsErrorOccurred>
|
|
8003356: 4603 mov r3, r0
|
|
8003358: 2b00 cmp r3, #0
|
|
800335a: d001 beq.n 8003360 <I2C_WaitOnTXISFlagUntilTimeout+0x22>
|
|
{
|
|
return HAL_ERROR;
|
|
800335c: 2301 movs r3, #1
|
|
800335e: e031 b.n 80033c4 <I2C_WaitOnTXISFlagUntilTimeout+0x86>
|
|
}
|
|
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
8003360: 68bb ldr r3, [r7, #8]
|
|
8003362: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8003366: d025 beq.n 80033b4 <I2C_WaitOnTXISFlagUntilTimeout+0x76>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
8003368: f7ff f878 bl 800245c <HAL_GetTick>
|
|
800336c: 4602 mov r2, r0
|
|
800336e: 687b ldr r3, [r7, #4]
|
|
8003370: 1ad3 subs r3, r2, r3
|
|
8003372: 68ba ldr r2, [r7, #8]
|
|
8003374: 429a cmp r2, r3
|
|
8003376: d302 bcc.n 800337e <I2C_WaitOnTXISFlagUntilTimeout+0x40>
|
|
8003378: 68bb ldr r3, [r7, #8]
|
|
800337a: 2b00 cmp r3, #0
|
|
800337c: d11a bne.n 80033b4 <I2C_WaitOnTXISFlagUntilTimeout+0x76>
|
|
{
|
|
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET))
|
|
800337e: 68fb ldr r3, [r7, #12]
|
|
8003380: 681b ldr r3, [r3, #0]
|
|
8003382: 699b ldr r3, [r3, #24]
|
|
8003384: f003 0302 and.w r3, r3, #2
|
|
8003388: 2b02 cmp r3, #2
|
|
800338a: d013 beq.n 80033b4 <I2C_WaitOnTXISFlagUntilTimeout+0x76>
|
|
{
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
|
800338c: 68fb ldr r3, [r7, #12]
|
|
800338e: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8003390: f043 0220 orr.w r2, r3, #32
|
|
8003394: 68fb ldr r3, [r7, #12]
|
|
8003396: 645a str r2, [r3, #68] @ 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8003398: 68fb ldr r3, [r7, #12]
|
|
800339a: 2220 movs r2, #32
|
|
800339c: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
80033a0: 68fb ldr r3, [r7, #12]
|
|
80033a2: 2200 movs r2, #0
|
|
80033a4: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
80033a8: 68fb ldr r3, [r7, #12]
|
|
80033aa: 2200 movs r2, #0
|
|
80033ac: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_ERROR;
|
|
80033b0: 2301 movs r3, #1
|
|
80033b2: e007 b.n 80033c4 <I2C_WaitOnTXISFlagUntilTimeout+0x86>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
|
|
80033b4: 68fb ldr r3, [r7, #12]
|
|
80033b6: 681b ldr r3, [r3, #0]
|
|
80033b8: 699b ldr r3, [r3, #24]
|
|
80033ba: f003 0302 and.w r3, r3, #2
|
|
80033be: 2b02 cmp r3, #2
|
|
80033c0: d1c4 bne.n 800334c <I2C_WaitOnTXISFlagUntilTimeout+0xe>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
80033c2: 2300 movs r3, #0
|
|
}
|
|
80033c4: 4618 mov r0, r3
|
|
80033c6: 3710 adds r7, #16
|
|
80033c8: 46bd mov sp, r7
|
|
80033ca: bd80 pop {r7, pc}
|
|
|
|
080033cc <I2C_WaitOnSTOPFlagUntilTimeout>:
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
|
|
uint32_t Tickstart)
|
|
{
|
|
80033cc: b580 push {r7, lr}
|
|
80033ce: b084 sub sp, #16
|
|
80033d0: af00 add r7, sp, #0
|
|
80033d2: 60f8 str r0, [r7, #12]
|
|
80033d4: 60b9 str r1, [r7, #8]
|
|
80033d6: 607a str r2, [r7, #4]
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
|
|
80033d8: e02f b.n 800343a <I2C_WaitOnSTOPFlagUntilTimeout+0x6e>
|
|
{
|
|
/* Check if an error is detected */
|
|
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
|
|
80033da: 687a ldr r2, [r7, #4]
|
|
80033dc: 68b9 ldr r1, [r7, #8]
|
|
80033de: 68f8 ldr r0, [r7, #12]
|
|
80033e0: f000 f838 bl 8003454 <I2C_IsErrorOccurred>
|
|
80033e4: 4603 mov r3, r0
|
|
80033e6: 2b00 cmp r3, #0
|
|
80033e8: d001 beq.n 80033ee <I2C_WaitOnSTOPFlagUntilTimeout+0x22>
|
|
{
|
|
return HAL_ERROR;
|
|
80033ea: 2301 movs r3, #1
|
|
80033ec: e02d b.n 800344a <I2C_WaitOnSTOPFlagUntilTimeout+0x7e>
|
|
}
|
|
|
|
/* Check for the Timeout */
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
80033ee: f7ff f835 bl 800245c <HAL_GetTick>
|
|
80033f2: 4602 mov r2, r0
|
|
80033f4: 687b ldr r3, [r7, #4]
|
|
80033f6: 1ad3 subs r3, r2, r3
|
|
80033f8: 68ba ldr r2, [r7, #8]
|
|
80033fa: 429a cmp r2, r3
|
|
80033fc: d302 bcc.n 8003404 <I2C_WaitOnSTOPFlagUntilTimeout+0x38>
|
|
80033fe: 68bb ldr r3, [r7, #8]
|
|
8003400: 2b00 cmp r3, #0
|
|
8003402: d11a bne.n 800343a <I2C_WaitOnSTOPFlagUntilTimeout+0x6e>
|
|
{
|
|
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET))
|
|
8003404: 68fb ldr r3, [r7, #12]
|
|
8003406: 681b ldr r3, [r3, #0]
|
|
8003408: 699b ldr r3, [r3, #24]
|
|
800340a: f003 0320 and.w r3, r3, #32
|
|
800340e: 2b20 cmp r3, #32
|
|
8003410: d013 beq.n 800343a <I2C_WaitOnSTOPFlagUntilTimeout+0x6e>
|
|
{
|
|
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
|
|
8003412: 68fb ldr r3, [r7, #12]
|
|
8003414: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
8003416: f043 0220 orr.w r2, r3, #32
|
|
800341a: 68fb ldr r3, [r7, #12]
|
|
800341c: 645a str r2, [r3, #68] @ 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
800341e: 68fb ldr r3, [r7, #12]
|
|
8003420: 2220 movs r2, #32
|
|
8003422: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
8003426: 68fb ldr r3, [r7, #12]
|
|
8003428: 2200 movs r2, #0
|
|
800342a: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
800342e: 68fb ldr r3, [r7, #12]
|
|
8003430: 2200 movs r2, #0
|
|
8003432: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_ERROR;
|
|
8003436: 2301 movs r3, #1
|
|
8003438: e007 b.n 800344a <I2C_WaitOnSTOPFlagUntilTimeout+0x7e>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
|
|
800343a: 68fb ldr r3, [r7, #12]
|
|
800343c: 681b ldr r3, [r3, #0]
|
|
800343e: 699b ldr r3, [r3, #24]
|
|
8003440: f003 0320 and.w r3, r3, #32
|
|
8003444: 2b20 cmp r3, #32
|
|
8003446: d1c8 bne.n 80033da <I2C_WaitOnSTOPFlagUntilTimeout+0xe>
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8003448: 2300 movs r3, #0
|
|
}
|
|
800344a: 4618 mov r0, r3
|
|
800344c: 3710 adds r7, #16
|
|
800344e: 46bd mov sp, r7
|
|
8003450: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08003454 <I2C_IsErrorOccurred>:
|
|
* @param Timeout Timeout duration
|
|
* @param Tickstart Tick start value
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
|
|
{
|
|
8003454: b580 push {r7, lr}
|
|
8003456: b08a sub sp, #40 @ 0x28
|
|
8003458: af00 add r7, sp, #0
|
|
800345a: 60f8 str r0, [r7, #12]
|
|
800345c: 60b9 str r1, [r7, #8]
|
|
800345e: 607a str r2, [r7, #4]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8003460: 2300 movs r3, #0
|
|
8003462: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
uint32_t itflag = hi2c->Instance->ISR;
|
|
8003466: 68fb ldr r3, [r7, #12]
|
|
8003468: 681b ldr r3, [r3, #0]
|
|
800346a: 699b ldr r3, [r3, #24]
|
|
800346c: 61bb str r3, [r7, #24]
|
|
uint32_t error_code = 0;
|
|
800346e: 2300 movs r3, #0
|
|
8003470: 623b str r3, [r7, #32]
|
|
uint32_t tickstart = Tickstart;
|
|
8003472: 687b ldr r3, [r7, #4]
|
|
8003474: 61fb str r3, [r7, #28]
|
|
uint32_t tmp1;
|
|
HAL_I2C_ModeTypeDef tmp2;
|
|
|
|
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF))
|
|
8003476: 69bb ldr r3, [r7, #24]
|
|
8003478: f003 0310 and.w r3, r3, #16
|
|
800347c: 2b00 cmp r3, #0
|
|
800347e: d068 beq.n 8003552 <I2C_IsErrorOccurred+0xfe>
|
|
{
|
|
/* Clear NACKF Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
|
8003480: 68fb ldr r3, [r7, #12]
|
|
8003482: 681b ldr r3, [r3, #0]
|
|
8003484: 2210 movs r2, #16
|
|
8003486: 61da str r2, [r3, #28]
|
|
|
|
/* Wait until STOP Flag is set or timeout occurred */
|
|
/* AutoEnd should be initiate after AF */
|
|
while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
|
|
8003488: e049 b.n 800351e <I2C_IsErrorOccurred+0xca>
|
|
{
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
800348a: 68bb ldr r3, [r7, #8]
|
|
800348c: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8003490: d045 beq.n 800351e <I2C_IsErrorOccurred+0xca>
|
|
{
|
|
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
|
|
8003492: f7fe ffe3 bl 800245c <HAL_GetTick>
|
|
8003496: 4602 mov r2, r0
|
|
8003498: 69fb ldr r3, [r7, #28]
|
|
800349a: 1ad3 subs r3, r2, r3
|
|
800349c: 68ba ldr r2, [r7, #8]
|
|
800349e: 429a cmp r2, r3
|
|
80034a0: d302 bcc.n 80034a8 <I2C_IsErrorOccurred+0x54>
|
|
80034a2: 68bb ldr r3, [r7, #8]
|
|
80034a4: 2b00 cmp r3, #0
|
|
80034a6: d13a bne.n 800351e <I2C_IsErrorOccurred+0xca>
|
|
{
|
|
tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP);
|
|
80034a8: 68fb ldr r3, [r7, #12]
|
|
80034aa: 681b ldr r3, [r3, #0]
|
|
80034ac: 685b ldr r3, [r3, #4]
|
|
80034ae: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
80034b2: 617b str r3, [r7, #20]
|
|
tmp2 = hi2c->Mode;
|
|
80034b4: 68fb ldr r3, [r7, #12]
|
|
80034b6: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
|
|
80034ba: 74fb strb r3, [r7, #19]
|
|
|
|
/* In case of I2C still busy, try to regenerate a STOP manually */
|
|
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \
|
|
80034bc: 68fb ldr r3, [r7, #12]
|
|
80034be: 681b ldr r3, [r3, #0]
|
|
80034c0: 699b ldr r3, [r3, #24]
|
|
80034c2: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
80034c6: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
80034ca: d121 bne.n 8003510 <I2C_IsErrorOccurred+0xbc>
|
|
80034cc: 697b ldr r3, [r7, #20]
|
|
80034ce: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
|
|
80034d2: d01d beq.n 8003510 <I2C_IsErrorOccurred+0xbc>
|
|
(tmp1 != I2C_CR2_STOP) && \
|
|
80034d4: 7cfb ldrb r3, [r7, #19]
|
|
80034d6: 2b20 cmp r3, #32
|
|
80034d8: d01a beq.n 8003510 <I2C_IsErrorOccurred+0xbc>
|
|
(tmp2 != HAL_I2C_MODE_SLAVE))
|
|
{
|
|
/* Generate Stop */
|
|
hi2c->Instance->CR2 |= I2C_CR2_STOP;
|
|
80034da: 68fb ldr r3, [r7, #12]
|
|
80034dc: 681b ldr r3, [r3, #0]
|
|
80034de: 685a ldr r2, [r3, #4]
|
|
80034e0: 68fb ldr r3, [r7, #12]
|
|
80034e2: 681b ldr r3, [r3, #0]
|
|
80034e4: f442 4280 orr.w r2, r2, #16384 @ 0x4000
|
|
80034e8: 605a str r2, [r3, #4]
|
|
|
|
/* Update Tick with new reference */
|
|
tickstart = HAL_GetTick();
|
|
80034ea: f7fe ffb7 bl 800245c <HAL_GetTick>
|
|
80034ee: 61f8 str r0, [r7, #28]
|
|
}
|
|
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
|
|
80034f0: e00e b.n 8003510 <I2C_IsErrorOccurred+0xbc>
|
|
{
|
|
/* Check for the Timeout */
|
|
if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF)
|
|
80034f2: f7fe ffb3 bl 800245c <HAL_GetTick>
|
|
80034f6: 4602 mov r2, r0
|
|
80034f8: 69fb ldr r3, [r7, #28]
|
|
80034fa: 1ad3 subs r3, r2, r3
|
|
80034fc: 2b19 cmp r3, #25
|
|
80034fe: d907 bls.n 8003510 <I2C_IsErrorOccurred+0xbc>
|
|
{
|
|
error_code |= HAL_I2C_ERROR_TIMEOUT;
|
|
8003500: 6a3b ldr r3, [r7, #32]
|
|
8003502: f043 0320 orr.w r3, r3, #32
|
|
8003506: 623b str r3, [r7, #32]
|
|
|
|
status = HAL_ERROR;
|
|
8003508: 2301 movs r3, #1
|
|
800350a: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
|
|
break;
|
|
800350e: e006 b.n 800351e <I2C_IsErrorOccurred+0xca>
|
|
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
|
|
8003510: 68fb ldr r3, [r7, #12]
|
|
8003512: 681b ldr r3, [r3, #0]
|
|
8003514: 699b ldr r3, [r3, #24]
|
|
8003516: f003 0320 and.w r3, r3, #32
|
|
800351a: 2b20 cmp r3, #32
|
|
800351c: d1e9 bne.n 80034f2 <I2C_IsErrorOccurred+0x9e>
|
|
while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK))
|
|
800351e: 68fb ldr r3, [r7, #12]
|
|
8003520: 681b ldr r3, [r3, #0]
|
|
8003522: 699b ldr r3, [r3, #24]
|
|
8003524: f003 0320 and.w r3, r3, #32
|
|
8003528: 2b20 cmp r3, #32
|
|
800352a: d003 beq.n 8003534 <I2C_IsErrorOccurred+0xe0>
|
|
800352c: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
8003530: 2b00 cmp r3, #0
|
|
8003532: d0aa beq.n 800348a <I2C_IsErrorOccurred+0x36>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* In case STOP Flag is detected, clear it */
|
|
if (status == HAL_OK)
|
|
8003534: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
8003538: 2b00 cmp r3, #0
|
|
800353a: d103 bne.n 8003544 <I2C_IsErrorOccurred+0xf0>
|
|
{
|
|
/* Clear STOP Flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
|
800353c: 68fb ldr r3, [r7, #12]
|
|
800353e: 681b ldr r3, [r3, #0]
|
|
8003540: 2220 movs r2, #32
|
|
8003542: 61da str r2, [r3, #28]
|
|
}
|
|
|
|
error_code |= HAL_I2C_ERROR_AF;
|
|
8003544: 6a3b ldr r3, [r7, #32]
|
|
8003546: f043 0304 orr.w r3, r3, #4
|
|
800354a: 623b str r3, [r7, #32]
|
|
|
|
status = HAL_ERROR;
|
|
800354c: 2301 movs r3, #1
|
|
800354e: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
}
|
|
|
|
/* Refresh Content of Status register */
|
|
itflag = hi2c->Instance->ISR;
|
|
8003552: 68fb ldr r3, [r7, #12]
|
|
8003554: 681b ldr r3, [r3, #0]
|
|
8003556: 699b ldr r3, [r3, #24]
|
|
8003558: 61bb str r3, [r7, #24]
|
|
|
|
/* Then verify if an additional errors occurs */
|
|
/* Check if a Bus error occurred */
|
|
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR))
|
|
800355a: 69bb ldr r3, [r7, #24]
|
|
800355c: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8003560: 2b00 cmp r3, #0
|
|
8003562: d00b beq.n 800357c <I2C_IsErrorOccurred+0x128>
|
|
{
|
|
error_code |= HAL_I2C_ERROR_BERR;
|
|
8003564: 6a3b ldr r3, [r7, #32]
|
|
8003566: f043 0301 orr.w r3, r3, #1
|
|
800356a: 623b str r3, [r7, #32]
|
|
|
|
/* Clear BERR flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
|
|
800356c: 68fb ldr r3, [r7, #12]
|
|
800356e: 681b ldr r3, [r3, #0]
|
|
8003570: f44f 7280 mov.w r2, #256 @ 0x100
|
|
8003574: 61da str r2, [r3, #28]
|
|
|
|
status = HAL_ERROR;
|
|
8003576: 2301 movs r3, #1
|
|
8003578: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
}
|
|
|
|
/* Check if an Over-Run/Under-Run error occurred */
|
|
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR))
|
|
800357c: 69bb ldr r3, [r7, #24]
|
|
800357e: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8003582: 2b00 cmp r3, #0
|
|
8003584: d00b beq.n 800359e <I2C_IsErrorOccurred+0x14a>
|
|
{
|
|
error_code |= HAL_I2C_ERROR_OVR;
|
|
8003586: 6a3b ldr r3, [r7, #32]
|
|
8003588: f043 0308 orr.w r3, r3, #8
|
|
800358c: 623b str r3, [r7, #32]
|
|
|
|
/* Clear OVR flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
|
|
800358e: 68fb ldr r3, [r7, #12]
|
|
8003590: 681b ldr r3, [r3, #0]
|
|
8003592: f44f 6280 mov.w r2, #1024 @ 0x400
|
|
8003596: 61da str r2, [r3, #28]
|
|
|
|
status = HAL_ERROR;
|
|
8003598: 2301 movs r3, #1
|
|
800359a: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
}
|
|
|
|
/* Check if an Arbitration Loss error occurred */
|
|
if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO))
|
|
800359e: 69bb ldr r3, [r7, #24]
|
|
80035a0: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
80035a4: 2b00 cmp r3, #0
|
|
80035a6: d00b beq.n 80035c0 <I2C_IsErrorOccurred+0x16c>
|
|
{
|
|
error_code |= HAL_I2C_ERROR_ARLO;
|
|
80035a8: 6a3b ldr r3, [r7, #32]
|
|
80035aa: f043 0302 orr.w r3, r3, #2
|
|
80035ae: 623b str r3, [r7, #32]
|
|
|
|
/* Clear ARLO flag */
|
|
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
|
|
80035b0: 68fb ldr r3, [r7, #12]
|
|
80035b2: 681b ldr r3, [r3, #0]
|
|
80035b4: f44f 7200 mov.w r2, #512 @ 0x200
|
|
80035b8: 61da str r2, [r3, #28]
|
|
|
|
status = HAL_ERROR;
|
|
80035ba: 2301 movs r3, #1
|
|
80035bc: f887 3027 strb.w r3, [r7, #39] @ 0x27
|
|
}
|
|
|
|
if (status != HAL_OK)
|
|
80035c0: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
80035c4: 2b00 cmp r3, #0
|
|
80035c6: d01c beq.n 8003602 <I2C_IsErrorOccurred+0x1ae>
|
|
{
|
|
/* Flush TX register */
|
|
I2C_Flush_TXDR(hi2c);
|
|
80035c8: 68f8 ldr r0, [r7, #12]
|
|
80035ca: f7ff fe3b bl 8003244 <I2C_Flush_TXDR>
|
|
|
|
/* Clear Configuration Register 2 */
|
|
I2C_RESET_CR2(hi2c);
|
|
80035ce: 68fb ldr r3, [r7, #12]
|
|
80035d0: 681b ldr r3, [r3, #0]
|
|
80035d2: 6859 ldr r1, [r3, #4]
|
|
80035d4: 68fb ldr r3, [r7, #12]
|
|
80035d6: 681a ldr r2, [r3, #0]
|
|
80035d8: 4b0d ldr r3, [pc, #52] @ (8003610 <I2C_IsErrorOccurred+0x1bc>)
|
|
80035da: 400b ands r3, r1
|
|
80035dc: 6053 str r3, [r2, #4]
|
|
|
|
hi2c->ErrorCode |= error_code;
|
|
80035de: 68fb ldr r3, [r7, #12]
|
|
80035e0: 6c5a ldr r2, [r3, #68] @ 0x44
|
|
80035e2: 6a3b ldr r3, [r7, #32]
|
|
80035e4: 431a orrs r2, r3
|
|
80035e6: 68fb ldr r3, [r7, #12]
|
|
80035e8: 645a str r2, [r3, #68] @ 0x44
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
80035ea: 68fb ldr r3, [r7, #12]
|
|
80035ec: 2220 movs r2, #32
|
|
80035ee: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
hi2c->Mode = HAL_I2C_MODE_NONE;
|
|
80035f2: 68fb ldr r3, [r7, #12]
|
|
80035f4: 2200 movs r2, #0
|
|
80035f6: f883 2042 strb.w r2, [r3, #66] @ 0x42
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
80035fa: 68fb ldr r3, [r7, #12]
|
|
80035fc: 2200 movs r2, #0
|
|
80035fe: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
}
|
|
|
|
return status;
|
|
8003602: f897 3027 ldrb.w r3, [r7, #39] @ 0x27
|
|
}
|
|
8003606: 4618 mov r0, r3
|
|
8003608: 3728 adds r7, #40 @ 0x28
|
|
800360a: 46bd mov sp, r7
|
|
800360c: bd80 pop {r7, pc}
|
|
800360e: bf00 nop
|
|
8003610: fe00e800 .word 0xfe00e800
|
|
|
|
08003614 <I2C_TransferConfig>:
|
|
* @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
|
|
* @retval None
|
|
*/
|
|
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode,
|
|
uint32_t Request)
|
|
{
|
|
8003614: b480 push {r7}
|
|
8003616: b087 sub sp, #28
|
|
8003618: af00 add r7, sp, #0
|
|
800361a: 60f8 str r0, [r7, #12]
|
|
800361c: 607b str r3, [r7, #4]
|
|
800361e: 460b mov r3, r1
|
|
8003620: 817b strh r3, [r7, #10]
|
|
8003622: 4613 mov r3, r2
|
|
8003624: 727b strb r3, [r7, #9]
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
assert_param(IS_TRANSFER_MODE(Mode));
|
|
assert_param(IS_TRANSFER_REQUEST(Request));
|
|
|
|
/* Declaration of tmp to prevent undefined behavior of volatile usage */
|
|
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
|
|
8003626: 897b ldrh r3, [r7, #10]
|
|
8003628: f3c3 0209 ubfx r2, r3, #0, #10
|
|
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
|
|
800362c: 7a7b ldrb r3, [r7, #9]
|
|
800362e: 041b lsls r3, r3, #16
|
|
8003630: f403 037f and.w r3, r3, #16711680 @ 0xff0000
|
|
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
|
|
8003634: 431a orrs r2, r3
|
|
(((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
|
|
8003636: 687b ldr r3, [r7, #4]
|
|
8003638: 431a orrs r2, r3
|
|
uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \
|
|
800363a: 6a3b ldr r3, [r7, #32]
|
|
800363c: 4313 orrs r3, r2
|
|
800363e: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
|
|
8003642: 617b str r3, [r7, #20]
|
|
(uint32_t)Mode | (uint32_t)Request) & (~0x80000000U));
|
|
|
|
/* update CR2 register */
|
|
MODIFY_REG(hi2c->Instance->CR2, \
|
|
8003644: 68fb ldr r3, [r7, #12]
|
|
8003646: 681b ldr r3, [r3, #0]
|
|
8003648: 685a ldr r2, [r3, #4]
|
|
800364a: 6a3b ldr r3, [r7, #32]
|
|
800364c: 0d5b lsrs r3, r3, #21
|
|
800364e: f403 6180 and.w r1, r3, #1024 @ 0x400
|
|
8003652: 4b08 ldr r3, [pc, #32] @ (8003674 <I2C_TransferConfig+0x60>)
|
|
8003654: 430b orrs r3, r1
|
|
8003656: 43db mvns r3, r3
|
|
8003658: ea02 0103 and.w r1, r2, r3
|
|
800365c: 68fb ldr r3, [r7, #12]
|
|
800365e: 681b ldr r3, [r3, #0]
|
|
8003660: 697a ldr r2, [r7, #20]
|
|
8003662: 430a orrs r2, r1
|
|
8003664: 605a str r2, [r3, #4]
|
|
((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \
|
|
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \
|
|
I2C_CR2_START | I2C_CR2_STOP)), tmp);
|
|
}
|
|
8003666: bf00 nop
|
|
8003668: 371c adds r7, #28
|
|
800366a: 46bd mov sp, r7
|
|
800366c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003670: 4770 bx lr
|
|
8003672: bf00 nop
|
|
8003674: 03ff63ff .word 0x03ff63ff
|
|
|
|
08003678 <HAL_I2CEx_ConfigAnalogFilter>:
|
|
* the configuration information for the specified I2Cx peripheral.
|
|
* @param AnalogFilter New state of the Analog filter.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
|
|
{
|
|
8003678: b480 push {r7}
|
|
800367a: b083 sub sp, #12
|
|
800367c: af00 add r7, sp, #0
|
|
800367e: 6078 str r0, [r7, #4]
|
|
8003680: 6039 str r1, [r7, #0]
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
8003682: 687b ldr r3, [r7, #4]
|
|
8003684: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
8003688: b2db uxtb r3, r3
|
|
800368a: 2b20 cmp r3, #32
|
|
800368c: d138 bne.n 8003700 <HAL_I2CEx_ConfigAnalogFilter+0x88>
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
800368e: 687b ldr r3, [r7, #4]
|
|
8003690: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
8003694: 2b01 cmp r3, #1
|
|
8003696: d101 bne.n 800369c <HAL_I2CEx_ConfigAnalogFilter+0x24>
|
|
8003698: 2302 movs r3, #2
|
|
800369a: e032 b.n 8003702 <HAL_I2CEx_ConfigAnalogFilter+0x8a>
|
|
800369c: 687b ldr r3, [r7, #4]
|
|
800369e: 2201 movs r2, #1
|
|
80036a0: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
80036a4: 687b ldr r3, [r7, #4]
|
|
80036a6: 2224 movs r2, #36 @ 0x24
|
|
80036a8: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
80036ac: 687b ldr r3, [r7, #4]
|
|
80036ae: 681b ldr r3, [r3, #0]
|
|
80036b0: 681a ldr r2, [r3, #0]
|
|
80036b2: 687b ldr r3, [r7, #4]
|
|
80036b4: 681b ldr r3, [r3, #0]
|
|
80036b6: f022 0201 bic.w r2, r2, #1
|
|
80036ba: 601a str r2, [r3, #0]
|
|
|
|
/* Reset I2Cx ANOFF bit */
|
|
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
|
|
80036bc: 687b ldr r3, [r7, #4]
|
|
80036be: 681b ldr r3, [r3, #0]
|
|
80036c0: 681a ldr r2, [r3, #0]
|
|
80036c2: 687b ldr r3, [r7, #4]
|
|
80036c4: 681b ldr r3, [r3, #0]
|
|
80036c6: f422 5280 bic.w r2, r2, #4096 @ 0x1000
|
|
80036ca: 601a str r2, [r3, #0]
|
|
|
|
/* Set analog filter bit*/
|
|
hi2c->Instance->CR1 |= AnalogFilter;
|
|
80036cc: 687b ldr r3, [r7, #4]
|
|
80036ce: 681b ldr r3, [r3, #0]
|
|
80036d0: 6819 ldr r1, [r3, #0]
|
|
80036d2: 687b ldr r3, [r7, #4]
|
|
80036d4: 681b ldr r3, [r3, #0]
|
|
80036d6: 683a ldr r2, [r7, #0]
|
|
80036d8: 430a orrs r2, r1
|
|
80036da: 601a str r2, [r3, #0]
|
|
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
80036dc: 687b ldr r3, [r7, #4]
|
|
80036de: 681b ldr r3, [r3, #0]
|
|
80036e0: 681a ldr r2, [r3, #0]
|
|
80036e2: 687b ldr r3, [r7, #4]
|
|
80036e4: 681b ldr r3, [r3, #0]
|
|
80036e6: f042 0201 orr.w r2, r2, #1
|
|
80036ea: 601a str r2, [r3, #0]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
80036ec: 687b ldr r3, [r7, #4]
|
|
80036ee: 2220 movs r2, #32
|
|
80036f0: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
80036f4: 687b ldr r3, [r7, #4]
|
|
80036f6: 2200 movs r2, #0
|
|
80036f8: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_OK;
|
|
80036fc: 2300 movs r3, #0
|
|
80036fe: e000 b.n 8003702 <HAL_I2CEx_ConfigAnalogFilter+0x8a>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8003700: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8003702: 4618 mov r0, r3
|
|
8003704: 370c adds r7, #12
|
|
8003706: 46bd mov sp, r7
|
|
8003708: f85d 7b04 ldr.w r7, [sp], #4
|
|
800370c: 4770 bx lr
|
|
|
|
0800370e <HAL_I2CEx_ConfigDigitalFilter>:
|
|
* the configuration information for the specified I2Cx peripheral.
|
|
* @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
|
|
{
|
|
800370e: b480 push {r7}
|
|
8003710: b085 sub sp, #20
|
|
8003712: af00 add r7, sp, #0
|
|
8003714: 6078 str r0, [r7, #4]
|
|
8003716: 6039 str r1, [r7, #0]
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
|
|
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
|
|
|
|
if (hi2c->State == HAL_I2C_STATE_READY)
|
|
8003718: 687b ldr r3, [r7, #4]
|
|
800371a: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
|
|
800371e: b2db uxtb r3, r3
|
|
8003720: 2b20 cmp r3, #32
|
|
8003722: d139 bne.n 8003798 <HAL_I2CEx_ConfigDigitalFilter+0x8a>
|
|
{
|
|
/* Process Locked */
|
|
__HAL_LOCK(hi2c);
|
|
8003724: 687b ldr r3, [r7, #4]
|
|
8003726: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
|
|
800372a: 2b01 cmp r3, #1
|
|
800372c: d101 bne.n 8003732 <HAL_I2CEx_ConfigDigitalFilter+0x24>
|
|
800372e: 2302 movs r3, #2
|
|
8003730: e033 b.n 800379a <HAL_I2CEx_ConfigDigitalFilter+0x8c>
|
|
8003732: 687b ldr r3, [r7, #4]
|
|
8003734: 2201 movs r2, #1
|
|
8003736: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
hi2c->State = HAL_I2C_STATE_BUSY;
|
|
800373a: 687b ldr r3, [r7, #4]
|
|
800373c: 2224 movs r2, #36 @ 0x24
|
|
800373e: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Disable the selected I2C peripheral */
|
|
__HAL_I2C_DISABLE(hi2c);
|
|
8003742: 687b ldr r3, [r7, #4]
|
|
8003744: 681b ldr r3, [r3, #0]
|
|
8003746: 681a ldr r2, [r3, #0]
|
|
8003748: 687b ldr r3, [r7, #4]
|
|
800374a: 681b ldr r3, [r3, #0]
|
|
800374c: f022 0201 bic.w r2, r2, #1
|
|
8003750: 601a str r2, [r3, #0]
|
|
|
|
/* Get the old register value */
|
|
tmpreg = hi2c->Instance->CR1;
|
|
8003752: 687b ldr r3, [r7, #4]
|
|
8003754: 681b ldr r3, [r3, #0]
|
|
8003756: 681b ldr r3, [r3, #0]
|
|
8003758: 60fb str r3, [r7, #12]
|
|
|
|
/* Reset I2Cx DNF bits [11:8] */
|
|
tmpreg &= ~(I2C_CR1_DNF);
|
|
800375a: 68fb ldr r3, [r7, #12]
|
|
800375c: f423 6370 bic.w r3, r3, #3840 @ 0xf00
|
|
8003760: 60fb str r3, [r7, #12]
|
|
|
|
/* Set I2Cx DNF coefficient */
|
|
tmpreg |= DigitalFilter << 8U;
|
|
8003762: 683b ldr r3, [r7, #0]
|
|
8003764: 021b lsls r3, r3, #8
|
|
8003766: 68fa ldr r2, [r7, #12]
|
|
8003768: 4313 orrs r3, r2
|
|
800376a: 60fb str r3, [r7, #12]
|
|
|
|
/* Store the new register value */
|
|
hi2c->Instance->CR1 = tmpreg;
|
|
800376c: 687b ldr r3, [r7, #4]
|
|
800376e: 681b ldr r3, [r3, #0]
|
|
8003770: 68fa ldr r2, [r7, #12]
|
|
8003772: 601a str r2, [r3, #0]
|
|
|
|
__HAL_I2C_ENABLE(hi2c);
|
|
8003774: 687b ldr r3, [r7, #4]
|
|
8003776: 681b ldr r3, [r3, #0]
|
|
8003778: 681a ldr r2, [r3, #0]
|
|
800377a: 687b ldr r3, [r7, #4]
|
|
800377c: 681b ldr r3, [r3, #0]
|
|
800377e: f042 0201 orr.w r2, r2, #1
|
|
8003782: 601a str r2, [r3, #0]
|
|
|
|
hi2c->State = HAL_I2C_STATE_READY;
|
|
8003784: 687b ldr r3, [r7, #4]
|
|
8003786: 2220 movs r2, #32
|
|
8003788: f883 2041 strb.w r2, [r3, #65] @ 0x41
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(hi2c);
|
|
800378c: 687b ldr r3, [r7, #4]
|
|
800378e: 2200 movs r2, #0
|
|
8003790: f883 2040 strb.w r2, [r3, #64] @ 0x40
|
|
|
|
return HAL_OK;
|
|
8003794: 2300 movs r3, #0
|
|
8003796: e000 b.n 800379a <HAL_I2CEx_ConfigDigitalFilter+0x8c>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8003798: 2302 movs r3, #2
|
|
}
|
|
}
|
|
800379a: 4618 mov r0, r3
|
|
800379c: 3714 adds r7, #20
|
|
800379e: 46bd mov sp, r7
|
|
80037a0: f85d 7b04 ldr.w r7, [sp], #4
|
|
80037a4: 4770 bx lr
|
|
...
|
|
|
|
080037a8 <HAL_PWREx_GetVoltageRange>:
|
|
* @brief Return Voltage Scaling Range.
|
|
* @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWR_REGULATOR_VOLTAGE_SCALE2
|
|
* or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable)
|
|
*/
|
|
uint32_t HAL_PWREx_GetVoltageRange(void)
|
|
{
|
|
80037a8: b480 push {r7}
|
|
80037aa: af00 add r7, sp, #0
|
|
else
|
|
{
|
|
return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST;
|
|
}
|
|
#else
|
|
return (PWR->CR1 & PWR_CR1_VOS);
|
|
80037ac: 4b04 ldr r3, [pc, #16] @ (80037c0 <HAL_PWREx_GetVoltageRange+0x18>)
|
|
80037ae: 681b ldr r3, [r3, #0]
|
|
80037b0: f403 63c0 and.w r3, r3, #1536 @ 0x600
|
|
#endif
|
|
}
|
|
80037b4: 4618 mov r0, r3
|
|
80037b6: 46bd mov sp, r7
|
|
80037b8: f85d 7b04 ldr.w r7, [sp], #4
|
|
80037bc: 4770 bx lr
|
|
80037be: bf00 nop
|
|
80037c0: 40007000 .word 0x40007000
|
|
|
|
080037c4 <HAL_PWREx_ControlVoltageScaling>:
|
|
* cleared before returning the status. If the flag is not cleared within
|
|
* 50 microseconds, HAL_TIMEOUT status is reported.
|
|
* @retval HAL Status
|
|
*/
|
|
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
|
|
{
|
|
80037c4: b480 push {r7}
|
|
80037c6: b085 sub sp, #20
|
|
80037c8: af00 add r7, sp, #0
|
|
80037ca: 6078 str r0, [r7, #4]
|
|
}
|
|
|
|
#else
|
|
|
|
/* If Set Range 1 */
|
|
if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
|
|
80037cc: 687b ldr r3, [r7, #4]
|
|
80037ce: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
80037d2: d130 bne.n 8003836 <HAL_PWREx_ControlVoltageScaling+0x72>
|
|
{
|
|
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1)
|
|
80037d4: 4b23 ldr r3, [pc, #140] @ (8003864 <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
80037d6: 681b ldr r3, [r3, #0]
|
|
80037d8: f403 63c0 and.w r3, r3, #1536 @ 0x600
|
|
80037dc: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
80037e0: d038 beq.n 8003854 <HAL_PWREx_ControlVoltageScaling+0x90>
|
|
{
|
|
/* Set Range 1 */
|
|
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
|
|
80037e2: 4b20 ldr r3, [pc, #128] @ (8003864 <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
80037e4: 681b ldr r3, [r3, #0]
|
|
80037e6: f423 63c0 bic.w r3, r3, #1536 @ 0x600
|
|
80037ea: 4a1e ldr r2, [pc, #120] @ (8003864 <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
80037ec: f443 7300 orr.w r3, r3, #512 @ 0x200
|
|
80037f0: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait until VOSF is cleared */
|
|
wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
|
|
80037f2: 4b1d ldr r3, [pc, #116] @ (8003868 <HAL_PWREx_ControlVoltageScaling+0xa4>)
|
|
80037f4: 681b ldr r3, [r3, #0]
|
|
80037f6: 2232 movs r2, #50 @ 0x32
|
|
80037f8: fb02 f303 mul.w r3, r2, r3
|
|
80037fc: 4a1b ldr r2, [pc, #108] @ (800386c <HAL_PWREx_ControlVoltageScaling+0xa8>)
|
|
80037fe: fba2 2303 umull r2, r3, r2, r3
|
|
8003802: 0c9b lsrs r3, r3, #18
|
|
8003804: 3301 adds r3, #1
|
|
8003806: 60fb str r3, [r7, #12]
|
|
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
|
|
8003808: e002 b.n 8003810 <HAL_PWREx_ControlVoltageScaling+0x4c>
|
|
{
|
|
wait_loop_index--;
|
|
800380a: 68fb ldr r3, [r7, #12]
|
|
800380c: 3b01 subs r3, #1
|
|
800380e: 60fb str r3, [r7, #12]
|
|
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
|
|
8003810: 4b14 ldr r3, [pc, #80] @ (8003864 <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
8003812: 695b ldr r3, [r3, #20]
|
|
8003814: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8003818: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
800381c: d102 bne.n 8003824 <HAL_PWREx_ControlVoltageScaling+0x60>
|
|
800381e: 68fb ldr r3, [r7, #12]
|
|
8003820: 2b00 cmp r3, #0
|
|
8003822: d1f2 bne.n 800380a <HAL_PWREx_ControlVoltageScaling+0x46>
|
|
}
|
|
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
|
|
8003824: 4b0f ldr r3, [pc, #60] @ (8003864 <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
8003826: 695b ldr r3, [r3, #20]
|
|
8003828: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
800382c: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
8003830: d110 bne.n 8003854 <HAL_PWREx_ControlVoltageScaling+0x90>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003832: 2303 movs r3, #3
|
|
8003834: e00f b.n 8003856 <HAL_PWREx_ControlVoltageScaling+0x92>
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2)
|
|
8003836: 4b0b ldr r3, [pc, #44] @ (8003864 <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
8003838: 681b ldr r3, [r3, #0]
|
|
800383a: f403 63c0 and.w r3, r3, #1536 @ 0x600
|
|
800383e: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
8003842: d007 beq.n 8003854 <HAL_PWREx_ControlVoltageScaling+0x90>
|
|
{
|
|
/* Set Range 2 */
|
|
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
|
|
8003844: 4b07 ldr r3, [pc, #28] @ (8003864 <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
8003846: 681b ldr r3, [r3, #0]
|
|
8003848: f423 63c0 bic.w r3, r3, #1536 @ 0x600
|
|
800384c: 4a05 ldr r2, [pc, #20] @ (8003864 <HAL_PWREx_ControlVoltageScaling+0xa0>)
|
|
800384e: f443 6380 orr.w r3, r3, #1024 @ 0x400
|
|
8003852: 6013 str r3, [r2, #0]
|
|
/* No need to wait for VOSF to be cleared for this transition */
|
|
}
|
|
}
|
|
#endif
|
|
|
|
return HAL_OK;
|
|
8003854: 2300 movs r3, #0
|
|
}
|
|
8003856: 4618 mov r0, r3
|
|
8003858: 3714 adds r7, #20
|
|
800385a: 46bd mov sp, r7
|
|
800385c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8003860: 4770 bx lr
|
|
8003862: bf00 nop
|
|
8003864: 40007000 .word 0x40007000
|
|
8003868: 20000014 .word 0x20000014
|
|
800386c: 431bde83 .word 0x431bde83
|
|
|
|
08003870 <HAL_RCC_OscConfig>:
|
|
* @note If HSE failed to start, HSE should be disabled before recalling
|
|
HAL_RCC_OscConfig().
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
8003870: b580 push {r7, lr}
|
|
8003872: b088 sub sp, #32
|
|
8003874: af00 add r7, sp, #0
|
|
8003876: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
HAL_StatusTypeDef status;
|
|
uint32_t sysclk_source, pll_config;
|
|
|
|
/* Check Null pointer */
|
|
if(RCC_OscInitStruct == NULL)
|
|
8003878: 687b ldr r3, [r7, #4]
|
|
800387a: 2b00 cmp r3, #0
|
|
800387c: d101 bne.n 8003882 <HAL_RCC_OscConfig+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
800387e: 2301 movs r3, #1
|
|
8003880: e3ca b.n 8004018 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
|
|
|
|
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
8003882: 4b97 ldr r3, [pc, #604] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
8003884: 689b ldr r3, [r3, #8]
|
|
8003886: f003 030c and.w r3, r3, #12
|
|
800388a: 61bb str r3, [r7, #24]
|
|
pll_config = __HAL_RCC_GET_PLL_OSCSOURCE();
|
|
800388c: 4b94 ldr r3, [pc, #592] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
800388e: 68db ldr r3, [r3, #12]
|
|
8003890: f003 0303 and.w r3, r3, #3
|
|
8003894: 617b str r3, [r7, #20]
|
|
|
|
/*----------------------------- MSI Configuration --------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
|
|
8003896: 687b ldr r3, [r7, #4]
|
|
8003898: 681b ldr r3, [r3, #0]
|
|
800389a: f003 0310 and.w r3, r3, #16
|
|
800389e: 2b00 cmp r3, #0
|
|
80038a0: f000 80e4 beq.w 8003a6c <HAL_RCC_OscConfig+0x1fc>
|
|
assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
|
|
assert_param(IS_RCC_MSICALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue));
|
|
assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange));
|
|
|
|
/* Check if MSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
if((sysclk_source == RCC_CFGR_SWS_MSI) ||
|
|
80038a4: 69bb ldr r3, [r7, #24]
|
|
80038a6: 2b00 cmp r3, #0
|
|
80038a8: d007 beq.n 80038ba <HAL_RCC_OscConfig+0x4a>
|
|
80038aa: 69bb ldr r3, [r7, #24]
|
|
80038ac: 2b0c cmp r3, #12
|
|
80038ae: f040 808b bne.w 80039c8 <HAL_RCC_OscConfig+0x158>
|
|
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_MSI)))
|
|
80038b2: 697b ldr r3, [r7, #20]
|
|
80038b4: 2b01 cmp r3, #1
|
|
80038b6: f040 8087 bne.w 80039c8 <HAL_RCC_OscConfig+0x158>
|
|
{
|
|
if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
|
|
80038ba: 4b89 ldr r3, [pc, #548] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
80038bc: 681b ldr r3, [r3, #0]
|
|
80038be: f003 0302 and.w r3, r3, #2
|
|
80038c2: 2b00 cmp r3, #0
|
|
80038c4: d005 beq.n 80038d2 <HAL_RCC_OscConfig+0x62>
|
|
80038c6: 687b ldr r3, [r7, #4]
|
|
80038c8: 699b ldr r3, [r3, #24]
|
|
80038ca: 2b00 cmp r3, #0
|
|
80038cc: d101 bne.n 80038d2 <HAL_RCC_OscConfig+0x62>
|
|
{
|
|
return HAL_ERROR;
|
|
80038ce: 2301 movs r3, #1
|
|
80038d0: e3a2 b.n 8004018 <HAL_RCC_OscConfig+0x7a8>
|
|
else
|
|
{
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) and the supply voltage of the device. */
|
|
if(RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE())
|
|
80038d2: 687b ldr r3, [r7, #4]
|
|
80038d4: 6a1a ldr r2, [r3, #32]
|
|
80038d6: 4b82 ldr r3, [pc, #520] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
80038d8: 681b ldr r3, [r3, #0]
|
|
80038da: f003 0308 and.w r3, r3, #8
|
|
80038de: 2b00 cmp r3, #0
|
|
80038e0: d004 beq.n 80038ec <HAL_RCC_OscConfig+0x7c>
|
|
80038e2: 4b7f ldr r3, [pc, #508] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
80038e4: 681b ldr r3, [r3, #0]
|
|
80038e6: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
80038ea: e005 b.n 80038f8 <HAL_RCC_OscConfig+0x88>
|
|
80038ec: 4b7c ldr r3, [pc, #496] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
80038ee: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
80038f2: 091b lsrs r3, r3, #4
|
|
80038f4: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
80038f8: 4293 cmp r3, r2
|
|
80038fa: d223 bcs.n 8003944 <HAL_RCC_OscConfig+0xd4>
|
|
{
|
|
/* First increase number of wait states update if necessary */
|
|
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
|
|
80038fc: 687b ldr r3, [r7, #4]
|
|
80038fe: 6a1b ldr r3, [r3, #32]
|
|
8003900: 4618 mov r0, r3
|
|
8003902: f000 fd55 bl 80043b0 <RCC_SetFlashLatencyFromMSIRange>
|
|
8003906: 4603 mov r3, r0
|
|
8003908: 2b00 cmp r3, #0
|
|
800390a: d001 beq.n 8003910 <HAL_RCC_OscConfig+0xa0>
|
|
{
|
|
return HAL_ERROR;
|
|
800390c: 2301 movs r3, #1
|
|
800390e: e383 b.n 8004018 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
|
8003910: 4b73 ldr r3, [pc, #460] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
8003912: 681b ldr r3, [r3, #0]
|
|
8003914: 4a72 ldr r2, [pc, #456] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
8003916: f043 0308 orr.w r3, r3, #8
|
|
800391a: 6013 str r3, [r2, #0]
|
|
800391c: 4b70 ldr r3, [pc, #448] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
800391e: 681b ldr r3, [r3, #0]
|
|
8003920: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8003924: 687b ldr r3, [r7, #4]
|
|
8003926: 6a1b ldr r3, [r3, #32]
|
|
8003928: 496d ldr r1, [pc, #436] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
800392a: 4313 orrs r3, r2
|
|
800392c: 600b str r3, [r1, #0]
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
|
800392e: 4b6c ldr r3, [pc, #432] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
8003930: 685b ldr r3, [r3, #4]
|
|
8003932: f423 427f bic.w r2, r3, #65280 @ 0xff00
|
|
8003936: 687b ldr r3, [r7, #4]
|
|
8003938: 69db ldr r3, [r3, #28]
|
|
800393a: 021b lsls r3, r3, #8
|
|
800393c: 4968 ldr r1, [pc, #416] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
800393e: 4313 orrs r3, r2
|
|
8003940: 604b str r3, [r1, #4]
|
|
8003942: e025 b.n 8003990 <HAL_RCC_OscConfig+0x120>
|
|
}
|
|
else
|
|
{
|
|
/* Else, keep current flash latency while decreasing applies */
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
|
8003944: 4b66 ldr r3, [pc, #408] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
8003946: 681b ldr r3, [r3, #0]
|
|
8003948: 4a65 ldr r2, [pc, #404] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
800394a: f043 0308 orr.w r3, r3, #8
|
|
800394e: 6013 str r3, [r2, #0]
|
|
8003950: 4b63 ldr r3, [pc, #396] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
8003952: 681b ldr r3, [r3, #0]
|
|
8003954: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8003958: 687b ldr r3, [r7, #4]
|
|
800395a: 6a1b ldr r3, [r3, #32]
|
|
800395c: 4960 ldr r1, [pc, #384] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
800395e: 4313 orrs r3, r2
|
|
8003960: 600b str r3, [r1, #0]
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
|
8003962: 4b5f ldr r3, [pc, #380] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
8003964: 685b ldr r3, [r3, #4]
|
|
8003966: f423 427f bic.w r2, r3, #65280 @ 0xff00
|
|
800396a: 687b ldr r3, [r7, #4]
|
|
800396c: 69db ldr r3, [r3, #28]
|
|
800396e: 021b lsls r3, r3, #8
|
|
8003970: 495b ldr r1, [pc, #364] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
8003972: 4313 orrs r3, r2
|
|
8003974: 604b str r3, [r1, #4]
|
|
|
|
/* Decrease number of wait states update if necessary */
|
|
/* Only possible when MSI is the System clock source */
|
|
if(sysclk_source == RCC_CFGR_SWS_MSI)
|
|
8003976: 69bb ldr r3, [r7, #24]
|
|
8003978: 2b00 cmp r3, #0
|
|
800397a: d109 bne.n 8003990 <HAL_RCC_OscConfig+0x120>
|
|
{
|
|
if(RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK)
|
|
800397c: 687b ldr r3, [r7, #4]
|
|
800397e: 6a1b ldr r3, [r3, #32]
|
|
8003980: 4618 mov r0, r3
|
|
8003982: f000 fd15 bl 80043b0 <RCC_SetFlashLatencyFromMSIRange>
|
|
8003986: 4603 mov r3, r0
|
|
8003988: 2b00 cmp r3, #0
|
|
800398a: d001 beq.n 8003990 <HAL_RCC_OscConfig+0x120>
|
|
{
|
|
return HAL_ERROR;
|
|
800398c: 2301 movs r3, #1
|
|
800398e: e343 b.n 8004018 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
|
|
8003990: f000 fc4a bl 8004228 <HAL_RCC_GetSysClockFreq>
|
|
8003994: 4602 mov r2, r0
|
|
8003996: 4b52 ldr r3, [pc, #328] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
8003998: 689b ldr r3, [r3, #8]
|
|
800399a: 091b lsrs r3, r3, #4
|
|
800399c: f003 030f and.w r3, r3, #15
|
|
80039a0: 4950 ldr r1, [pc, #320] @ (8003ae4 <HAL_RCC_OscConfig+0x274>)
|
|
80039a2: 5ccb ldrb r3, [r1, r3]
|
|
80039a4: f003 031f and.w r3, r3, #31
|
|
80039a8: fa22 f303 lsr.w r3, r2, r3
|
|
80039ac: 4a4e ldr r2, [pc, #312] @ (8003ae8 <HAL_RCC_OscConfig+0x278>)
|
|
80039ae: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
status = HAL_InitTick(uwTickPrio);
|
|
80039b0: 4b4e ldr r3, [pc, #312] @ (8003aec <HAL_RCC_OscConfig+0x27c>)
|
|
80039b2: 681b ldr r3, [r3, #0]
|
|
80039b4: 4618 mov r0, r3
|
|
80039b6: f7fe fd01 bl 80023bc <HAL_InitTick>
|
|
80039ba: 4603 mov r3, r0
|
|
80039bc: 73fb strb r3, [r7, #15]
|
|
if(status != HAL_OK)
|
|
80039be: 7bfb ldrb r3, [r7, #15]
|
|
80039c0: 2b00 cmp r3, #0
|
|
80039c2: d052 beq.n 8003a6a <HAL_RCC_OscConfig+0x1fa>
|
|
{
|
|
return status;
|
|
80039c4: 7bfb ldrb r3, [r7, #15]
|
|
80039c6: e327 b.n 8004018 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the MSI State */
|
|
if(RCC_OscInitStruct->MSIState != RCC_MSI_OFF)
|
|
80039c8: 687b ldr r3, [r7, #4]
|
|
80039ca: 699b ldr r3, [r3, #24]
|
|
80039cc: 2b00 cmp r3, #0
|
|
80039ce: d032 beq.n 8003a36 <HAL_RCC_OscConfig+0x1c6>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (MSI). */
|
|
__HAL_RCC_MSI_ENABLE();
|
|
80039d0: 4b43 ldr r3, [pc, #268] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
80039d2: 681b ldr r3, [r3, #0]
|
|
80039d4: 4a42 ldr r2, [pc, #264] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
80039d6: f043 0301 orr.w r3, r3, #1
|
|
80039da: 6013 str r3, [r2, #0]
|
|
|
|
/* Get timeout */
|
|
tickstart = HAL_GetTick();
|
|
80039dc: f7fe fd3e bl 800245c <HAL_GetTick>
|
|
80039e0: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till MSI is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
|
|
80039e2: e008 b.n 80039f6 <HAL_RCC_OscConfig+0x186>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
|
|
80039e4: f7fe fd3a bl 800245c <HAL_GetTick>
|
|
80039e8: 4602 mov r2, r0
|
|
80039ea: 693b ldr r3, [r7, #16]
|
|
80039ec: 1ad3 subs r3, r2, r3
|
|
80039ee: 2b02 cmp r3, #2
|
|
80039f0: d901 bls.n 80039f6 <HAL_RCC_OscConfig+0x186>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
80039f2: 2303 movs r3, #3
|
|
80039f4: e310 b.n 8004018 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
|
|
80039f6: 4b3a ldr r3, [pc, #232] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
80039f8: 681b ldr r3, [r3, #0]
|
|
80039fa: f003 0302 and.w r3, r3, #2
|
|
80039fe: 2b00 cmp r3, #0
|
|
8003a00: d0f0 beq.n 80039e4 <HAL_RCC_OscConfig+0x174>
|
|
}
|
|
}
|
|
/* Selects the Multiple Speed oscillator (MSI) clock range .*/
|
|
__HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
|
|
8003a02: 4b37 ldr r3, [pc, #220] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
8003a04: 681b ldr r3, [r3, #0]
|
|
8003a06: 4a36 ldr r2, [pc, #216] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
8003a08: f043 0308 orr.w r3, r3, #8
|
|
8003a0c: 6013 str r3, [r2, #0]
|
|
8003a0e: 4b34 ldr r3, [pc, #208] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
8003a10: 681b ldr r3, [r3, #0]
|
|
8003a12: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8003a16: 687b ldr r3, [r7, #4]
|
|
8003a18: 6a1b ldr r3, [r3, #32]
|
|
8003a1a: 4931 ldr r1, [pc, #196] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
8003a1c: 4313 orrs r3, r2
|
|
8003a1e: 600b str r3, [r1, #0]
|
|
/* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/
|
|
__HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
|
|
8003a20: 4b2f ldr r3, [pc, #188] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
8003a22: 685b ldr r3, [r3, #4]
|
|
8003a24: f423 427f bic.w r2, r3, #65280 @ 0xff00
|
|
8003a28: 687b ldr r3, [r7, #4]
|
|
8003a2a: 69db ldr r3, [r3, #28]
|
|
8003a2c: 021b lsls r3, r3, #8
|
|
8003a2e: 492c ldr r1, [pc, #176] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
8003a30: 4313 orrs r3, r2
|
|
8003a32: 604b str r3, [r1, #4]
|
|
8003a34: e01a b.n 8003a6c <HAL_RCC_OscConfig+0x1fc>
|
|
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (MSI). */
|
|
__HAL_RCC_MSI_DISABLE();
|
|
8003a36: 4b2a ldr r3, [pc, #168] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
8003a38: 681b ldr r3, [r3, #0]
|
|
8003a3a: 4a29 ldr r2, [pc, #164] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
8003a3c: f023 0301 bic.w r3, r3, #1
|
|
8003a40: 6013 str r3, [r2, #0]
|
|
|
|
/* Get timeout */
|
|
tickstart = HAL_GetTick();
|
|
8003a42: f7fe fd0b bl 800245c <HAL_GetTick>
|
|
8003a46: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till MSI is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
|
|
8003a48: e008 b.n 8003a5c <HAL_RCC_OscConfig+0x1ec>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
|
|
8003a4a: f7fe fd07 bl 800245c <HAL_GetTick>
|
|
8003a4e: 4602 mov r2, r0
|
|
8003a50: 693b ldr r3, [r7, #16]
|
|
8003a52: 1ad3 subs r3, r2, r3
|
|
8003a54: 2b02 cmp r3, #2
|
|
8003a56: d901 bls.n 8003a5c <HAL_RCC_OscConfig+0x1ec>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003a58: 2303 movs r3, #3
|
|
8003a5a: e2dd b.n 8004018 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U)
|
|
8003a5c: 4b20 ldr r3, [pc, #128] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
8003a5e: 681b ldr r3, [r3, #0]
|
|
8003a60: f003 0302 and.w r3, r3, #2
|
|
8003a64: 2b00 cmp r3, #0
|
|
8003a66: d1f0 bne.n 8003a4a <HAL_RCC_OscConfig+0x1da>
|
|
8003a68: e000 b.n 8003a6c <HAL_RCC_OscConfig+0x1fc>
|
|
if((READ_BIT(RCC->CR, RCC_CR_MSIRDY) != 0U) && (RCC_OscInitStruct->MSIState == RCC_MSI_OFF))
|
|
8003a6a: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------- HSE Configuration ------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
8003a6c: 687b ldr r3, [r7, #4]
|
|
8003a6e: 681b ldr r3, [r3, #0]
|
|
8003a70: f003 0301 and.w r3, r3, #1
|
|
8003a74: 2b00 cmp r3, #0
|
|
8003a76: d074 beq.n 8003b62 <HAL_RCC_OscConfig+0x2f2>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
|
|
|
|
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
|
|
if((sysclk_source == RCC_CFGR_SWS_HSE) ||
|
|
8003a78: 69bb ldr r3, [r7, #24]
|
|
8003a7a: 2b08 cmp r3, #8
|
|
8003a7c: d005 beq.n 8003a8a <HAL_RCC_OscConfig+0x21a>
|
|
8003a7e: 69bb ldr r3, [r7, #24]
|
|
8003a80: 2b0c cmp r3, #12
|
|
8003a82: d10e bne.n 8003aa2 <HAL_RCC_OscConfig+0x232>
|
|
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSE)))
|
|
8003a84: 697b ldr r3, [r7, #20]
|
|
8003a86: 2b03 cmp r3, #3
|
|
8003a88: d10b bne.n 8003aa2 <HAL_RCC_OscConfig+0x232>
|
|
{
|
|
if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8003a8a: 4b15 ldr r3, [pc, #84] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
8003a8c: 681b ldr r3, [r3, #0]
|
|
8003a8e: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8003a92: 2b00 cmp r3, #0
|
|
8003a94: d064 beq.n 8003b60 <HAL_RCC_OscConfig+0x2f0>
|
|
8003a96: 687b ldr r3, [r7, #4]
|
|
8003a98: 685b ldr r3, [r3, #4]
|
|
8003a9a: 2b00 cmp r3, #0
|
|
8003a9c: d160 bne.n 8003b60 <HAL_RCC_OscConfig+0x2f0>
|
|
{
|
|
return HAL_ERROR;
|
|
8003a9e: 2301 movs r3, #1
|
|
8003aa0: e2ba b.n 8004018 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Set the new HSE configuration ---------------------------------------*/
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
8003aa2: 687b ldr r3, [r7, #4]
|
|
8003aa4: 685b ldr r3, [r3, #4]
|
|
8003aa6: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8003aaa: d106 bne.n 8003aba <HAL_RCC_OscConfig+0x24a>
|
|
8003aac: 4b0c ldr r3, [pc, #48] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
8003aae: 681b ldr r3, [r3, #0]
|
|
8003ab0: 4a0b ldr r2, [pc, #44] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
8003ab2: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8003ab6: 6013 str r3, [r2, #0]
|
|
8003ab8: e026 b.n 8003b08 <HAL_RCC_OscConfig+0x298>
|
|
8003aba: 687b ldr r3, [r7, #4]
|
|
8003abc: 685b ldr r3, [r3, #4]
|
|
8003abe: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
|
|
8003ac2: d115 bne.n 8003af0 <HAL_RCC_OscConfig+0x280>
|
|
8003ac4: 4b06 ldr r3, [pc, #24] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
8003ac6: 681b ldr r3, [r3, #0]
|
|
8003ac8: 4a05 ldr r2, [pc, #20] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
8003aca: f443 2380 orr.w r3, r3, #262144 @ 0x40000
|
|
8003ace: 6013 str r3, [r2, #0]
|
|
8003ad0: 4b03 ldr r3, [pc, #12] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
8003ad2: 681b ldr r3, [r3, #0]
|
|
8003ad4: 4a02 ldr r2, [pc, #8] @ (8003ae0 <HAL_RCC_OscConfig+0x270>)
|
|
8003ad6: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8003ada: 6013 str r3, [r2, #0]
|
|
8003adc: e014 b.n 8003b08 <HAL_RCC_OscConfig+0x298>
|
|
8003ade: bf00 nop
|
|
8003ae0: 40021000 .word 0x40021000
|
|
8003ae4: 080092f8 .word 0x080092f8
|
|
8003ae8: 20000014 .word 0x20000014
|
|
8003aec: 20000018 .word 0x20000018
|
|
8003af0: 4ba0 ldr r3, [pc, #640] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003af2: 681b ldr r3, [r3, #0]
|
|
8003af4: 4a9f ldr r2, [pc, #636] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003af6: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
8003afa: 6013 str r3, [r2, #0]
|
|
8003afc: 4b9d ldr r3, [pc, #628] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003afe: 681b ldr r3, [r3, #0]
|
|
8003b00: 4a9c ldr r2, [pc, #624] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003b02: f423 2380 bic.w r3, r3, #262144 @ 0x40000
|
|
8003b06: 6013 str r3, [r2, #0]
|
|
|
|
/* Check the HSE State */
|
|
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
|
8003b08: 687b ldr r3, [r7, #4]
|
|
8003b0a: 685b ldr r3, [r3, #4]
|
|
8003b0c: 2b00 cmp r3, #0
|
|
8003b0e: d013 beq.n 8003b38 <HAL_RCC_OscConfig+0x2c8>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003b10: f7fe fca4 bl 800245c <HAL_GetTick>
|
|
8003b14: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
8003b16: e008 b.n 8003b2a <HAL_RCC_OscConfig+0x2ba>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8003b18: f7fe fca0 bl 800245c <HAL_GetTick>
|
|
8003b1c: 4602 mov r2, r0
|
|
8003b1e: 693b ldr r3, [r7, #16]
|
|
8003b20: 1ad3 subs r3, r2, r3
|
|
8003b22: 2b64 cmp r3, #100 @ 0x64
|
|
8003b24: d901 bls.n 8003b2a <HAL_RCC_OscConfig+0x2ba>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003b26: 2303 movs r3, #3
|
|
8003b28: e276 b.n 8004018 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
8003b2a: 4b92 ldr r3, [pc, #584] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003b2c: 681b ldr r3, [r3, #0]
|
|
8003b2e: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8003b32: 2b00 cmp r3, #0
|
|
8003b34: d0f0 beq.n 8003b18 <HAL_RCC_OscConfig+0x2a8>
|
|
8003b36: e014 b.n 8003b62 <HAL_RCC_OscConfig+0x2f2>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003b38: f7fe fc90 bl 800245c <HAL_GetTick>
|
|
8003b3c: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSE is disabled */
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
|
|
8003b3e: e008 b.n 8003b52 <HAL_RCC_OscConfig+0x2e2>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
|
|
8003b40: f7fe fc8c bl 800245c <HAL_GetTick>
|
|
8003b44: 4602 mov r2, r0
|
|
8003b46: 693b ldr r3, [r7, #16]
|
|
8003b48: 1ad3 subs r3, r2, r3
|
|
8003b4a: 2b64 cmp r3, #100 @ 0x64
|
|
8003b4c: d901 bls.n 8003b52 <HAL_RCC_OscConfig+0x2e2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003b4e: 2303 movs r3, #3
|
|
8003b50: e262 b.n 8004018 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
|
|
8003b52: 4b88 ldr r3, [pc, #544] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003b54: 681b ldr r3, [r3, #0]
|
|
8003b56: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8003b5a: 2b00 cmp r3, #0
|
|
8003b5c: d1f0 bne.n 8003b40 <HAL_RCC_OscConfig+0x2d0>
|
|
8003b5e: e000 b.n 8003b62 <HAL_RCC_OscConfig+0x2f2>
|
|
if((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
|
|
8003b60: bf00 nop
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*----------------------------- HSI Configuration --------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
8003b62: 687b ldr r3, [r7, #4]
|
|
8003b64: 681b ldr r3, [r3, #0]
|
|
8003b66: f003 0302 and.w r3, r3, #2
|
|
8003b6a: 2b00 cmp r3, #0
|
|
8003b6c: d060 beq.n 8003c30 <HAL_RCC_OscConfig+0x3c0>
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
|
|
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
|
|
|
|
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
|
|
if((sysclk_source == RCC_CFGR_SWS_HSI) ||
|
|
8003b6e: 69bb ldr r3, [r7, #24]
|
|
8003b70: 2b04 cmp r3, #4
|
|
8003b72: d005 beq.n 8003b80 <HAL_RCC_OscConfig+0x310>
|
|
8003b74: 69bb ldr r3, [r7, #24]
|
|
8003b76: 2b0c cmp r3, #12
|
|
8003b78: d119 bne.n 8003bae <HAL_RCC_OscConfig+0x33e>
|
|
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_config == RCC_PLLSOURCE_HSI)))
|
|
8003b7a: 697b ldr r3, [r7, #20]
|
|
8003b7c: 2b02 cmp r3, #2
|
|
8003b7e: d116 bne.n 8003bae <HAL_RCC_OscConfig+0x33e>
|
|
{
|
|
/* When HSI is used as system clock it will not be disabled */
|
|
if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
|
|
8003b80: 4b7c ldr r3, [pc, #496] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003b82: 681b ldr r3, [r3, #0]
|
|
8003b84: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8003b88: 2b00 cmp r3, #0
|
|
8003b8a: d005 beq.n 8003b98 <HAL_RCC_OscConfig+0x328>
|
|
8003b8c: 687b ldr r3, [r7, #4]
|
|
8003b8e: 68db ldr r3, [r3, #12]
|
|
8003b90: 2b00 cmp r3, #0
|
|
8003b92: d101 bne.n 8003b98 <HAL_RCC_OscConfig+0x328>
|
|
{
|
|
return HAL_ERROR;
|
|
8003b94: 2301 movs r3, #1
|
|
8003b96: e23f b.n 8004018 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
/* Otherwise, just the calibration is allowed */
|
|
else
|
|
{
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8003b98: 4b76 ldr r3, [pc, #472] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003b9a: 685b ldr r3, [r3, #4]
|
|
8003b9c: f023 52f8 bic.w r2, r3, #520093696 @ 0x1f000000
|
|
8003ba0: 687b ldr r3, [r7, #4]
|
|
8003ba2: 691b ldr r3, [r3, #16]
|
|
8003ba4: 061b lsls r3, r3, #24
|
|
8003ba6: 4973 ldr r1, [pc, #460] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003ba8: 4313 orrs r3, r2
|
|
8003baa: 604b str r3, [r1, #4]
|
|
if((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
|
|
8003bac: e040 b.n 8003c30 <HAL_RCC_OscConfig+0x3c0>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check the HSI State */
|
|
if(RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
|
|
8003bae: 687b ldr r3, [r7, #4]
|
|
8003bb0: 68db ldr r3, [r3, #12]
|
|
8003bb2: 2b00 cmp r3, #0
|
|
8003bb4: d023 beq.n 8003bfe <HAL_RCC_OscConfig+0x38e>
|
|
{
|
|
/* Enable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_ENABLE();
|
|
8003bb6: 4b6f ldr r3, [pc, #444] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003bb8: 681b ldr r3, [r3, #0]
|
|
8003bba: 4a6e ldr r2, [pc, #440] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003bbc: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8003bc0: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003bc2: f7fe fc4b bl 800245c <HAL_GetTick>
|
|
8003bc6: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
8003bc8: e008 b.n 8003bdc <HAL_RCC_OscConfig+0x36c>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8003bca: f7fe fc47 bl 800245c <HAL_GetTick>
|
|
8003bce: 4602 mov r2, r0
|
|
8003bd0: 693b ldr r3, [r7, #16]
|
|
8003bd2: 1ad3 subs r3, r2, r3
|
|
8003bd4: 2b02 cmp r3, #2
|
|
8003bd6: d901 bls.n 8003bdc <HAL_RCC_OscConfig+0x36c>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003bd8: 2303 movs r3, #3
|
|
8003bda: e21d b.n 8004018 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
8003bdc: 4b65 ldr r3, [pc, #404] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003bde: 681b ldr r3, [r3, #0]
|
|
8003be0: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8003be4: 2b00 cmp r3, #0
|
|
8003be6: d0f0 beq.n 8003bca <HAL_RCC_OscConfig+0x35a>
|
|
}
|
|
}
|
|
|
|
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8003be8: 4b62 ldr r3, [pc, #392] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003bea: 685b ldr r3, [r3, #4]
|
|
8003bec: f023 52f8 bic.w r2, r3, #520093696 @ 0x1f000000
|
|
8003bf0: 687b ldr r3, [r7, #4]
|
|
8003bf2: 691b ldr r3, [r3, #16]
|
|
8003bf4: 061b lsls r3, r3, #24
|
|
8003bf6: 495f ldr r1, [pc, #380] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003bf8: 4313 orrs r3, r2
|
|
8003bfa: 604b str r3, [r1, #4]
|
|
8003bfc: e018 b.n 8003c30 <HAL_RCC_OscConfig+0x3c0>
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal High Speed oscillator (HSI). */
|
|
__HAL_RCC_HSI_DISABLE();
|
|
8003bfe: 4b5d ldr r3, [pc, #372] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003c00: 681b ldr r3, [r3, #0]
|
|
8003c02: 4a5c ldr r2, [pc, #368] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003c04: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
8003c08: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003c0a: f7fe fc27 bl 800245c <HAL_GetTick>
|
|
8003c0e: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till HSI is disabled */
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
|
|
8003c10: e008 b.n 8003c24 <HAL_RCC_OscConfig+0x3b4>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
|
|
8003c12: f7fe fc23 bl 800245c <HAL_GetTick>
|
|
8003c16: 4602 mov r2, r0
|
|
8003c18: 693b ldr r3, [r7, #16]
|
|
8003c1a: 1ad3 subs r3, r2, r3
|
|
8003c1c: 2b02 cmp r3, #2
|
|
8003c1e: d901 bls.n 8003c24 <HAL_RCC_OscConfig+0x3b4>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003c20: 2303 movs r3, #3
|
|
8003c22: e1f9 b.n 8004018 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
|
|
8003c24: 4b53 ldr r3, [pc, #332] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003c26: 681b ldr r3, [r3, #0]
|
|
8003c28: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8003c2c: 2b00 cmp r3, #0
|
|
8003c2e: d1f0 bne.n 8003c12 <HAL_RCC_OscConfig+0x3a2>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSI Configuration -------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
8003c30: 687b ldr r3, [r7, #4]
|
|
8003c32: 681b ldr r3, [r3, #0]
|
|
8003c34: f003 0308 and.w r3, r3, #8
|
|
8003c38: 2b00 cmp r3, #0
|
|
8003c3a: d03c beq.n 8003cb6 <HAL_RCC_OscConfig+0x446>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
|
|
|
|
/* Check the LSI State */
|
|
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
|
|
8003c3c: 687b ldr r3, [r7, #4]
|
|
8003c3e: 695b ldr r3, [r3, #20]
|
|
8003c40: 2b00 cmp r3, #0
|
|
8003c42: d01c beq.n 8003c7e <HAL_RCC_OscConfig+0x40e>
|
|
MODIFY_REG(RCC->CSR, RCC_CSR_LSIPREDIV, RCC_OscInitStruct->LSIDiv);
|
|
}
|
|
#endif /* RCC_CSR_LSIPREDIV */
|
|
|
|
/* Enable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_ENABLE();
|
|
8003c44: 4b4b ldr r3, [pc, #300] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003c46: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8003c4a: 4a4a ldr r2, [pc, #296] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003c4c: f043 0301 orr.w r3, r3, #1
|
|
8003c50: f8c2 3094 str.w r3, [r2, #148] @ 0x94
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003c54: f7fe fc02 bl 800245c <HAL_GetTick>
|
|
8003c58: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is ready */
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
|
|
8003c5a: e008 b.n 8003c6e <HAL_RCC_OscConfig+0x3fe>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8003c5c: f7fe fbfe bl 800245c <HAL_GetTick>
|
|
8003c60: 4602 mov r2, r0
|
|
8003c62: 693b ldr r3, [r7, #16]
|
|
8003c64: 1ad3 subs r3, r2, r3
|
|
8003c66: 2b02 cmp r3, #2
|
|
8003c68: d901 bls.n 8003c6e <HAL_RCC_OscConfig+0x3fe>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003c6a: 2303 movs r3, #3
|
|
8003c6c: e1d4 b.n 8004018 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
|
|
8003c6e: 4b41 ldr r3, [pc, #260] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003c70: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8003c74: f003 0302 and.w r3, r3, #2
|
|
8003c78: 2b00 cmp r3, #0
|
|
8003c7a: d0ef beq.n 8003c5c <HAL_RCC_OscConfig+0x3ec>
|
|
8003c7c: e01b b.n 8003cb6 <HAL_RCC_OscConfig+0x446>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Disable the Internal Low Speed oscillator (LSI). */
|
|
__HAL_RCC_LSI_DISABLE();
|
|
8003c7e: 4b3d ldr r3, [pc, #244] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003c80: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8003c84: 4a3b ldr r2, [pc, #236] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003c86: f023 0301 bic.w r3, r3, #1
|
|
8003c8a: f8c2 3094 str.w r3, [r2, #148] @ 0x94
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003c8e: f7fe fbe5 bl 800245c <HAL_GetTick>
|
|
8003c92: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSI is disabled */
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
|
|
8003c94: e008 b.n 8003ca8 <HAL_RCC_OscConfig+0x438>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
|
|
8003c96: f7fe fbe1 bl 800245c <HAL_GetTick>
|
|
8003c9a: 4602 mov r2, r0
|
|
8003c9c: 693b ldr r3, [r7, #16]
|
|
8003c9e: 1ad3 subs r3, r2, r3
|
|
8003ca0: 2b02 cmp r3, #2
|
|
8003ca2: d901 bls.n 8003ca8 <HAL_RCC_OscConfig+0x438>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003ca4: 2303 movs r3, #3
|
|
8003ca6: e1b7 b.n 8004018 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
|
|
8003ca8: 4b32 ldr r3, [pc, #200] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003caa: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
8003cae: f003 0302 and.w r3, r3, #2
|
|
8003cb2: 2b00 cmp r3, #0
|
|
8003cb4: d1ef bne.n 8003c96 <HAL_RCC_OscConfig+0x426>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
/*------------------------------ LSE Configuration -------------------------*/
|
|
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
8003cb6: 687b ldr r3, [r7, #4]
|
|
8003cb8: 681b ldr r3, [r3, #0]
|
|
8003cba: f003 0304 and.w r3, r3, #4
|
|
8003cbe: 2b00 cmp r3, #0
|
|
8003cc0: f000 80a6 beq.w 8003e10 <HAL_RCC_OscConfig+0x5a0>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
8003cc4: 2300 movs r3, #0
|
|
8003cc6: 77fb strb r3, [r7, #31]
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
|
|
|
|
/* Update LSE configuration in Backup Domain control register */
|
|
/* Requires to enable write access to Backup Domain of necessary */
|
|
if(HAL_IS_BIT_CLR(RCC->APB1ENR1, RCC_APB1ENR1_PWREN))
|
|
8003cc8: 4b2a ldr r3, [pc, #168] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003cca: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8003ccc: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8003cd0: 2b00 cmp r3, #0
|
|
8003cd2: d10d bne.n 8003cf0 <HAL_RCC_OscConfig+0x480>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8003cd4: 4b27 ldr r3, [pc, #156] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003cd6: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8003cd8: 4a26 ldr r2, [pc, #152] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003cda: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8003cde: 6593 str r3, [r2, #88] @ 0x58
|
|
8003ce0: 4b24 ldr r3, [pc, #144] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003ce2: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8003ce4: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8003ce8: 60bb str r3, [r7, #8]
|
|
8003cea: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
8003cec: 2301 movs r3, #1
|
|
8003cee: 77fb strb r3, [r7, #31]
|
|
}
|
|
|
|
if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
8003cf0: 4b21 ldr r3, [pc, #132] @ (8003d78 <HAL_RCC_OscConfig+0x508>)
|
|
8003cf2: 681b ldr r3, [r3, #0]
|
|
8003cf4: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8003cf8: 2b00 cmp r3, #0
|
|
8003cfa: d118 bne.n 8003d2e <HAL_RCC_OscConfig+0x4be>
|
|
{
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
|
8003cfc: 4b1e ldr r3, [pc, #120] @ (8003d78 <HAL_RCC_OscConfig+0x508>)
|
|
8003cfe: 681b ldr r3, [r3, #0]
|
|
8003d00: 4a1d ldr r2, [pc, #116] @ (8003d78 <HAL_RCC_OscConfig+0x508>)
|
|
8003d02: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
8003d06: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
8003d08: f7fe fba8 bl 800245c <HAL_GetTick>
|
|
8003d0c: 6138 str r0, [r7, #16]
|
|
|
|
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
8003d0e: e008 b.n 8003d22 <HAL_RCC_OscConfig+0x4b2>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
8003d10: f7fe fba4 bl 800245c <HAL_GetTick>
|
|
8003d14: 4602 mov r2, r0
|
|
8003d16: 693b ldr r3, [r7, #16]
|
|
8003d18: 1ad3 subs r3, r2, r3
|
|
8003d1a: 2b02 cmp r3, #2
|
|
8003d1c: d901 bls.n 8003d22 <HAL_RCC_OscConfig+0x4b2>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003d1e: 2303 movs r3, #3
|
|
8003d20: e17a b.n 8004018 <HAL_RCC_OscConfig+0x7a8>
|
|
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
|
|
8003d22: 4b15 ldr r3, [pc, #84] @ (8003d78 <HAL_RCC_OscConfig+0x508>)
|
|
8003d24: 681b ldr r3, [r3, #0]
|
|
8003d26: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8003d2a: 2b00 cmp r3, #0
|
|
8003d2c: d0f0 beq.n 8003d10 <HAL_RCC_OscConfig+0x4a0>
|
|
{
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
|
|
}
|
|
#else
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
8003d2e: 687b ldr r3, [r7, #4]
|
|
8003d30: 689b ldr r3, [r3, #8]
|
|
8003d32: 2b01 cmp r3, #1
|
|
8003d34: d108 bne.n 8003d48 <HAL_RCC_OscConfig+0x4d8>
|
|
8003d36: 4b0f ldr r3, [pc, #60] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003d38: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003d3c: 4a0d ldr r2, [pc, #52] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003d3e: f043 0301 orr.w r3, r3, #1
|
|
8003d42: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
8003d46: e029 b.n 8003d9c <HAL_RCC_OscConfig+0x52c>
|
|
8003d48: 687b ldr r3, [r7, #4]
|
|
8003d4a: 689b ldr r3, [r3, #8]
|
|
8003d4c: 2b05 cmp r3, #5
|
|
8003d4e: d115 bne.n 8003d7c <HAL_RCC_OscConfig+0x50c>
|
|
8003d50: 4b08 ldr r3, [pc, #32] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003d52: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003d56: 4a07 ldr r2, [pc, #28] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003d58: f043 0304 orr.w r3, r3, #4
|
|
8003d5c: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
8003d60: 4b04 ldr r3, [pc, #16] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003d62: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003d66: 4a03 ldr r2, [pc, #12] @ (8003d74 <HAL_RCC_OscConfig+0x504>)
|
|
8003d68: f043 0301 orr.w r3, r3, #1
|
|
8003d6c: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
8003d70: e014 b.n 8003d9c <HAL_RCC_OscConfig+0x52c>
|
|
8003d72: bf00 nop
|
|
8003d74: 40021000 .word 0x40021000
|
|
8003d78: 40007000 .word 0x40007000
|
|
8003d7c: 4b9c ldr r3, [pc, #624] @ (8003ff0 <HAL_RCC_OscConfig+0x780>)
|
|
8003d7e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003d82: 4a9b ldr r2, [pc, #620] @ (8003ff0 <HAL_RCC_OscConfig+0x780>)
|
|
8003d84: f023 0301 bic.w r3, r3, #1
|
|
8003d88: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
8003d8c: 4b98 ldr r3, [pc, #608] @ (8003ff0 <HAL_RCC_OscConfig+0x780>)
|
|
8003d8e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003d92: 4a97 ldr r2, [pc, #604] @ (8003ff0 <HAL_RCC_OscConfig+0x780>)
|
|
8003d94: f023 0304 bic.w r3, r3, #4
|
|
8003d98: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
#endif /* RCC_BDCR_LSESYSDIS */
|
|
|
|
/* Check the LSE State */
|
|
if(RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
|
|
8003d9c: 687b ldr r3, [r7, #4]
|
|
8003d9e: 689b ldr r3, [r3, #8]
|
|
8003da0: 2b00 cmp r3, #0
|
|
8003da2: d016 beq.n 8003dd2 <HAL_RCC_OscConfig+0x562>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003da4: f7fe fb5a bl 800245c <HAL_GetTick>
|
|
8003da8: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is ready */
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
8003daa: e00a b.n 8003dc2 <HAL_RCC_OscConfig+0x552>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8003dac: f7fe fb56 bl 800245c <HAL_GetTick>
|
|
8003db0: 4602 mov r2, r0
|
|
8003db2: 693b ldr r3, [r7, #16]
|
|
8003db4: 1ad3 subs r3, r2, r3
|
|
8003db6: f241 3288 movw r2, #5000 @ 0x1388
|
|
8003dba: 4293 cmp r3, r2
|
|
8003dbc: d901 bls.n 8003dc2 <HAL_RCC_OscConfig+0x552>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003dbe: 2303 movs r3, #3
|
|
8003dc0: e12a b.n 8004018 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
8003dc2: 4b8b ldr r3, [pc, #556] @ (8003ff0 <HAL_RCC_OscConfig+0x780>)
|
|
8003dc4: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003dc8: f003 0302 and.w r3, r3, #2
|
|
8003dcc: 2b00 cmp r3, #0
|
|
8003dce: d0ed beq.n 8003dac <HAL_RCC_OscConfig+0x53c>
|
|
8003dd0: e015 b.n 8003dfe <HAL_RCC_OscConfig+0x58e>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003dd2: f7fe fb43 bl 800245c <HAL_GetTick>
|
|
8003dd6: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till LSE is disabled */
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
|
|
8003dd8: e00a b.n 8003df0 <HAL_RCC_OscConfig+0x580>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8003dda: f7fe fb3f bl 800245c <HAL_GetTick>
|
|
8003dde: 4602 mov r2, r0
|
|
8003de0: 693b ldr r3, [r7, #16]
|
|
8003de2: 1ad3 subs r3, r2, r3
|
|
8003de4: f241 3288 movw r2, #5000 @ 0x1388
|
|
8003de8: 4293 cmp r3, r2
|
|
8003dea: d901 bls.n 8003df0 <HAL_RCC_OscConfig+0x580>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003dec: 2303 movs r3, #3
|
|
8003dee: e113 b.n 8004018 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
|
|
8003df0: 4b7f ldr r3, [pc, #508] @ (8003ff0 <HAL_RCC_OscConfig+0x780>)
|
|
8003df2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8003df6: f003 0302 and.w r3, r3, #2
|
|
8003dfa: 2b00 cmp r3, #0
|
|
8003dfc: d1ed bne.n 8003dda <HAL_RCC_OscConfig+0x56a>
|
|
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSDIS);
|
|
#endif /* RCC_BDCR_LSESYSDIS */
|
|
}
|
|
|
|
/* Restore clock configuration if changed */
|
|
if(pwrclkchanged == SET)
|
|
8003dfe: 7ffb ldrb r3, [r7, #31]
|
|
8003e00: 2b01 cmp r3, #1
|
|
8003e02: d105 bne.n 8003e10 <HAL_RCC_OscConfig+0x5a0>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8003e04: 4b7a ldr r3, [pc, #488] @ (8003ff0 <HAL_RCC_OscConfig+0x780>)
|
|
8003e06: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
8003e08: 4a79 ldr r2, [pc, #484] @ (8003ff0 <HAL_RCC_OscConfig+0x780>)
|
|
8003e0a: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8003e0e: 6593 str r3, [r2, #88] @ 0x58
|
|
#endif /* RCC_HSI48_SUPPORT */
|
|
/*-------------------------------- PLL Configuration -----------------------*/
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
|
|
|
|
if(RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
|
|
8003e10: 687b ldr r3, [r7, #4]
|
|
8003e12: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8003e14: 2b00 cmp r3, #0
|
|
8003e16: f000 80fe beq.w 8004016 <HAL_RCC_OscConfig+0x7a6>
|
|
{
|
|
/* PLL On ? */
|
|
if(RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
|
|
8003e1a: 687b ldr r3, [r7, #4]
|
|
8003e1c: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
8003e1e: 2b02 cmp r3, #2
|
|
8003e20: f040 80d0 bne.w 8003fc4 <HAL_RCC_OscConfig+0x754>
|
|
#endif /* RCC_PLLP_SUPPORT */
|
|
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
|
|
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
|
|
|
|
/* Do nothing if PLL configuration is the unchanged */
|
|
pll_config = RCC->PLLCFGR;
|
|
8003e24: 4b72 ldr r3, [pc, #456] @ (8003ff0 <HAL_RCC_OscConfig+0x780>)
|
|
8003e26: 68db ldr r3, [r3, #12]
|
|
8003e28: 617b str r3, [r7, #20]
|
|
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8003e2a: 697b ldr r3, [r7, #20]
|
|
8003e2c: f003 0203 and.w r2, r3, #3
|
|
8003e30: 687b ldr r3, [r7, #4]
|
|
8003e32: 6adb ldr r3, [r3, #44] @ 0x2c
|
|
8003e34: 429a cmp r2, r3
|
|
8003e36: d130 bne.n 8003e9a <HAL_RCC_OscConfig+0x62a>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
|
|
8003e38: 697b ldr r3, [r7, #20]
|
|
8003e3a: f003 0270 and.w r2, r3, #112 @ 0x70
|
|
8003e3e: 687b ldr r3, [r7, #4]
|
|
8003e40: 6b1b ldr r3, [r3, #48] @ 0x30
|
|
8003e42: 3b01 subs r3, #1
|
|
8003e44: 011b lsls r3, r3, #4
|
|
if((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
|
|
8003e46: 429a cmp r2, r3
|
|
8003e48: d127 bne.n 8003e9a <HAL_RCC_OscConfig+0x62a>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
|
|
8003e4a: 697b ldr r3, [r7, #20]
|
|
8003e4c: f403 42fe and.w r2, r3, #32512 @ 0x7f00
|
|
8003e50: 687b ldr r3, [r7, #4]
|
|
8003e52: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
8003e54: 021b lsls r3, r3, #8
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != ((RCC_OscInitStruct->PLL.PLLM - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
|
|
8003e56: 429a cmp r2, r3
|
|
8003e58: d11f bne.n 8003e9a <HAL_RCC_OscConfig+0x62a>
|
|
#if defined(RCC_PLLP_SUPPORT)
|
|
#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLPDIV) != (RCC_OscInitStruct->PLL.PLLP << RCC_PLLCFGR_PLLPDIV_Pos)) ||
|
|
#else
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
|
|
8003e5a: 697b ldr r3, [r7, #20]
|
|
8003e5c: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8003e60: 687a ldr r2, [r7, #4]
|
|
8003e62: 6b92 ldr r2, [r2, #56] @ 0x38
|
|
8003e64: 2a07 cmp r2, #7
|
|
8003e66: bf14 ite ne
|
|
8003e68: 2201 movne r2, #1
|
|
8003e6a: 2200 moveq r2, #0
|
|
8003e6c: b2d2 uxtb r2, r2
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) ||
|
|
8003e6e: 4293 cmp r3, r2
|
|
8003e70: d113 bne.n 8003e9a <HAL_RCC_OscConfig+0x62a>
|
|
#endif
|
|
#endif
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
|
|
8003e72: 697b ldr r3, [r7, #20]
|
|
8003e74: f403 02c0 and.w r2, r3, #6291456 @ 0x600000
|
|
8003e78: 687b ldr r3, [r7, #4]
|
|
8003e7a: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8003e7c: 085b lsrs r3, r3, #1
|
|
8003e7e: 3b01 subs r3, #1
|
|
8003e80: 055b lsls r3, r3, #21
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLP) != ((RCC_OscInitStruct->PLL.PLLP == RCC_PLLP_DIV7) ? 0U : 1U)) ||
|
|
8003e82: 429a cmp r2, r3
|
|
8003e84: d109 bne.n 8003e9a <HAL_RCC_OscConfig+0x62a>
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
|
|
8003e86: 697b ldr r3, [r7, #20]
|
|
8003e88: f003 62c0 and.w r2, r3, #100663296 @ 0x6000000
|
|
8003e8c: 687b ldr r3, [r7, #4]
|
|
8003e8e: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8003e90: 085b lsrs r3, r3, #1
|
|
8003e92: 3b01 subs r3, #1
|
|
8003e94: 065b lsls r3, r3, #25
|
|
(READ_BIT(pll_config, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
|
|
8003e96: 429a cmp r2, r3
|
|
8003e98: d06e beq.n 8003f78 <HAL_RCC_OscConfig+0x708>
|
|
{
|
|
/* Check if the PLL is used as system clock or not */
|
|
if(sysclk_source != RCC_CFGR_SWS_PLL)
|
|
8003e9a: 69bb ldr r3, [r7, #24]
|
|
8003e9c: 2b0c cmp r3, #12
|
|
8003e9e: d069 beq.n 8003f74 <HAL_RCC_OscConfig+0x704>
|
|
{
|
|
#if defined(RCC_PLLSAI1_SUPPORT) || defined(RCC_PLLSAI2_SUPPORT)
|
|
/* Check if main PLL can be updated */
|
|
/* Not possible if the source is shared by other enabled PLLSAIx */
|
|
if((READ_BIT(RCC->CR, RCC_CR_PLLSAI1ON) != 0U)
|
|
8003ea0: 4b53 ldr r3, [pc, #332] @ (8003ff0 <HAL_RCC_OscConfig+0x780>)
|
|
8003ea2: 681b ldr r3, [r3, #0]
|
|
8003ea4: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
|
|
8003ea8: 2b00 cmp r3, #0
|
|
8003eaa: d105 bne.n 8003eb8 <HAL_RCC_OscConfig+0x648>
|
|
#if defined(RCC_PLLSAI2_SUPPORT)
|
|
|| (READ_BIT(RCC->CR, RCC_CR_PLLSAI2ON) != 0U)
|
|
8003eac: 4b50 ldr r3, [pc, #320] @ (8003ff0 <HAL_RCC_OscConfig+0x780>)
|
|
8003eae: 681b ldr r3, [r3, #0]
|
|
8003eb0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
8003eb4: 2b00 cmp r3, #0
|
|
8003eb6: d001 beq.n 8003ebc <HAL_RCC_OscConfig+0x64c>
|
|
#endif
|
|
)
|
|
{
|
|
return HAL_ERROR;
|
|
8003eb8: 2301 movs r3, #1
|
|
8003eba: e0ad b.n 8004018 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
else
|
|
#endif /* RCC_PLLSAI1_SUPPORT || RCC_PLLSAI2_SUPPORT */
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8003ebc: 4b4c ldr r3, [pc, #304] @ (8003ff0 <HAL_RCC_OscConfig+0x780>)
|
|
8003ebe: 681b ldr r3, [r3, #0]
|
|
8003ec0: 4a4b ldr r2, [pc, #300] @ (8003ff0 <HAL_RCC_OscConfig+0x780>)
|
|
8003ec2: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
|
|
8003ec6: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003ec8: f7fe fac8 bl 800245c <HAL_GetTick>
|
|
8003ecc: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
8003ece: e008 b.n 8003ee2 <HAL_RCC_OscConfig+0x672>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8003ed0: f7fe fac4 bl 800245c <HAL_GetTick>
|
|
8003ed4: 4602 mov r2, r0
|
|
8003ed6: 693b ldr r3, [r7, #16]
|
|
8003ed8: 1ad3 subs r3, r2, r3
|
|
8003eda: 2b02 cmp r3, #2
|
|
8003edc: d901 bls.n 8003ee2 <HAL_RCC_OscConfig+0x672>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003ede: 2303 movs r3, #3
|
|
8003ee0: e09a b.n 8004018 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
8003ee2: 4b43 ldr r3, [pc, #268] @ (8003ff0 <HAL_RCC_OscConfig+0x780>)
|
|
8003ee4: 681b ldr r3, [r3, #0]
|
|
8003ee6: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8003eea: 2b00 cmp r3, #0
|
|
8003eec: d1f0 bne.n 8003ed0 <HAL_RCC_OscConfig+0x660>
|
|
}
|
|
}
|
|
|
|
/* Configure the main PLL clock source, multiplication and division factors. */
|
|
#if defined(RCC_PLLP_SUPPORT)
|
|
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
|
|
8003eee: 4b40 ldr r3, [pc, #256] @ (8003ff0 <HAL_RCC_OscConfig+0x780>)
|
|
8003ef0: 68da ldr r2, [r3, #12]
|
|
8003ef2: 4b40 ldr r3, [pc, #256] @ (8003ff4 <HAL_RCC_OscConfig+0x784>)
|
|
8003ef4: 4013 ands r3, r2
|
|
8003ef6: 687a ldr r2, [r7, #4]
|
|
8003ef8: 6ad1 ldr r1, [r2, #44] @ 0x2c
|
|
8003efa: 687a ldr r2, [r7, #4]
|
|
8003efc: 6b12 ldr r2, [r2, #48] @ 0x30
|
|
8003efe: 3a01 subs r2, #1
|
|
8003f00: 0112 lsls r2, r2, #4
|
|
8003f02: 4311 orrs r1, r2
|
|
8003f04: 687a ldr r2, [r7, #4]
|
|
8003f06: 6b52 ldr r2, [r2, #52] @ 0x34
|
|
8003f08: 0212 lsls r2, r2, #8
|
|
8003f0a: 4311 orrs r1, r2
|
|
8003f0c: 687a ldr r2, [r7, #4]
|
|
8003f0e: 6bd2 ldr r2, [r2, #60] @ 0x3c
|
|
8003f10: 0852 lsrs r2, r2, #1
|
|
8003f12: 3a01 subs r2, #1
|
|
8003f14: 0552 lsls r2, r2, #21
|
|
8003f16: 4311 orrs r1, r2
|
|
8003f18: 687a ldr r2, [r7, #4]
|
|
8003f1a: 6c12 ldr r2, [r2, #64] @ 0x40
|
|
8003f1c: 0852 lsrs r2, r2, #1
|
|
8003f1e: 3a01 subs r2, #1
|
|
8003f20: 0652 lsls r2, r2, #25
|
|
8003f22: 4311 orrs r1, r2
|
|
8003f24: 687a ldr r2, [r7, #4]
|
|
8003f26: 6b92 ldr r2, [r2, #56] @ 0x38
|
|
8003f28: 0912 lsrs r2, r2, #4
|
|
8003f2a: 0452 lsls r2, r2, #17
|
|
8003f2c: 430a orrs r2, r1
|
|
8003f2e: 4930 ldr r1, [pc, #192] @ (8003ff0 <HAL_RCC_OscConfig+0x780>)
|
|
8003f30: 4313 orrs r3, r2
|
|
8003f32: 60cb str r3, [r1, #12]
|
|
RCC_OscInitStruct->PLL.PLLQ,
|
|
RCC_OscInitStruct->PLL.PLLR);
|
|
#endif
|
|
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
8003f34: 4b2e ldr r3, [pc, #184] @ (8003ff0 <HAL_RCC_OscConfig+0x780>)
|
|
8003f36: 681b ldr r3, [r3, #0]
|
|
8003f38: 4a2d ldr r2, [pc, #180] @ (8003ff0 <HAL_RCC_OscConfig+0x780>)
|
|
8003f3a: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
8003f3e: 6013 str r3, [r2, #0]
|
|
|
|
/* Enable PLL System Clock output. */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
|
|
8003f40: 4b2b ldr r3, [pc, #172] @ (8003ff0 <HAL_RCC_OscConfig+0x780>)
|
|
8003f42: 68db ldr r3, [r3, #12]
|
|
8003f44: 4a2a ldr r2, [pc, #168] @ (8003ff0 <HAL_RCC_OscConfig+0x780>)
|
|
8003f46: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
8003f4a: 60d3 str r3, [r2, #12]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003f4c: f7fe fa86 bl 800245c <HAL_GetTick>
|
|
8003f50: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
8003f52: e008 b.n 8003f66 <HAL_RCC_OscConfig+0x6f6>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8003f54: f7fe fa82 bl 800245c <HAL_GetTick>
|
|
8003f58: 4602 mov r2, r0
|
|
8003f5a: 693b ldr r3, [r7, #16]
|
|
8003f5c: 1ad3 subs r3, r2, r3
|
|
8003f5e: 2b02 cmp r3, #2
|
|
8003f60: d901 bls.n 8003f66 <HAL_RCC_OscConfig+0x6f6>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003f62: 2303 movs r3, #3
|
|
8003f64: e058 b.n 8004018 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
8003f66: 4b22 ldr r3, [pc, #136] @ (8003ff0 <HAL_RCC_OscConfig+0x780>)
|
|
8003f68: 681b ldr r3, [r3, #0]
|
|
8003f6a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8003f6e: 2b00 cmp r3, #0
|
|
8003f70: d0f0 beq.n 8003f54 <HAL_RCC_OscConfig+0x6e4>
|
|
if(sysclk_source != RCC_CFGR_SWS_PLL)
|
|
8003f72: e050 b.n 8004016 <HAL_RCC_OscConfig+0x7a6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* PLL is already used as System core clock */
|
|
return HAL_ERROR;
|
|
8003f74: 2301 movs r3, #1
|
|
8003f76: e04f b.n 8004018 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
else
|
|
{
|
|
/* PLL configuration is unchanged */
|
|
/* Re-enable PLL if it was disabled (ie. low power mode) */
|
|
if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
8003f78: 4b1d ldr r3, [pc, #116] @ (8003ff0 <HAL_RCC_OscConfig+0x780>)
|
|
8003f7a: 681b ldr r3, [r3, #0]
|
|
8003f7c: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8003f80: 2b00 cmp r3, #0
|
|
8003f82: d148 bne.n 8004016 <HAL_RCC_OscConfig+0x7a6>
|
|
{
|
|
/* Enable the main PLL. */
|
|
__HAL_RCC_PLL_ENABLE();
|
|
8003f84: 4b1a ldr r3, [pc, #104] @ (8003ff0 <HAL_RCC_OscConfig+0x780>)
|
|
8003f86: 681b ldr r3, [r3, #0]
|
|
8003f88: 4a19 ldr r2, [pc, #100] @ (8003ff0 <HAL_RCC_OscConfig+0x780>)
|
|
8003f8a: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
8003f8e: 6013 str r3, [r2, #0]
|
|
|
|
/* Enable PLL System Clock output. */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
|
|
8003f90: 4b17 ldr r3, [pc, #92] @ (8003ff0 <HAL_RCC_OscConfig+0x780>)
|
|
8003f92: 68db ldr r3, [r3, #12]
|
|
8003f94: 4a16 ldr r2, [pc, #88] @ (8003ff0 <HAL_RCC_OscConfig+0x780>)
|
|
8003f96: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
|
|
8003f9a: 60d3 str r3, [r2, #12]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003f9c: f7fe fa5e bl 800245c <HAL_GetTick>
|
|
8003fa0: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
8003fa2: e008 b.n 8003fb6 <HAL_RCC_OscConfig+0x746>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8003fa4: f7fe fa5a bl 800245c <HAL_GetTick>
|
|
8003fa8: 4602 mov r2, r0
|
|
8003faa: 693b ldr r3, [r7, #16]
|
|
8003fac: 1ad3 subs r3, r2, r3
|
|
8003fae: 2b02 cmp r3, #2
|
|
8003fb0: d901 bls.n 8003fb6 <HAL_RCC_OscConfig+0x746>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003fb2: 2303 movs r3, #3
|
|
8003fb4: e030 b.n 8004018 <HAL_RCC_OscConfig+0x7a8>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
8003fb6: 4b0e ldr r3, [pc, #56] @ (8003ff0 <HAL_RCC_OscConfig+0x780>)
|
|
8003fb8: 681b ldr r3, [r3, #0]
|
|
8003fba: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8003fbe: 2b00 cmp r3, #0
|
|
8003fc0: d0f0 beq.n 8003fa4 <HAL_RCC_OscConfig+0x734>
|
|
8003fc2: e028 b.n 8004016 <HAL_RCC_OscConfig+0x7a6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check that PLL is not used as system clock or not */
|
|
if(sysclk_source != RCC_CFGR_SWS_PLL)
|
|
8003fc4: 69bb ldr r3, [r7, #24]
|
|
8003fc6: 2b0c cmp r3, #12
|
|
8003fc8: d023 beq.n 8004012 <HAL_RCC_OscConfig+0x7a2>
|
|
{
|
|
/* Disable the main PLL. */
|
|
__HAL_RCC_PLL_DISABLE();
|
|
8003fca: 4b09 ldr r3, [pc, #36] @ (8003ff0 <HAL_RCC_OscConfig+0x780>)
|
|
8003fcc: 681b ldr r3, [r3, #0]
|
|
8003fce: 4a08 ldr r2, [pc, #32] @ (8003ff0 <HAL_RCC_OscConfig+0x780>)
|
|
8003fd0: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
|
|
8003fd4: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8003fd6: f7fe fa41 bl 800245c <HAL_GetTick>
|
|
8003fda: 6138 str r0, [r7, #16]
|
|
|
|
/* Wait till PLL is disabled */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
8003fdc: e00c b.n 8003ff8 <HAL_RCC_OscConfig+0x788>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
|
|
8003fde: f7fe fa3d bl 800245c <HAL_GetTick>
|
|
8003fe2: 4602 mov r2, r0
|
|
8003fe4: 693b ldr r3, [r7, #16]
|
|
8003fe6: 1ad3 subs r3, r2, r3
|
|
8003fe8: 2b02 cmp r3, #2
|
|
8003fea: d905 bls.n 8003ff8 <HAL_RCC_OscConfig+0x788>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
8003fec: 2303 movs r3, #3
|
|
8003fee: e013 b.n 8004018 <HAL_RCC_OscConfig+0x7a8>
|
|
8003ff0: 40021000 .word 0x40021000
|
|
8003ff4: f99d808c .word 0xf99d808c
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
|
|
8003ff8: 4b09 ldr r3, [pc, #36] @ (8004020 <HAL_RCC_OscConfig+0x7b0>)
|
|
8003ffa: 681b ldr r3, [r3, #0]
|
|
8003ffc: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
8004000: 2b00 cmp r3, #0
|
|
8004002: d1ec bne.n 8003fde <HAL_RCC_OscConfig+0x76e>
|
|
}
|
|
}
|
|
/* Unselect main PLL clock source and disable main PLL outputs to save power */
|
|
#if defined(RCC_PLLSAI2_SUPPORT)
|
|
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_SAI3CLK);
|
|
8004004: 4b06 ldr r3, [pc, #24] @ (8004020 <HAL_RCC_OscConfig+0x7b0>)
|
|
8004006: 68da ldr r2, [r3, #12]
|
|
8004008: 4905 ldr r1, [pc, #20] @ (8004020 <HAL_RCC_OscConfig+0x7b0>)
|
|
800400a: 4b06 ldr r3, [pc, #24] @ (8004024 <HAL_RCC_OscConfig+0x7b4>)
|
|
800400c: 4013 ands r3, r2
|
|
800400e: 60cb str r3, [r1, #12]
|
|
8004010: e001 b.n 8004016 <HAL_RCC_OscConfig+0x7a6>
|
|
#endif /* RCC_PLLSAI2_SUPPORT */
|
|
}
|
|
else
|
|
{
|
|
/* PLL is already used as System core clock */
|
|
return HAL_ERROR;
|
|
8004012: 2301 movs r3, #1
|
|
8004014: e000 b.n 8004018 <HAL_RCC_OscConfig+0x7a8>
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8004016: 2300 movs r3, #0
|
|
}
|
|
8004018: 4618 mov r0, r3
|
|
800401a: 3720 adds r7, #32
|
|
800401c: 46bd mov sp, r7
|
|
800401e: bd80 pop {r7, pc}
|
|
8004020: 40021000 .word 0x40021000
|
|
8004024: feeefffc .word 0xfeeefffc
|
|
|
|
08004028 <HAL_RCC_ClockConfig>:
|
|
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
|
|
* (for more details refer to section above "Initialization/de-initialization functions")
|
|
* @retval None
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
|
|
{
|
|
8004028: b580 push {r7, lr}
|
|
800402a: b084 sub sp, #16
|
|
800402c: af00 add r7, sp, #0
|
|
800402e: 6078 str r0, [r7, #4]
|
|
8004030: 6039 str r1, [r7, #0]
|
|
uint32_t hpre = RCC_SYSCLK_DIV1;
|
|
#endif
|
|
HAL_StatusTypeDef status;
|
|
|
|
/* Check Null pointer */
|
|
if(RCC_ClkInitStruct == NULL)
|
|
8004032: 687b ldr r3, [r7, #4]
|
|
8004034: 2b00 cmp r3, #0
|
|
8004036: d101 bne.n 800403c <HAL_RCC_ClockConfig+0x14>
|
|
{
|
|
return HAL_ERROR;
|
|
8004038: 2301 movs r3, #1
|
|
800403a: e0e7 b.n 800420c <HAL_RCC_ClockConfig+0x1e4>
|
|
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
|
|
must be correctly programmed according to the frequency of the CPU clock
|
|
(HCLK) and the supply voltage of the device. */
|
|
|
|
/* Increasing the number of wait states because of higher CPU frequency */
|
|
if(FLatency > __HAL_FLASH_GET_LATENCY())
|
|
800403c: 4b75 ldr r3, [pc, #468] @ (8004214 <HAL_RCC_ClockConfig+0x1ec>)
|
|
800403e: 681b ldr r3, [r3, #0]
|
|
8004040: f003 0307 and.w r3, r3, #7
|
|
8004044: 683a ldr r2, [r7, #0]
|
|
8004046: 429a cmp r2, r3
|
|
8004048: d910 bls.n 800406c <HAL_RCC_ClockConfig+0x44>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
800404a: 4b72 ldr r3, [pc, #456] @ (8004214 <HAL_RCC_ClockConfig+0x1ec>)
|
|
800404c: 681b ldr r3, [r3, #0]
|
|
800404e: f023 0207 bic.w r2, r3, #7
|
|
8004052: 4970 ldr r1, [pc, #448] @ (8004214 <HAL_RCC_ClockConfig+0x1ec>)
|
|
8004054: 683b ldr r3, [r7, #0]
|
|
8004056: 4313 orrs r3, r2
|
|
8004058: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if(__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
800405a: 4b6e ldr r3, [pc, #440] @ (8004214 <HAL_RCC_ClockConfig+0x1ec>)
|
|
800405c: 681b ldr r3, [r3, #0]
|
|
800405e: f003 0307 and.w r3, r3, #7
|
|
8004062: 683a ldr r2, [r7, #0]
|
|
8004064: 429a cmp r2, r3
|
|
8004066: d001 beq.n 800406c <HAL_RCC_ClockConfig+0x44>
|
|
{
|
|
return HAL_ERROR;
|
|
8004068: 2301 movs r3, #1
|
|
800406a: e0cf b.n 800420c <HAL_RCC_ClockConfig+0x1e4>
|
|
}
|
|
}
|
|
|
|
/*----------------- HCLK Configuration prior to SYSCLK----------------------*/
|
|
/* Apply higher HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is increased */
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
800406c: 687b ldr r3, [r7, #4]
|
|
800406e: 681b ldr r3, [r3, #0]
|
|
8004070: f003 0302 and.w r3, r3, #2
|
|
8004074: 2b00 cmp r3, #0
|
|
8004076: d010 beq.n 800409a <HAL_RCC_ClockConfig+0x72>
|
|
{
|
|
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
|
|
|
|
if(RCC_ClkInitStruct->AHBCLKDivider > READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
|
|
8004078: 687b ldr r3, [r7, #4]
|
|
800407a: 689a ldr r2, [r3, #8]
|
|
800407c: 4b66 ldr r3, [pc, #408] @ (8004218 <HAL_RCC_ClockConfig+0x1f0>)
|
|
800407e: 689b ldr r3, [r3, #8]
|
|
8004080: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
8004084: 429a cmp r2, r3
|
|
8004086: d908 bls.n 800409a <HAL_RCC_ClockConfig+0x72>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
8004088: 4b63 ldr r3, [pc, #396] @ (8004218 <HAL_RCC_ClockConfig+0x1f0>)
|
|
800408a: 689b ldr r3, [r3, #8]
|
|
800408c: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8004090: 687b ldr r3, [r7, #4]
|
|
8004092: 689b ldr r3, [r3, #8]
|
|
8004094: 4960 ldr r1, [pc, #384] @ (8004218 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8004096: 4313 orrs r3, r2
|
|
8004098: 608b str r3, [r1, #8]
|
|
}
|
|
}
|
|
|
|
/*------------------------- SYSCLK Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
800409a: 687b ldr r3, [r7, #4]
|
|
800409c: 681b ldr r3, [r3, #0]
|
|
800409e: f003 0301 and.w r3, r3, #1
|
|
80040a2: 2b00 cmp r3, #0
|
|
80040a4: d04c beq.n 8004140 <HAL_RCC_ClockConfig+0x118>
|
|
{
|
|
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
|
|
|
|
/* PLL is selected as System Clock Source */
|
|
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
|
|
80040a6: 687b ldr r3, [r7, #4]
|
|
80040a8: 685b ldr r3, [r3, #4]
|
|
80040aa: 2b03 cmp r3, #3
|
|
80040ac: d107 bne.n 80040be <HAL_RCC_ClockConfig+0x96>
|
|
{
|
|
/* Check the PLL ready flag */
|
|
if(READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
|
|
80040ae: 4b5a ldr r3, [pc, #360] @ (8004218 <HAL_RCC_ClockConfig+0x1f0>)
|
|
80040b0: 681b ldr r3, [r3, #0]
|
|
80040b2: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
|
|
80040b6: 2b00 cmp r3, #0
|
|
80040b8: d121 bne.n 80040fe <HAL_RCC_ClockConfig+0xd6>
|
|
{
|
|
return HAL_ERROR;
|
|
80040ba: 2301 movs r3, #1
|
|
80040bc: e0a6 b.n 800420c <HAL_RCC_ClockConfig+0x1e4>
|
|
#endif
|
|
}
|
|
else
|
|
{
|
|
/* HSE is selected as System Clock Source */
|
|
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
80040be: 687b ldr r3, [r7, #4]
|
|
80040c0: 685b ldr r3, [r3, #4]
|
|
80040c2: 2b02 cmp r3, #2
|
|
80040c4: d107 bne.n 80040d6 <HAL_RCC_ClockConfig+0xae>
|
|
{
|
|
/* Check the HSE ready flag */
|
|
if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
80040c6: 4b54 ldr r3, [pc, #336] @ (8004218 <HAL_RCC_ClockConfig+0x1f0>)
|
|
80040c8: 681b ldr r3, [r3, #0]
|
|
80040ca: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
80040ce: 2b00 cmp r3, #0
|
|
80040d0: d115 bne.n 80040fe <HAL_RCC_ClockConfig+0xd6>
|
|
{
|
|
return HAL_ERROR;
|
|
80040d2: 2301 movs r3, #1
|
|
80040d4: e09a b.n 800420c <HAL_RCC_ClockConfig+0x1e4>
|
|
}
|
|
}
|
|
/* MSI is selected as System Clock Source */
|
|
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI)
|
|
80040d6: 687b ldr r3, [r7, #4]
|
|
80040d8: 685b ldr r3, [r3, #4]
|
|
80040da: 2b00 cmp r3, #0
|
|
80040dc: d107 bne.n 80040ee <HAL_RCC_ClockConfig+0xc6>
|
|
{
|
|
/* Check the MSI ready flag */
|
|
if(READ_BIT(RCC->CR, RCC_CR_MSIRDY) == 0U)
|
|
80040de: 4b4e ldr r3, [pc, #312] @ (8004218 <HAL_RCC_ClockConfig+0x1f0>)
|
|
80040e0: 681b ldr r3, [r3, #0]
|
|
80040e2: f003 0302 and.w r3, r3, #2
|
|
80040e6: 2b00 cmp r3, #0
|
|
80040e8: d109 bne.n 80040fe <HAL_RCC_ClockConfig+0xd6>
|
|
{
|
|
return HAL_ERROR;
|
|
80040ea: 2301 movs r3, #1
|
|
80040ec: e08e b.n 800420c <HAL_RCC_ClockConfig+0x1e4>
|
|
}
|
|
/* HSI is selected as System Clock Source */
|
|
else
|
|
{
|
|
/* Check the HSI ready flag */
|
|
if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
80040ee: 4b4a ldr r3, [pc, #296] @ (8004218 <HAL_RCC_ClockConfig+0x1f0>)
|
|
80040f0: 681b ldr r3, [r3, #0]
|
|
80040f2: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
80040f6: 2b00 cmp r3, #0
|
|
80040f8: d101 bne.n 80040fe <HAL_RCC_ClockConfig+0xd6>
|
|
{
|
|
return HAL_ERROR;
|
|
80040fa: 2301 movs r3, #1
|
|
80040fc: e086 b.n 800420c <HAL_RCC_ClockConfig+0x1e4>
|
|
}
|
|
#endif
|
|
|
|
}
|
|
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
|
|
80040fe: 4b46 ldr r3, [pc, #280] @ (8004218 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8004100: 689b ldr r3, [r3, #8]
|
|
8004102: f023 0203 bic.w r2, r3, #3
|
|
8004106: 687b ldr r3, [r7, #4]
|
|
8004108: 685b ldr r3, [r3, #4]
|
|
800410a: 4943 ldr r1, [pc, #268] @ (8004218 <HAL_RCC_ClockConfig+0x1f0>)
|
|
800410c: 4313 orrs r3, r2
|
|
800410e: 608b str r3, [r1, #8]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8004110: f7fe f9a4 bl 800245c <HAL_GetTick>
|
|
8004114: 60f8 str r0, [r7, #12]
|
|
|
|
while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
8004116: e00a b.n 800412e <HAL_RCC_ClockConfig+0x106>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
|
|
8004118: f7fe f9a0 bl 800245c <HAL_GetTick>
|
|
800411c: 4602 mov r2, r0
|
|
800411e: 68fb ldr r3, [r7, #12]
|
|
8004120: 1ad3 subs r3, r2, r3
|
|
8004122: f241 3288 movw r2, #5000 @ 0x1388
|
|
8004126: 4293 cmp r3, r2
|
|
8004128: d901 bls.n 800412e <HAL_RCC_ClockConfig+0x106>
|
|
{
|
|
return HAL_TIMEOUT;
|
|
800412a: 2303 movs r3, #3
|
|
800412c: e06e b.n 800420c <HAL_RCC_ClockConfig+0x1e4>
|
|
while(__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
800412e: 4b3a ldr r3, [pc, #232] @ (8004218 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8004130: 689b ldr r3, [r3, #8]
|
|
8004132: f003 020c and.w r2, r3, #12
|
|
8004136: 687b ldr r3, [r7, #4]
|
|
8004138: 685b ldr r3, [r3, #4]
|
|
800413a: 009b lsls r3, r3, #2
|
|
800413c: 429a cmp r2, r3
|
|
800413e: d1eb bne.n 8004118 <HAL_RCC_ClockConfig+0xf0>
|
|
}
|
|
#endif
|
|
|
|
/*----------------- HCLK Configuration after SYSCLK-------------------------*/
|
|
/* Apply lower HCLK prescaler request here to ensure CPU clock is not of of spec when SYSCLK is set */
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
8004140: 687b ldr r3, [r7, #4]
|
|
8004142: 681b ldr r3, [r3, #0]
|
|
8004144: f003 0302 and.w r3, r3, #2
|
|
8004148: 2b00 cmp r3, #0
|
|
800414a: d010 beq.n 800416e <HAL_RCC_ClockConfig+0x146>
|
|
{
|
|
if(RCC_ClkInitStruct->AHBCLKDivider < READ_BIT(RCC->CFGR, RCC_CFGR_HPRE))
|
|
800414c: 687b ldr r3, [r7, #4]
|
|
800414e: 689a ldr r2, [r3, #8]
|
|
8004150: 4b31 ldr r3, [pc, #196] @ (8004218 <HAL_RCC_ClockConfig+0x1f0>)
|
|
8004152: 689b ldr r3, [r3, #8]
|
|
8004154: f003 03f0 and.w r3, r3, #240 @ 0xf0
|
|
8004158: 429a cmp r2, r3
|
|
800415a: d208 bcs.n 800416e <HAL_RCC_ClockConfig+0x146>
|
|
{
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
800415c: 4b2e ldr r3, [pc, #184] @ (8004218 <HAL_RCC_ClockConfig+0x1f0>)
|
|
800415e: 689b ldr r3, [r3, #8]
|
|
8004160: f023 02f0 bic.w r2, r3, #240 @ 0xf0
|
|
8004164: 687b ldr r3, [r7, #4]
|
|
8004166: 689b ldr r3, [r3, #8]
|
|
8004168: 492b ldr r1, [pc, #172] @ (8004218 <HAL_RCC_ClockConfig+0x1f0>)
|
|
800416a: 4313 orrs r3, r2
|
|
800416c: 608b str r3, [r1, #8]
|
|
}
|
|
}
|
|
|
|
/* Allow decreasing of the number of wait states (because of lower CPU frequency expected) */
|
|
if(FLatency < __HAL_FLASH_GET_LATENCY())
|
|
800416e: 4b29 ldr r3, [pc, #164] @ (8004214 <HAL_RCC_ClockConfig+0x1ec>)
|
|
8004170: 681b ldr r3, [r3, #0]
|
|
8004172: f003 0307 and.w r3, r3, #7
|
|
8004176: 683a ldr r2, [r7, #0]
|
|
8004178: 429a cmp r2, r3
|
|
800417a: d210 bcs.n 800419e <HAL_RCC_ClockConfig+0x176>
|
|
{
|
|
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
800417c: 4b25 ldr r3, [pc, #148] @ (8004214 <HAL_RCC_ClockConfig+0x1ec>)
|
|
800417e: 681b ldr r3, [r3, #0]
|
|
8004180: f023 0207 bic.w r2, r3, #7
|
|
8004184: 4923 ldr r1, [pc, #140] @ (8004214 <HAL_RCC_ClockConfig+0x1ec>)
|
|
8004186: 683b ldr r3, [r7, #0]
|
|
8004188: 4313 orrs r3, r2
|
|
800418a: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if(__HAL_FLASH_GET_LATENCY() != FLatency)
|
|
800418c: 4b21 ldr r3, [pc, #132] @ (8004214 <HAL_RCC_ClockConfig+0x1ec>)
|
|
800418e: 681b ldr r3, [r3, #0]
|
|
8004190: f003 0307 and.w r3, r3, #7
|
|
8004194: 683a ldr r2, [r7, #0]
|
|
8004196: 429a cmp r2, r3
|
|
8004198: d001 beq.n 800419e <HAL_RCC_ClockConfig+0x176>
|
|
{
|
|
return HAL_ERROR;
|
|
800419a: 2301 movs r3, #1
|
|
800419c: e036 b.n 800420c <HAL_RCC_ClockConfig+0x1e4>
|
|
}
|
|
}
|
|
|
|
/*-------------------------- PCLK1 Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
800419e: 687b ldr r3, [r7, #4]
|
|
80041a0: 681b ldr r3, [r3, #0]
|
|
80041a2: f003 0304 and.w r3, r3, #4
|
|
80041a6: 2b00 cmp r3, #0
|
|
80041a8: d008 beq.n 80041bc <HAL_RCC_ClockConfig+0x194>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
|
|
80041aa: 4b1b ldr r3, [pc, #108] @ (8004218 <HAL_RCC_ClockConfig+0x1f0>)
|
|
80041ac: 689b ldr r3, [r3, #8]
|
|
80041ae: f423 62e0 bic.w r2, r3, #1792 @ 0x700
|
|
80041b2: 687b ldr r3, [r7, #4]
|
|
80041b4: 68db ldr r3, [r3, #12]
|
|
80041b6: 4918 ldr r1, [pc, #96] @ (8004218 <HAL_RCC_ClockConfig+0x1f0>)
|
|
80041b8: 4313 orrs r3, r2
|
|
80041ba: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/*-------------------------- PCLK2 Configuration ---------------------------*/
|
|
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
|
|
80041bc: 687b ldr r3, [r7, #4]
|
|
80041be: 681b ldr r3, [r3, #0]
|
|
80041c0: f003 0308 and.w r3, r3, #8
|
|
80041c4: 2b00 cmp r3, #0
|
|
80041c6: d009 beq.n 80041dc <HAL_RCC_ClockConfig+0x1b4>
|
|
{
|
|
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
|
|
80041c8: 4b13 ldr r3, [pc, #76] @ (8004218 <HAL_RCC_ClockConfig+0x1f0>)
|
|
80041ca: 689b ldr r3, [r3, #8]
|
|
80041cc: f423 5260 bic.w r2, r3, #14336 @ 0x3800
|
|
80041d0: 687b ldr r3, [r7, #4]
|
|
80041d2: 691b ldr r3, [r3, #16]
|
|
80041d4: 00db lsls r3, r3, #3
|
|
80041d6: 4910 ldr r1, [pc, #64] @ (8004218 <HAL_RCC_ClockConfig+0x1f0>)
|
|
80041d8: 4313 orrs r3, r2
|
|
80041da: 608b str r3, [r1, #8]
|
|
}
|
|
|
|
/* Update the SystemCoreClock global variable */
|
|
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
|
|
80041dc: f000 f824 bl 8004228 <HAL_RCC_GetSysClockFreq>
|
|
80041e0: 4602 mov r2, r0
|
|
80041e2: 4b0d ldr r3, [pc, #52] @ (8004218 <HAL_RCC_ClockConfig+0x1f0>)
|
|
80041e4: 689b ldr r3, [r3, #8]
|
|
80041e6: 091b lsrs r3, r3, #4
|
|
80041e8: f003 030f and.w r3, r3, #15
|
|
80041ec: 490b ldr r1, [pc, #44] @ (800421c <HAL_RCC_ClockConfig+0x1f4>)
|
|
80041ee: 5ccb ldrb r3, [r1, r3]
|
|
80041f0: f003 031f and.w r3, r3, #31
|
|
80041f4: fa22 f303 lsr.w r3, r2, r3
|
|
80041f8: 4a09 ldr r2, [pc, #36] @ (8004220 <HAL_RCC_ClockConfig+0x1f8>)
|
|
80041fa: 6013 str r3, [r2, #0]
|
|
|
|
/* Configure the source of time base considering new system clocks settings*/
|
|
status = HAL_InitTick(uwTickPrio);
|
|
80041fc: 4b09 ldr r3, [pc, #36] @ (8004224 <HAL_RCC_ClockConfig+0x1fc>)
|
|
80041fe: 681b ldr r3, [r3, #0]
|
|
8004200: 4618 mov r0, r3
|
|
8004202: f7fe f8db bl 80023bc <HAL_InitTick>
|
|
8004206: 4603 mov r3, r0
|
|
8004208: 72fb strb r3, [r7, #11]
|
|
|
|
return status;
|
|
800420a: 7afb ldrb r3, [r7, #11]
|
|
}
|
|
800420c: 4618 mov r0, r3
|
|
800420e: 3710 adds r7, #16
|
|
8004210: 46bd mov sp, r7
|
|
8004212: bd80 pop {r7, pc}
|
|
8004214: 40022000 .word 0x40022000
|
|
8004218: 40021000 .word 0x40021000
|
|
800421c: 080092f8 .word 0x080092f8
|
|
8004220: 20000014 .word 0x20000014
|
|
8004224: 20000018 .word 0x20000018
|
|
|
|
08004228 <HAL_RCC_GetSysClockFreq>:
|
|
*
|
|
*
|
|
* @retval SYSCLK frequency
|
|
*/
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
8004228: b480 push {r7}
|
|
800422a: b089 sub sp, #36 @ 0x24
|
|
800422c: af00 add r7, sp, #0
|
|
uint32_t msirange = 0U, sysclockfreq = 0U;
|
|
800422e: 2300 movs r3, #0
|
|
8004230: 61fb str r3, [r7, #28]
|
|
8004232: 2300 movs r3, #0
|
|
8004234: 61bb str r3, [r7, #24]
|
|
uint32_t pllvco, pllsource, pllr, pllm; /* no init needed */
|
|
uint32_t sysclk_source, pll_oscsource;
|
|
|
|
sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
8004236: 4b3e ldr r3, [pc, #248] @ (8004330 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
8004238: 689b ldr r3, [r3, #8]
|
|
800423a: f003 030c and.w r3, r3, #12
|
|
800423e: 613b str r3, [r7, #16]
|
|
pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE();
|
|
8004240: 4b3b ldr r3, [pc, #236] @ (8004330 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
8004242: 68db ldr r3, [r3, #12]
|
|
8004244: f003 0303 and.w r3, r3, #3
|
|
8004248: 60fb str r3, [r7, #12]
|
|
|
|
if((sysclk_source == RCC_CFGR_SWS_MSI) ||
|
|
800424a: 693b ldr r3, [r7, #16]
|
|
800424c: 2b00 cmp r3, #0
|
|
800424e: d005 beq.n 800425c <HAL_RCC_GetSysClockFreq+0x34>
|
|
8004250: 693b ldr r3, [r7, #16]
|
|
8004252: 2b0c cmp r3, #12
|
|
8004254: d121 bne.n 800429a <HAL_RCC_GetSysClockFreq+0x72>
|
|
((sysclk_source == RCC_CFGR_SWS_PLL) && (pll_oscsource == RCC_PLLSOURCE_MSI)))
|
|
8004256: 68fb ldr r3, [r7, #12]
|
|
8004258: 2b01 cmp r3, #1
|
|
800425a: d11e bne.n 800429a <HAL_RCC_GetSysClockFreq+0x72>
|
|
{
|
|
/* MSI or PLL with MSI source used as system clock source */
|
|
|
|
/* Get SYSCLK source */
|
|
if(READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == 0U)
|
|
800425c: 4b34 ldr r3, [pc, #208] @ (8004330 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
800425e: 681b ldr r3, [r3, #0]
|
|
8004260: f003 0308 and.w r3, r3, #8
|
|
8004264: 2b00 cmp r3, #0
|
|
8004266: d107 bne.n 8004278 <HAL_RCC_GetSysClockFreq+0x50>
|
|
{ /* MSISRANGE from RCC_CSR applies */
|
|
msirange = READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE) >> RCC_CSR_MSISRANGE_Pos;
|
|
8004268: 4b31 ldr r3, [pc, #196] @ (8004330 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
800426a: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
|
|
800426e: 0a1b lsrs r3, r3, #8
|
|
8004270: f003 030f and.w r3, r3, #15
|
|
8004274: 61fb str r3, [r7, #28]
|
|
8004276: e005 b.n 8004284 <HAL_RCC_GetSysClockFreq+0x5c>
|
|
}
|
|
else
|
|
{ /* MSIRANGE from RCC_CR applies */
|
|
msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos;
|
|
8004278: 4b2d ldr r3, [pc, #180] @ (8004330 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
800427a: 681b ldr r3, [r3, #0]
|
|
800427c: 091b lsrs r3, r3, #4
|
|
800427e: f003 030f and.w r3, r3, #15
|
|
8004282: 61fb str r3, [r7, #28]
|
|
}
|
|
/*MSI frequency range in HZ*/
|
|
msirange = MSIRangeTable[msirange];
|
|
8004284: 4a2b ldr r2, [pc, #172] @ (8004334 <HAL_RCC_GetSysClockFreq+0x10c>)
|
|
8004286: 69fb ldr r3, [r7, #28]
|
|
8004288: f852 3023 ldr.w r3, [r2, r3, lsl #2]
|
|
800428c: 61fb str r3, [r7, #28]
|
|
|
|
if(sysclk_source == RCC_CFGR_SWS_MSI)
|
|
800428e: 693b ldr r3, [r7, #16]
|
|
8004290: 2b00 cmp r3, #0
|
|
8004292: d10d bne.n 80042b0 <HAL_RCC_GetSysClockFreq+0x88>
|
|
{
|
|
/* MSI used as system clock source */
|
|
sysclockfreq = msirange;
|
|
8004294: 69fb ldr r3, [r7, #28]
|
|
8004296: 61bb str r3, [r7, #24]
|
|
if(sysclk_source == RCC_CFGR_SWS_MSI)
|
|
8004298: e00a b.n 80042b0 <HAL_RCC_GetSysClockFreq+0x88>
|
|
}
|
|
}
|
|
else if(sysclk_source == RCC_CFGR_SWS_HSI)
|
|
800429a: 693b ldr r3, [r7, #16]
|
|
800429c: 2b04 cmp r3, #4
|
|
800429e: d102 bne.n 80042a6 <HAL_RCC_GetSysClockFreq+0x7e>
|
|
{
|
|
/* HSI used as system clock source */
|
|
sysclockfreq = HSI_VALUE;
|
|
80042a0: 4b25 ldr r3, [pc, #148] @ (8004338 <HAL_RCC_GetSysClockFreq+0x110>)
|
|
80042a2: 61bb str r3, [r7, #24]
|
|
80042a4: e004 b.n 80042b0 <HAL_RCC_GetSysClockFreq+0x88>
|
|
}
|
|
else if(sysclk_source == RCC_CFGR_SWS_HSE)
|
|
80042a6: 693b ldr r3, [r7, #16]
|
|
80042a8: 2b08 cmp r3, #8
|
|
80042aa: d101 bne.n 80042b0 <HAL_RCC_GetSysClockFreq+0x88>
|
|
{
|
|
/* HSE used as system clock source */
|
|
sysclockfreq = HSE_VALUE;
|
|
80042ac: 4b23 ldr r3, [pc, #140] @ (800433c <HAL_RCC_GetSysClockFreq+0x114>)
|
|
80042ae: 61bb str r3, [r7, #24]
|
|
else
|
|
{
|
|
/* unexpected case: sysclockfreq at 0 */
|
|
}
|
|
|
|
if(sysclk_source == RCC_CFGR_SWS_PLL)
|
|
80042b0: 693b ldr r3, [r7, #16]
|
|
80042b2: 2b0c cmp r3, #12
|
|
80042b4: d134 bne.n 8004320 <HAL_RCC_GetSysClockFreq+0xf8>
|
|
/* PLL used as system clock source */
|
|
|
|
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE) * PLLN / PLLM
|
|
SYSCLK = PLL_VCO / PLLR
|
|
*/
|
|
pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
|
|
80042b6: 4b1e ldr r3, [pc, #120] @ (8004330 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
80042b8: 68db ldr r3, [r3, #12]
|
|
80042ba: f003 0303 and.w r3, r3, #3
|
|
80042be: 60bb str r3, [r7, #8]
|
|
|
|
switch (pllsource)
|
|
80042c0: 68bb ldr r3, [r7, #8]
|
|
80042c2: 2b02 cmp r3, #2
|
|
80042c4: d003 beq.n 80042ce <HAL_RCC_GetSysClockFreq+0xa6>
|
|
80042c6: 68bb ldr r3, [r7, #8]
|
|
80042c8: 2b03 cmp r3, #3
|
|
80042ca: d003 beq.n 80042d4 <HAL_RCC_GetSysClockFreq+0xac>
|
|
80042cc: e005 b.n 80042da <HAL_RCC_GetSysClockFreq+0xb2>
|
|
{
|
|
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
|
|
pllvco = HSI_VALUE;
|
|
80042ce: 4b1a ldr r3, [pc, #104] @ (8004338 <HAL_RCC_GetSysClockFreq+0x110>)
|
|
80042d0: 617b str r3, [r7, #20]
|
|
break;
|
|
80042d2: e005 b.n 80042e0 <HAL_RCC_GetSysClockFreq+0xb8>
|
|
|
|
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
|
|
pllvco = HSE_VALUE;
|
|
80042d4: 4b19 ldr r3, [pc, #100] @ (800433c <HAL_RCC_GetSysClockFreq+0x114>)
|
|
80042d6: 617b str r3, [r7, #20]
|
|
break;
|
|
80042d8: e002 b.n 80042e0 <HAL_RCC_GetSysClockFreq+0xb8>
|
|
|
|
case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
|
|
default:
|
|
pllvco = msirange;
|
|
80042da: 69fb ldr r3, [r7, #28]
|
|
80042dc: 617b str r3, [r7, #20]
|
|
break;
|
|
80042de: bf00 nop
|
|
}
|
|
pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
|
|
80042e0: 4b13 ldr r3, [pc, #76] @ (8004330 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
80042e2: 68db ldr r3, [r3, #12]
|
|
80042e4: 091b lsrs r3, r3, #4
|
|
80042e6: f003 0307 and.w r3, r3, #7
|
|
80042ea: 3301 adds r3, #1
|
|
80042ec: 607b str r3, [r7, #4]
|
|
pllvco = (pllvco * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)) / pllm;
|
|
80042ee: 4b10 ldr r3, [pc, #64] @ (8004330 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
80042f0: 68db ldr r3, [r3, #12]
|
|
80042f2: 0a1b lsrs r3, r3, #8
|
|
80042f4: f003 037f and.w r3, r3, #127 @ 0x7f
|
|
80042f8: 697a ldr r2, [r7, #20]
|
|
80042fa: fb03 f202 mul.w r2, r3, r2
|
|
80042fe: 687b ldr r3, [r7, #4]
|
|
8004300: fbb2 f3f3 udiv r3, r2, r3
|
|
8004304: 617b str r3, [r7, #20]
|
|
pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
|
|
8004306: 4b0a ldr r3, [pc, #40] @ (8004330 <HAL_RCC_GetSysClockFreq+0x108>)
|
|
8004308: 68db ldr r3, [r3, #12]
|
|
800430a: 0e5b lsrs r3, r3, #25
|
|
800430c: f003 0303 and.w r3, r3, #3
|
|
8004310: 3301 adds r3, #1
|
|
8004312: 005b lsls r3, r3, #1
|
|
8004314: 603b str r3, [r7, #0]
|
|
sysclockfreq = pllvco / pllr;
|
|
8004316: 697a ldr r2, [r7, #20]
|
|
8004318: 683b ldr r3, [r7, #0]
|
|
800431a: fbb2 f3f3 udiv r3, r2, r3
|
|
800431e: 61bb str r3, [r7, #24]
|
|
}
|
|
|
|
return sysclockfreq;
|
|
8004320: 69bb ldr r3, [r7, #24]
|
|
}
|
|
8004322: 4618 mov r0, r3
|
|
8004324: 3724 adds r7, #36 @ 0x24
|
|
8004326: 46bd mov sp, r7
|
|
8004328: f85d 7b04 ldr.w r7, [sp], #4
|
|
800432c: 4770 bx lr
|
|
800432e: bf00 nop
|
|
8004330: 40021000 .word 0x40021000
|
|
8004334: 08009310 .word 0x08009310
|
|
8004338: 00f42400 .word 0x00f42400
|
|
800433c: 007a1200 .word 0x007a1200
|
|
|
|
08004340 <HAL_RCC_GetHCLKFreq>:
|
|
*
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
|
|
* @retval HCLK frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
{
|
|
8004340: b480 push {r7}
|
|
8004342: af00 add r7, sp, #0
|
|
return SystemCoreClock;
|
|
8004344: 4b03 ldr r3, [pc, #12] @ (8004354 <HAL_RCC_GetHCLKFreq+0x14>)
|
|
8004346: 681b ldr r3, [r3, #0]
|
|
}
|
|
8004348: 4618 mov r0, r3
|
|
800434a: 46bd mov sp, r7
|
|
800434c: f85d 7b04 ldr.w r7, [sp], #4
|
|
8004350: 4770 bx lr
|
|
8004352: bf00 nop
|
|
8004354: 20000014 .word 0x20000014
|
|
|
|
08004358 <HAL_RCC_GetPCLK1Freq>:
|
|
* @note Each time PCLK1 changes, this function must be called to update the
|
|
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK1 frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|
{
|
|
8004358: b580 push {r7, lr}
|
|
800435a: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU));
|
|
800435c: f7ff fff0 bl 8004340 <HAL_RCC_GetHCLKFreq>
|
|
8004360: 4602 mov r2, r0
|
|
8004362: 4b06 ldr r3, [pc, #24] @ (800437c <HAL_RCC_GetPCLK1Freq+0x24>)
|
|
8004364: 689b ldr r3, [r3, #8]
|
|
8004366: 0a1b lsrs r3, r3, #8
|
|
8004368: f003 0307 and.w r3, r3, #7
|
|
800436c: 4904 ldr r1, [pc, #16] @ (8004380 <HAL_RCC_GetPCLK1Freq+0x28>)
|
|
800436e: 5ccb ldrb r3, [r1, r3]
|
|
8004370: f003 031f and.w r3, r3, #31
|
|
8004374: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
8004378: 4618 mov r0, r3
|
|
800437a: bd80 pop {r7, pc}
|
|
800437c: 40021000 .word 0x40021000
|
|
8004380: 08009308 .word 0x08009308
|
|
|
|
08004384 <HAL_RCC_GetPCLK2Freq>:
|
|
* @note Each time PCLK2 changes, this function must be called to update the
|
|
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK2 frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK2Freq(void)
|
|
{
|
|
8004384: b580 push {r7, lr}
|
|
8004386: af00 add r7, sp, #0
|
|
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU));
|
|
8004388: f7ff ffda bl 8004340 <HAL_RCC_GetHCLKFreq>
|
|
800438c: 4602 mov r2, r0
|
|
800438e: 4b06 ldr r3, [pc, #24] @ (80043a8 <HAL_RCC_GetPCLK2Freq+0x24>)
|
|
8004390: 689b ldr r3, [r3, #8]
|
|
8004392: 0adb lsrs r3, r3, #11
|
|
8004394: f003 0307 and.w r3, r3, #7
|
|
8004398: 4904 ldr r1, [pc, #16] @ (80043ac <HAL_RCC_GetPCLK2Freq+0x28>)
|
|
800439a: 5ccb ldrb r3, [r1, r3]
|
|
800439c: f003 031f and.w r3, r3, #31
|
|
80043a0: fa22 f303 lsr.w r3, r2, r3
|
|
}
|
|
80043a4: 4618 mov r0, r3
|
|
80043a6: bd80 pop {r7, pc}
|
|
80043a8: 40021000 .word 0x40021000
|
|
80043ac: 08009308 .word 0x08009308
|
|
|
|
080043b0 <RCC_SetFlashLatencyFromMSIRange>:
|
|
voltage range.
|
|
* @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_11
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange)
|
|
{
|
|
80043b0: b580 push {r7, lr}
|
|
80043b2: b086 sub sp, #24
|
|
80043b4: af00 add r7, sp, #0
|
|
80043b6: 6078 str r0, [r7, #4]
|
|
uint32_t vos;
|
|
uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
|
|
80043b8: 2300 movs r3, #0
|
|
80043ba: 613b str r3, [r7, #16]
|
|
|
|
if(__HAL_RCC_PWR_IS_CLK_ENABLED())
|
|
80043bc: 4b2a ldr r3, [pc, #168] @ (8004468 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
80043be: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80043c0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
80043c4: 2b00 cmp r3, #0
|
|
80043c6: d003 beq.n 80043d0 <RCC_SetFlashLatencyFromMSIRange+0x20>
|
|
{
|
|
vos = HAL_PWREx_GetVoltageRange();
|
|
80043c8: f7ff f9ee bl 80037a8 <HAL_PWREx_GetVoltageRange>
|
|
80043cc: 6178 str r0, [r7, #20]
|
|
80043ce: e014 b.n 80043fa <RCC_SetFlashLatencyFromMSIRange+0x4a>
|
|
}
|
|
else
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
80043d0: 4b25 ldr r3, [pc, #148] @ (8004468 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
80043d2: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80043d4: 4a24 ldr r2, [pc, #144] @ (8004468 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
80043d6: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
80043da: 6593 str r3, [r2, #88] @ 0x58
|
|
80043dc: 4b22 ldr r3, [pc, #136] @ (8004468 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
80043de: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80043e0: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
80043e4: 60fb str r3, [r7, #12]
|
|
80043e6: 68fb ldr r3, [r7, #12]
|
|
vos = HAL_PWREx_GetVoltageRange();
|
|
80043e8: f7ff f9de bl 80037a8 <HAL_PWREx_GetVoltageRange>
|
|
80043ec: 6178 str r0, [r7, #20]
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
80043ee: 4b1e ldr r3, [pc, #120] @ (8004468 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
80043f0: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80043f2: 4a1d ldr r2, [pc, #116] @ (8004468 <RCC_SetFlashLatencyFromMSIRange+0xb8>)
|
|
80043f4: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
80043f8: 6593 str r3, [r2, #88] @ 0x58
|
|
}
|
|
|
|
if(vos == PWR_REGULATOR_VOLTAGE_SCALE1)
|
|
80043fa: 697b ldr r3, [r7, #20]
|
|
80043fc: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
8004400: d10b bne.n 800441a <RCC_SetFlashLatencyFromMSIRange+0x6a>
|
|
{
|
|
if(msirange > RCC_MSIRANGE_8)
|
|
8004402: 687b ldr r3, [r7, #4]
|
|
8004404: 2b80 cmp r3, #128 @ 0x80
|
|
8004406: d919 bls.n 800443c <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
|
{
|
|
/* MSI > 16Mhz */
|
|
if(msirange > RCC_MSIRANGE_10)
|
|
8004408: 687b ldr r3, [r7, #4]
|
|
800440a: 2ba0 cmp r3, #160 @ 0xa0
|
|
800440c: d902 bls.n 8004414 <RCC_SetFlashLatencyFromMSIRange+0x64>
|
|
{
|
|
/* MSI 48Mhz */
|
|
latency = FLASH_LATENCY_2; /* 2WS */
|
|
800440e: 2302 movs r3, #2
|
|
8004410: 613b str r3, [r7, #16]
|
|
8004412: e013 b.n 800443c <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
|
}
|
|
else
|
|
{
|
|
/* MSI 24Mhz or 32Mhz */
|
|
latency = FLASH_LATENCY_1; /* 1WS */
|
|
8004414: 2301 movs r3, #1
|
|
8004416: 613b str r3, [r7, #16]
|
|
8004418: e010 b.n 800443c <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
|
latency = FLASH_LATENCY_1; /* 1WS */
|
|
}
|
|
/* else MSI < 8Mhz default FLASH_LATENCY_0 0WS */
|
|
}
|
|
#else
|
|
if(msirange > RCC_MSIRANGE_8)
|
|
800441a: 687b ldr r3, [r7, #4]
|
|
800441c: 2b80 cmp r3, #128 @ 0x80
|
|
800441e: d902 bls.n 8004426 <RCC_SetFlashLatencyFromMSIRange+0x76>
|
|
{
|
|
/* MSI > 16Mhz */
|
|
latency = FLASH_LATENCY_3; /* 3WS */
|
|
8004420: 2303 movs r3, #3
|
|
8004422: 613b str r3, [r7, #16]
|
|
8004424: e00a b.n 800443c <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
|
}
|
|
else
|
|
{
|
|
if(msirange == RCC_MSIRANGE_8)
|
|
8004426: 687b ldr r3, [r7, #4]
|
|
8004428: 2b80 cmp r3, #128 @ 0x80
|
|
800442a: d102 bne.n 8004432 <RCC_SetFlashLatencyFromMSIRange+0x82>
|
|
{
|
|
/* MSI 16Mhz */
|
|
latency = FLASH_LATENCY_2; /* 2WS */
|
|
800442c: 2302 movs r3, #2
|
|
800442e: 613b str r3, [r7, #16]
|
|
8004430: e004 b.n 800443c <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
|
}
|
|
else if(msirange == RCC_MSIRANGE_7)
|
|
8004432: 687b ldr r3, [r7, #4]
|
|
8004434: 2b70 cmp r3, #112 @ 0x70
|
|
8004436: d101 bne.n 800443c <RCC_SetFlashLatencyFromMSIRange+0x8c>
|
|
{
|
|
/* MSI 8Mhz */
|
|
latency = FLASH_LATENCY_1; /* 1WS */
|
|
8004438: 2301 movs r3, #1
|
|
800443a: 613b str r3, [r7, #16]
|
|
}
|
|
}
|
|
#endif
|
|
}
|
|
|
|
__HAL_FLASH_SET_LATENCY(latency);
|
|
800443c: 4b0b ldr r3, [pc, #44] @ (800446c <RCC_SetFlashLatencyFromMSIRange+0xbc>)
|
|
800443e: 681b ldr r3, [r3, #0]
|
|
8004440: f023 0207 bic.w r2, r3, #7
|
|
8004444: 4909 ldr r1, [pc, #36] @ (800446c <RCC_SetFlashLatencyFromMSIRange+0xbc>)
|
|
8004446: 693b ldr r3, [r7, #16]
|
|
8004448: 4313 orrs r3, r2
|
|
800444a: 600b str r3, [r1, #0]
|
|
|
|
/* Check that the new number of wait states is taken into account to access the Flash
|
|
memory by reading the FLASH_ACR register */
|
|
if(__HAL_FLASH_GET_LATENCY() != latency)
|
|
800444c: 4b07 ldr r3, [pc, #28] @ (800446c <RCC_SetFlashLatencyFromMSIRange+0xbc>)
|
|
800444e: 681b ldr r3, [r3, #0]
|
|
8004450: f003 0307 and.w r3, r3, #7
|
|
8004454: 693a ldr r2, [r7, #16]
|
|
8004456: 429a cmp r2, r3
|
|
8004458: d001 beq.n 800445e <RCC_SetFlashLatencyFromMSIRange+0xae>
|
|
{
|
|
return HAL_ERROR;
|
|
800445a: 2301 movs r3, #1
|
|
800445c: e000 b.n 8004460 <RCC_SetFlashLatencyFromMSIRange+0xb0>
|
|
}
|
|
|
|
return HAL_OK;
|
|
800445e: 2300 movs r3, #0
|
|
}
|
|
8004460: 4618 mov r0, r3
|
|
8004462: 3718 adds r7, #24
|
|
8004464: 46bd mov sp, r7
|
|
8004466: bd80 pop {r7, pc}
|
|
8004468: 40021000 .word 0x40021000
|
|
800446c: 40022000 .word 0x40022000
|
|
|
|
08004470 <HAL_RCCEx_PeriphCLKConfig>:
|
|
* the RTC clock source: in this case the access to Backup domain is enabled.
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
|
{
|
|
8004470: b580 push {r7, lr}
|
|
8004472: b086 sub sp, #24
|
|
8004474: af00 add r7, sp, #0
|
|
8004476: 6078 str r0, [r7, #4]
|
|
uint32_t tmpregister, tickstart; /* no init needed */
|
|
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
|
|
8004478: 2300 movs r3, #0
|
|
800447a: 74fb strb r3, [r7, #19]
|
|
HAL_StatusTypeDef status = HAL_OK; /* Final status */
|
|
800447c: 2300 movs r3, #0
|
|
800447e: 74bb strb r3, [r7, #18]
|
|
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
|
|
|
#if defined(SAI1)
|
|
|
|
/*-------------------------- SAI1 clock source configuration ---------------------*/
|
|
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
|
|
8004480: 687b ldr r3, [r7, #4]
|
|
8004482: 681b ldr r3, [r3, #0]
|
|
8004484: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
8004488: 2b00 cmp r3, #0
|
|
800448a: d041 beq.n 8004510 <HAL_RCCEx_PeriphCLKConfig+0xa0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SAI1CLK(PeriphClkInit->Sai1ClockSelection));
|
|
|
|
switch(PeriphClkInit->Sai1ClockSelection)
|
|
800448c: 687b ldr r3, [r7, #4]
|
|
800448e: 6e5b ldr r3, [r3, #100] @ 0x64
|
|
8004490: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000
|
|
8004494: d02a beq.n 80044ec <HAL_RCCEx_PeriphCLKConfig+0x7c>
|
|
8004496: f5b3 0f40 cmp.w r3, #12582912 @ 0xc00000
|
|
800449a: d824 bhi.n 80044e6 <HAL_RCCEx_PeriphCLKConfig+0x76>
|
|
800449c: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000
|
|
80044a0: d008 beq.n 80044b4 <HAL_RCCEx_PeriphCLKConfig+0x44>
|
|
80044a2: f5b3 0f00 cmp.w r3, #8388608 @ 0x800000
|
|
80044a6: d81e bhi.n 80044e6 <HAL_RCCEx_PeriphCLKConfig+0x76>
|
|
80044a8: 2b00 cmp r3, #0
|
|
80044aa: d00a beq.n 80044c2 <HAL_RCCEx_PeriphCLKConfig+0x52>
|
|
80044ac: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
|
|
80044b0: d010 beq.n 80044d4 <HAL_RCCEx_PeriphCLKConfig+0x64>
|
|
80044b2: e018 b.n 80044e6 <HAL_RCCEx_PeriphCLKConfig+0x76>
|
|
{
|
|
case RCC_SAI1CLKSOURCE_PLL: /* PLL is used as clock source for SAI1*/
|
|
/* Enable SAI Clock output generated from System PLL . */
|
|
#if defined(RCC_PLLSAI2_SUPPORT)
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
|
|
80044b4: 4b86 ldr r3, [pc, #536] @ (80046d0 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
80044b6: 68db ldr r3, [r3, #12]
|
|
80044b8: 4a85 ldr r2, [pc, #532] @ (80046d0 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
80044ba: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
80044be: 60d3 str r3, [r2, #12]
|
|
#else
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI2CLK);
|
|
#endif /* RCC_PLLSAI2_SUPPORT */
|
|
/* SAI1 clock source config set later after clock selection check */
|
|
break;
|
|
80044c0: e015 b.n 80044ee <HAL_RCCEx_PeriphCLKConfig+0x7e>
|
|
|
|
case RCC_SAI1CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI1*/
|
|
/* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
|
|
80044c2: 687b ldr r3, [r7, #4]
|
|
80044c4: 3304 adds r3, #4
|
|
80044c6: 2100 movs r1, #0
|
|
80044c8: 4618 mov r0, r3
|
|
80044ca: f000 fabb bl 8004a44 <RCCEx_PLLSAI1_Config>
|
|
80044ce: 4603 mov r3, r0
|
|
80044d0: 74fb strb r3, [r7, #19]
|
|
/* SAI1 clock source config set later after clock selection check */
|
|
break;
|
|
80044d2: e00c b.n 80044ee <HAL_RCCEx_PeriphCLKConfig+0x7e>
|
|
|
|
#if defined(RCC_PLLSAI2_SUPPORT)
|
|
|
|
case RCC_SAI1CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI1*/
|
|
/* PLLSAI2 input clock, parameters M, N & P configuration clock output (PLLSAI2ClockOut) */
|
|
ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
|
|
80044d4: 687b ldr r3, [r7, #4]
|
|
80044d6: 3320 adds r3, #32
|
|
80044d8: 2100 movs r1, #0
|
|
80044da: 4618 mov r0, r3
|
|
80044dc: f000 fba6 bl 8004c2c <RCCEx_PLLSAI2_Config>
|
|
80044e0: 4603 mov r3, r0
|
|
80044e2: 74fb strb r3, [r7, #19]
|
|
/* SAI1 clock source config set later after clock selection check */
|
|
break;
|
|
80044e4: e003 b.n 80044ee <HAL_RCCEx_PeriphCLKConfig+0x7e>
|
|
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
|
|
/* SAI1 clock source config set later after clock selection check */
|
|
break;
|
|
|
|
default:
|
|
ret = HAL_ERROR;
|
|
80044e6: 2301 movs r3, #1
|
|
80044e8: 74fb strb r3, [r7, #19]
|
|
break;
|
|
80044ea: e000 b.n 80044ee <HAL_RCCEx_PeriphCLKConfig+0x7e>
|
|
break;
|
|
80044ec: bf00 nop
|
|
}
|
|
|
|
if(ret == HAL_OK)
|
|
80044ee: 7cfb ldrb r3, [r7, #19]
|
|
80044f0: 2b00 cmp r3, #0
|
|
80044f2: d10b bne.n 800450c <HAL_RCCEx_PeriphCLKConfig+0x9c>
|
|
{
|
|
/* Set the source of SAI1 clock*/
|
|
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
|
|
80044f4: 4b76 ldr r3, [pc, #472] @ (80046d0 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
80044f6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80044fa: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
|
|
80044fe: 687b ldr r3, [r7, #4]
|
|
8004500: 6e5b ldr r3, [r3, #100] @ 0x64
|
|
8004502: 4973 ldr r1, [pc, #460] @ (80046d0 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8004504: 4313 orrs r3, r2
|
|
8004506: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
800450a: e001 b.n 8004510 <HAL_RCCEx_PeriphCLKConfig+0xa0>
|
|
}
|
|
else
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
800450c: 7cfb ldrb r3, [r7, #19]
|
|
800450e: 74bb strb r3, [r7, #18]
|
|
#endif /* SAI1 */
|
|
|
|
#if defined(SAI2)
|
|
|
|
/*-------------------------- SAI2 clock source configuration ---------------------*/
|
|
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2))
|
|
8004510: 687b ldr r3, [r7, #4]
|
|
8004512: 681b ldr r3, [r3, #0]
|
|
8004514: f403 5380 and.w r3, r3, #4096 @ 0x1000
|
|
8004518: 2b00 cmp r3, #0
|
|
800451a: d041 beq.n 80045a0 <HAL_RCCEx_PeriphCLKConfig+0x130>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SAI2CLK(PeriphClkInit->Sai2ClockSelection));
|
|
|
|
switch(PeriphClkInit->Sai2ClockSelection)
|
|
800451c: 687b ldr r3, [r7, #4]
|
|
800451e: 6e9b ldr r3, [r3, #104] @ 0x68
|
|
8004520: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000
|
|
8004524: d02a beq.n 800457c <HAL_RCCEx_PeriphCLKConfig+0x10c>
|
|
8004526: f1b3 7f40 cmp.w r3, #50331648 @ 0x3000000
|
|
800452a: d824 bhi.n 8004576 <HAL_RCCEx_PeriphCLKConfig+0x106>
|
|
800452c: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
|
|
8004530: d008 beq.n 8004544 <HAL_RCCEx_PeriphCLKConfig+0xd4>
|
|
8004532: f1b3 7f00 cmp.w r3, #33554432 @ 0x2000000
|
|
8004536: d81e bhi.n 8004576 <HAL_RCCEx_PeriphCLKConfig+0x106>
|
|
8004538: 2b00 cmp r3, #0
|
|
800453a: d00a beq.n 8004552 <HAL_RCCEx_PeriphCLKConfig+0xe2>
|
|
800453c: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
8004540: d010 beq.n 8004564 <HAL_RCCEx_PeriphCLKConfig+0xf4>
|
|
8004542: e018 b.n 8004576 <HAL_RCCEx_PeriphCLKConfig+0x106>
|
|
{
|
|
case RCC_SAI2CLKSOURCE_PLL: /* PLL is used as clock source for SAI2*/
|
|
/* Enable SAI Clock output generated from System PLL . */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
|
|
8004544: 4b62 ldr r3, [pc, #392] @ (80046d0 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8004546: 68db ldr r3, [r3, #12]
|
|
8004548: 4a61 ldr r2, [pc, #388] @ (80046d0 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
800454a: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
800454e: 60d3 str r3, [r2, #12]
|
|
/* SAI2 clock source config set later after clock selection check */
|
|
break;
|
|
8004550: e015 b.n 800457e <HAL_RCCEx_PeriphCLKConfig+0x10e>
|
|
|
|
case RCC_SAI2CLKSOURCE_PLLSAI1: /* PLLSAI1 is used as clock source for SAI2*/
|
|
/* PLLSAI1 input clock, parameters M, N & P configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_P_UPDATE);
|
|
8004552: 687b ldr r3, [r7, #4]
|
|
8004554: 3304 adds r3, #4
|
|
8004556: 2100 movs r1, #0
|
|
8004558: 4618 mov r0, r3
|
|
800455a: f000 fa73 bl 8004a44 <RCCEx_PLLSAI1_Config>
|
|
800455e: 4603 mov r3, r0
|
|
8004560: 74fb strb r3, [r7, #19]
|
|
/* SAI2 clock source config set later after clock selection check */
|
|
break;
|
|
8004562: e00c b.n 800457e <HAL_RCCEx_PeriphCLKConfig+0x10e>
|
|
|
|
case RCC_SAI2CLKSOURCE_PLLSAI2: /* PLLSAI2 is used as clock source for SAI2*/
|
|
/* PLLSAI2 input clock, parameters M, N & P configuration and clock output (PLLSAI2ClockOut) */
|
|
ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_P_UPDATE);
|
|
8004564: 687b ldr r3, [r7, #4]
|
|
8004566: 3320 adds r3, #32
|
|
8004568: 2100 movs r1, #0
|
|
800456a: 4618 mov r0, r3
|
|
800456c: f000 fb5e bl 8004c2c <RCCEx_PLLSAI2_Config>
|
|
8004570: 4603 mov r3, r0
|
|
8004572: 74fb strb r3, [r7, #19]
|
|
/* SAI2 clock source config set later after clock selection check */
|
|
break;
|
|
8004574: e003 b.n 800457e <HAL_RCCEx_PeriphCLKConfig+0x10e>
|
|
#endif /* STM32L4P5xx || STM32L4Q5xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */
|
|
/* SAI2 clock source config set later after clock selection check */
|
|
break;
|
|
|
|
default:
|
|
ret = HAL_ERROR;
|
|
8004576: 2301 movs r3, #1
|
|
8004578: 74fb strb r3, [r7, #19]
|
|
break;
|
|
800457a: e000 b.n 800457e <HAL_RCCEx_PeriphCLKConfig+0x10e>
|
|
break;
|
|
800457c: bf00 nop
|
|
}
|
|
|
|
if(ret == HAL_OK)
|
|
800457e: 7cfb ldrb r3, [r7, #19]
|
|
8004580: 2b00 cmp r3, #0
|
|
8004582: d10b bne.n 800459c <HAL_RCCEx_PeriphCLKConfig+0x12c>
|
|
{
|
|
/* Set the source of SAI2 clock*/
|
|
__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
|
|
8004584: 4b52 ldr r3, [pc, #328] @ (80046d0 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8004586: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
800458a: f023 7240 bic.w r2, r3, #50331648 @ 0x3000000
|
|
800458e: 687b ldr r3, [r7, #4]
|
|
8004590: 6e9b ldr r3, [r3, #104] @ 0x68
|
|
8004592: 494f ldr r1, [pc, #316] @ (80046d0 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8004594: 4313 orrs r3, r2
|
|
8004596: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
800459a: e001 b.n 80045a0 <HAL_RCCEx_PeriphCLKConfig+0x130>
|
|
}
|
|
else
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
800459c: 7cfb ldrb r3, [r7, #19]
|
|
800459e: 74bb strb r3, [r7, #18]
|
|
}
|
|
}
|
|
#endif /* SAI2 */
|
|
|
|
/*-------------------------- RTC clock source configuration ----------------------*/
|
|
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
|
|
80045a0: 687b ldr r3, [r7, #4]
|
|
80045a2: 681b ldr r3, [r3, #0]
|
|
80045a4: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
80045a8: 2b00 cmp r3, #0
|
|
80045aa: f000 80a0 beq.w 80046ee <HAL_RCCEx_PeriphCLKConfig+0x27e>
|
|
{
|
|
FlagStatus pwrclkchanged = RESET;
|
|
80045ae: 2300 movs r3, #0
|
|
80045b0: 747b strb r3, [r7, #17]
|
|
|
|
/* Check for RTC Parameters used to output RTCCLK */
|
|
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
|
|
|
|
/* Enable Power Clock */
|
|
if(__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
|
|
80045b2: 4b47 ldr r3, [pc, #284] @ (80046d0 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
80045b4: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80045b6: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
80045ba: 2b00 cmp r3, #0
|
|
80045bc: d101 bne.n 80045c2 <HAL_RCCEx_PeriphCLKConfig+0x152>
|
|
80045be: 2301 movs r3, #1
|
|
80045c0: e000 b.n 80045c4 <HAL_RCCEx_PeriphCLKConfig+0x154>
|
|
80045c2: 2300 movs r3, #0
|
|
80045c4: 2b00 cmp r3, #0
|
|
80045c6: d00d beq.n 80045e4 <HAL_RCCEx_PeriphCLKConfig+0x174>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
80045c8: 4b41 ldr r3, [pc, #260] @ (80046d0 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
80045ca: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80045cc: 4a40 ldr r2, [pc, #256] @ (80046d0 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
80045ce: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
80045d2: 6593 str r3, [r2, #88] @ 0x58
|
|
80045d4: 4b3e ldr r3, [pc, #248] @ (80046d0 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
80045d6: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80045d8: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
|
|
80045dc: 60bb str r3, [r7, #8]
|
|
80045de: 68bb ldr r3, [r7, #8]
|
|
pwrclkchanged = SET;
|
|
80045e0: 2301 movs r3, #1
|
|
80045e2: 747b strb r3, [r7, #17]
|
|
}
|
|
|
|
/* Enable write access to Backup domain */
|
|
SET_BIT(PWR->CR1, PWR_CR1_DBP);
|
|
80045e4: 4b3b ldr r3, [pc, #236] @ (80046d4 <HAL_RCCEx_PeriphCLKConfig+0x264>)
|
|
80045e6: 681b ldr r3, [r3, #0]
|
|
80045e8: 4a3a ldr r2, [pc, #232] @ (80046d4 <HAL_RCCEx_PeriphCLKConfig+0x264>)
|
|
80045ea: f443 7380 orr.w r3, r3, #256 @ 0x100
|
|
80045ee: 6013 str r3, [r2, #0]
|
|
|
|
/* Wait for Backup domain Write protection disable */
|
|
tickstart = HAL_GetTick();
|
|
80045f0: f7fd ff34 bl 800245c <HAL_GetTick>
|
|
80045f4: 60f8 str r0, [r7, #12]
|
|
|
|
while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
|
|
80045f6: e009 b.n 800460c <HAL_RCCEx_PeriphCLKConfig+0x19c>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
|
|
80045f8: f7fd ff30 bl 800245c <HAL_GetTick>
|
|
80045fc: 4602 mov r2, r0
|
|
80045fe: 68fb ldr r3, [r7, #12]
|
|
8004600: 1ad3 subs r3, r2, r3
|
|
8004602: 2b02 cmp r3, #2
|
|
8004604: d902 bls.n 800460c <HAL_RCCEx_PeriphCLKConfig+0x19c>
|
|
{
|
|
ret = HAL_TIMEOUT;
|
|
8004606: 2303 movs r3, #3
|
|
8004608: 74fb strb r3, [r7, #19]
|
|
break;
|
|
800460a: e005 b.n 8004618 <HAL_RCCEx_PeriphCLKConfig+0x1a8>
|
|
while(READ_BIT(PWR->CR1, PWR_CR1_DBP) == 0U)
|
|
800460c: 4b31 ldr r3, [pc, #196] @ (80046d4 <HAL_RCCEx_PeriphCLKConfig+0x264>)
|
|
800460e: 681b ldr r3, [r3, #0]
|
|
8004610: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
8004614: 2b00 cmp r3, #0
|
|
8004616: d0ef beq.n 80045f8 <HAL_RCCEx_PeriphCLKConfig+0x188>
|
|
}
|
|
}
|
|
|
|
if(ret == HAL_OK)
|
|
8004618: 7cfb ldrb r3, [r7, #19]
|
|
800461a: 2b00 cmp r3, #0
|
|
800461c: d15c bne.n 80046d8 <HAL_RCCEx_PeriphCLKConfig+0x268>
|
|
{
|
|
/* Reset the Backup domain only if the RTC Clock source selection is modified from default */
|
|
tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
|
|
800461e: 4b2c ldr r3, [pc, #176] @ (80046d0 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8004620: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8004624: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
8004628: 617b str r3, [r7, #20]
|
|
|
|
if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
|
|
800462a: 697b ldr r3, [r7, #20]
|
|
800462c: 2b00 cmp r3, #0
|
|
800462e: d01f beq.n 8004670 <HAL_RCCEx_PeriphCLKConfig+0x200>
|
|
8004630: 687b ldr r3, [r7, #4]
|
|
8004632: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8004636: 697a ldr r2, [r7, #20]
|
|
8004638: 429a cmp r2, r3
|
|
800463a: d019 beq.n 8004670 <HAL_RCCEx_PeriphCLKConfig+0x200>
|
|
{
|
|
/* Store the content of BDCR register before the reset of Backup Domain */
|
|
tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
|
|
800463c: 4b24 ldr r3, [pc, #144] @ (80046d0 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
800463e: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
8004642: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8004646: 617b str r3, [r7, #20]
|
|
/* RTC Clock selection can be changed only if the Backup Domain is reset */
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
|
8004648: 4b21 ldr r3, [pc, #132] @ (80046d0 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
800464a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
800464e: 4a20 ldr r2, [pc, #128] @ (80046d0 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8004650: f443 3380 orr.w r3, r3, #65536 @ 0x10000
|
|
8004654: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
__HAL_RCC_BACKUPRESET_RELEASE();
|
|
8004658: 4b1d ldr r3, [pc, #116] @ (80046d0 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
800465a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
800465e: 4a1c ldr r2, [pc, #112] @ (80046d0 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
8004660: f423 3380 bic.w r3, r3, #65536 @ 0x10000
|
|
8004664: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
/* Restore the Content of BDCR register */
|
|
RCC->BDCR = tmpregister;
|
|
8004668: 4a19 ldr r2, [pc, #100] @ (80046d0 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
800466a: 697b ldr r3, [r7, #20]
|
|
800466c: f8c2 3090 str.w r3, [r2, #144] @ 0x90
|
|
}
|
|
|
|
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
|
|
if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
|
|
8004670: 697b ldr r3, [r7, #20]
|
|
8004672: f003 0301 and.w r3, r3, #1
|
|
8004676: 2b00 cmp r3, #0
|
|
8004678: d016 beq.n 80046a8 <HAL_RCCEx_PeriphCLKConfig+0x238>
|
|
{
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
800467a: f7fd feef bl 800245c <HAL_GetTick>
|
|
800467e: 60f8 str r0, [r7, #12]
|
|
|
|
/* Wait till LSE is ready */
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
8004680: e00b b.n 800469a <HAL_RCCEx_PeriphCLKConfig+0x22a>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8004682: f7fd feeb bl 800245c <HAL_GetTick>
|
|
8004686: 4602 mov r2, r0
|
|
8004688: 68fb ldr r3, [r7, #12]
|
|
800468a: 1ad3 subs r3, r2, r3
|
|
800468c: f241 3288 movw r2, #5000 @ 0x1388
|
|
8004690: 4293 cmp r3, r2
|
|
8004692: d902 bls.n 800469a <HAL_RCCEx_PeriphCLKConfig+0x22a>
|
|
{
|
|
ret = HAL_TIMEOUT;
|
|
8004694: 2303 movs r3, #3
|
|
8004696: 74fb strb r3, [r7, #19]
|
|
break;
|
|
8004698: e006 b.n 80046a8 <HAL_RCCEx_PeriphCLKConfig+0x238>
|
|
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
|
|
800469a: 4b0d ldr r3, [pc, #52] @ (80046d0 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
800469c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
80046a0: f003 0302 and.w r3, r3, #2
|
|
80046a4: 2b00 cmp r3, #0
|
|
80046a6: d0ec beq.n 8004682 <HAL_RCCEx_PeriphCLKConfig+0x212>
|
|
}
|
|
}
|
|
}
|
|
|
|
if(ret == HAL_OK)
|
|
80046a8: 7cfb ldrb r3, [r7, #19]
|
|
80046aa: 2b00 cmp r3, #0
|
|
80046ac: d10c bne.n 80046c8 <HAL_RCCEx_PeriphCLKConfig+0x258>
|
|
{
|
|
/* Apply new RTC clock source selection */
|
|
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
|
80046ae: 4b08 ldr r3, [pc, #32] @ (80046d0 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
80046b0: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
|
|
80046b4: f423 7240 bic.w r2, r3, #768 @ 0x300
|
|
80046b8: 687b ldr r3, [r7, #4]
|
|
80046ba: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
80046be: 4904 ldr r1, [pc, #16] @ (80046d0 <HAL_RCCEx_PeriphCLKConfig+0x260>)
|
|
80046c0: 4313 orrs r3, r2
|
|
80046c2: f8c1 3090 str.w r3, [r1, #144] @ 0x90
|
|
80046c6: e009 b.n 80046dc <HAL_RCCEx_PeriphCLKConfig+0x26c>
|
|
}
|
|
else
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
80046c8: 7cfb ldrb r3, [r7, #19]
|
|
80046ca: 74bb strb r3, [r7, #18]
|
|
80046cc: e006 b.n 80046dc <HAL_RCCEx_PeriphCLKConfig+0x26c>
|
|
80046ce: bf00 nop
|
|
80046d0: 40021000 .word 0x40021000
|
|
80046d4: 40007000 .word 0x40007000
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
80046d8: 7cfb ldrb r3, [r7, #19]
|
|
80046da: 74bb strb r3, [r7, #18]
|
|
}
|
|
|
|
/* Restore clock configuration if changed */
|
|
if(pwrclkchanged == SET)
|
|
80046dc: 7c7b ldrb r3, [r7, #17]
|
|
80046de: 2b01 cmp r3, #1
|
|
80046e0: d105 bne.n 80046ee <HAL_RCCEx_PeriphCLKConfig+0x27e>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
80046e2: 4b9e ldr r3, [pc, #632] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80046e4: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
80046e6: 4a9d ldr r2, [pc, #628] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80046e8: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
80046ec: 6593 str r3, [r2, #88] @ 0x58
|
|
}
|
|
}
|
|
|
|
/*-------------------------- USART1 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
|
|
80046ee: 687b ldr r3, [r7, #4]
|
|
80046f0: 681b ldr r3, [r3, #0]
|
|
80046f2: f003 0301 and.w r3, r3, #1
|
|
80046f6: 2b00 cmp r3, #0
|
|
80046f8: d00a beq.n 8004710 <HAL_RCCEx_PeriphCLKConfig+0x2a0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
|
|
|
|
/* Configure the USART1 clock source */
|
|
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
|
|
80046fa: 4b98 ldr r3, [pc, #608] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80046fc: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8004700: f023 0203 bic.w r2, r3, #3
|
|
8004704: 687b ldr r3, [r7, #4]
|
|
8004706: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8004708: 4994 ldr r1, [pc, #592] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
800470a: 4313 orrs r3, r2
|
|
800470c: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
/*-------------------------- USART2 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
|
|
8004710: 687b ldr r3, [r7, #4]
|
|
8004712: 681b ldr r3, [r3, #0]
|
|
8004714: f003 0302 and.w r3, r3, #2
|
|
8004718: 2b00 cmp r3, #0
|
|
800471a: d00a beq.n 8004732 <HAL_RCCEx_PeriphCLKConfig+0x2c2>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
|
|
|
|
/* Configure the USART2 clock source */
|
|
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
|
|
800471c: 4b8f ldr r3, [pc, #572] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
800471e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8004722: f023 020c bic.w r2, r3, #12
|
|
8004726: 687b ldr r3, [r7, #4]
|
|
8004728: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
800472a: 498c ldr r1, [pc, #560] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
800472c: 4313 orrs r3, r2
|
|
800472e: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
#if defined(USART3)
|
|
|
|
/*-------------------------- USART3 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
|
|
8004732: 687b ldr r3, [r7, #4]
|
|
8004734: 681b ldr r3, [r3, #0]
|
|
8004736: f003 0304 and.w r3, r3, #4
|
|
800473a: 2b00 cmp r3, #0
|
|
800473c: d00a beq.n 8004754 <HAL_RCCEx_PeriphCLKConfig+0x2e4>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
|
|
|
|
/* Configure the USART3 clock source */
|
|
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
|
|
800473e: 4b87 ldr r3, [pc, #540] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8004740: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8004744: f023 0230 bic.w r2, r3, #48 @ 0x30
|
|
8004748: 687b ldr r3, [r7, #4]
|
|
800474a: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800474c: 4983 ldr r1, [pc, #524] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
800474e: 4313 orrs r3, r2
|
|
8004750: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
#endif /* USART3 */
|
|
|
|
#if defined(UART4)
|
|
|
|
/*-------------------------- UART4 clock source configuration --------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
|
|
8004754: 687b ldr r3, [r7, #4]
|
|
8004756: 681b ldr r3, [r3, #0]
|
|
8004758: f003 0308 and.w r3, r3, #8
|
|
800475c: 2b00 cmp r3, #0
|
|
800475e: d00a beq.n 8004776 <HAL_RCCEx_PeriphCLKConfig+0x306>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
|
|
|
|
/* Configure the UART4 clock source */
|
|
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
|
|
8004760: 4b7e ldr r3, [pc, #504] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8004762: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8004766: f023 02c0 bic.w r2, r3, #192 @ 0xc0
|
|
800476a: 687b ldr r3, [r7, #4]
|
|
800476c: 6c5b ldr r3, [r3, #68] @ 0x44
|
|
800476e: 497b ldr r1, [pc, #492] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8004770: 4313 orrs r3, r2
|
|
8004772: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
#endif /* UART4 */
|
|
|
|
#if defined(UART5)
|
|
|
|
/*-------------------------- UART5 clock source configuration --------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
|
|
8004776: 687b ldr r3, [r7, #4]
|
|
8004778: 681b ldr r3, [r3, #0]
|
|
800477a: f003 0310 and.w r3, r3, #16
|
|
800477e: 2b00 cmp r3, #0
|
|
8004780: d00a beq.n 8004798 <HAL_RCCEx_PeriphCLKConfig+0x328>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
|
|
|
|
/* Configure the UART5 clock source */
|
|
__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
|
|
8004782: 4b76 ldr r3, [pc, #472] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8004784: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8004788: f423 7240 bic.w r2, r3, #768 @ 0x300
|
|
800478c: 687b ldr r3, [r7, #4]
|
|
800478e: 6c9b ldr r3, [r3, #72] @ 0x48
|
|
8004790: 4972 ldr r1, [pc, #456] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8004792: 4313 orrs r3, r2
|
|
8004794: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
#endif /* UART5 */
|
|
|
|
/*-------------------------- LPUART1 clock source configuration ------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
|
|
8004798: 687b ldr r3, [r7, #4]
|
|
800479a: 681b ldr r3, [r3, #0]
|
|
800479c: f003 0320 and.w r3, r3, #32
|
|
80047a0: 2b00 cmp r3, #0
|
|
80047a2: d00a beq.n 80047ba <HAL_RCCEx_PeriphCLKConfig+0x34a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
|
|
|
|
/* Configure the LPUART1 clock source */
|
|
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
|
|
80047a4: 4b6d ldr r3, [pc, #436] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80047a6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80047aa: f423 6240 bic.w r2, r3, #3072 @ 0xc00
|
|
80047ae: 687b ldr r3, [r7, #4]
|
|
80047b0: 6cdb ldr r3, [r3, #76] @ 0x4c
|
|
80047b2: 496a ldr r1, [pc, #424] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80047b4: 4313 orrs r3, r2
|
|
80047b6: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
/*-------------------------- LPTIM1 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
|
|
80047ba: 687b ldr r3, [r7, #4]
|
|
80047bc: 681b ldr r3, [r3, #0]
|
|
80047be: f403 7300 and.w r3, r3, #512 @ 0x200
|
|
80047c2: 2b00 cmp r3, #0
|
|
80047c4: d00a beq.n 80047dc <HAL_RCCEx_PeriphCLKConfig+0x36c>
|
|
{
|
|
assert_param(IS_RCC_LPTIM1CLK(PeriphClkInit->Lptim1ClockSelection));
|
|
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
|
|
80047c6: 4b65 ldr r3, [pc, #404] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80047c8: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80047cc: f423 2240 bic.w r2, r3, #786432 @ 0xc0000
|
|
80047d0: 687b ldr r3, [r7, #4]
|
|
80047d2: 6ddb ldr r3, [r3, #92] @ 0x5c
|
|
80047d4: 4961 ldr r1, [pc, #388] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80047d6: 4313 orrs r3, r2
|
|
80047d8: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
/*-------------------------- LPTIM2 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2))
|
|
80047dc: 687b ldr r3, [r7, #4]
|
|
80047de: 681b ldr r3, [r3, #0]
|
|
80047e0: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
80047e4: 2b00 cmp r3, #0
|
|
80047e6: d00a beq.n 80047fe <HAL_RCCEx_PeriphCLKConfig+0x38e>
|
|
{
|
|
assert_param(IS_RCC_LPTIM2CLK(PeriphClkInit->Lptim2ClockSelection));
|
|
__HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection);
|
|
80047e8: 4b5c ldr r3, [pc, #368] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80047ea: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80047ee: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
|
|
80047f2: 687b ldr r3, [r7, #4]
|
|
80047f4: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
80047f6: 4959 ldr r1, [pc, #356] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80047f8: 4313 orrs r3, r2
|
|
80047fa: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
/*-------------------------- I2C1 clock source configuration ---------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
|
|
80047fe: 687b ldr r3, [r7, #4]
|
|
8004800: 681b ldr r3, [r3, #0]
|
|
8004802: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8004806: 2b00 cmp r3, #0
|
|
8004808: d00a beq.n 8004820 <HAL_RCCEx_PeriphCLKConfig+0x3b0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
|
|
|
|
/* Configure the I2C1 clock source */
|
|
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
|
|
800480a: 4b54 ldr r3, [pc, #336] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
800480c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8004810: f423 5240 bic.w r2, r3, #12288 @ 0x3000
|
|
8004814: 687b ldr r3, [r7, #4]
|
|
8004816: 6d1b ldr r3, [r3, #80] @ 0x50
|
|
8004818: 4950 ldr r1, [pc, #320] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
800481a: 4313 orrs r3, r2
|
|
800481c: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
#if defined(I2C2)
|
|
|
|
/*-------------------------- I2C2 clock source configuration ---------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
|
|
8004820: 687b ldr r3, [r7, #4]
|
|
8004822: 681b ldr r3, [r3, #0]
|
|
8004824: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8004828: 2b00 cmp r3, #0
|
|
800482a: d00a beq.n 8004842 <HAL_RCCEx_PeriphCLKConfig+0x3d2>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
|
|
|
|
/* Configure the I2C2 clock source */
|
|
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
|
|
800482c: 4b4b ldr r3, [pc, #300] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
800482e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8004832: f423 4240 bic.w r2, r3, #49152 @ 0xc000
|
|
8004836: 687b ldr r3, [r7, #4]
|
|
8004838: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
800483a: 4948 ldr r1, [pc, #288] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
800483c: 4313 orrs r3, r2
|
|
800483e: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
|
|
#endif /* I2C2 */
|
|
|
|
/*-------------------------- I2C3 clock source configuration ---------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
|
|
8004842: 687b ldr r3, [r7, #4]
|
|
8004844: 681b ldr r3, [r3, #0]
|
|
8004846: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
800484a: 2b00 cmp r3, #0
|
|
800484c: d00a beq.n 8004864 <HAL_RCCEx_PeriphCLKConfig+0x3f4>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
|
|
|
|
/* Configure the I2C3 clock source */
|
|
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
|
|
800484e: 4b43 ldr r3, [pc, #268] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8004850: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8004854: f423 3240 bic.w r2, r3, #196608 @ 0x30000
|
|
8004858: 687b ldr r3, [r7, #4]
|
|
800485a: 6d9b ldr r3, [r3, #88] @ 0x58
|
|
800485c: 493f ldr r1, [pc, #252] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
800485e: 4313 orrs r3, r2
|
|
8004860: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
#endif /* I2C4 */
|
|
|
|
#if defined(USB_OTG_FS) || defined(USB)
|
|
|
|
/*-------------------------- USB clock source configuration ----------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
|
|
8004864: 687b ldr r3, [r7, #4]
|
|
8004866: 681b ldr r3, [r3, #0]
|
|
8004868: f403 5300 and.w r3, r3, #8192 @ 0x2000
|
|
800486c: 2b00 cmp r3, #0
|
|
800486e: d028 beq.n 80048c2 <HAL_RCCEx_PeriphCLKConfig+0x452>
|
|
{
|
|
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
|
|
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
|
|
8004870: 4b3a ldr r3, [pc, #232] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8004872: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8004876: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
|
|
800487a: 687b ldr r3, [r7, #4]
|
|
800487c: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
800487e: 4937 ldr r1, [pc, #220] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8004880: 4313 orrs r3, r2
|
|
8004882: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
|
|
if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
|
|
8004886: 687b ldr r3, [r7, #4]
|
|
8004888: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
800488a: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
800488e: d106 bne.n 800489e <HAL_RCCEx_PeriphCLKConfig+0x42e>
|
|
{
|
|
/* Enable PLL48M1CLK output clock */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
|
|
8004890: 4b32 ldr r3, [pc, #200] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8004892: 68db ldr r3, [r3, #12]
|
|
8004894: 4a31 ldr r2, [pc, #196] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8004896: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
800489a: 60d3 str r3, [r2, #12]
|
|
800489c: e011 b.n 80048c2 <HAL_RCCEx_PeriphCLKConfig+0x452>
|
|
}
|
|
else
|
|
{
|
|
#if defined(RCC_PLLSAI1_SUPPORT)
|
|
if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1)
|
|
800489e: 687b ldr r3, [r7, #4]
|
|
80048a0: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
80048a2: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
|
|
80048a6: d10c bne.n 80048c2 <HAL_RCCEx_PeriphCLKConfig+0x452>
|
|
{
|
|
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
|
|
80048a8: 687b ldr r3, [r7, #4]
|
|
80048aa: 3304 adds r3, #4
|
|
80048ac: 2101 movs r1, #1
|
|
80048ae: 4618 mov r0, r3
|
|
80048b0: f000 f8c8 bl 8004a44 <RCCEx_PLLSAI1_Config>
|
|
80048b4: 4603 mov r3, r0
|
|
80048b6: 74fb strb r3, [r7, #19]
|
|
|
|
if(ret != HAL_OK)
|
|
80048b8: 7cfb ldrb r3, [r7, #19]
|
|
80048ba: 2b00 cmp r3, #0
|
|
80048bc: d001 beq.n 80048c2 <HAL_RCCEx_PeriphCLKConfig+0x452>
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
80048be: 7cfb ldrb r3, [r7, #19]
|
|
80048c0: 74bb strb r3, [r7, #18]
|
|
#endif /* USB_OTG_FS || USB */
|
|
|
|
#if defined(SDMMC1)
|
|
|
|
/*-------------------------- SDMMC1 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC1) == (RCC_PERIPHCLK_SDMMC1))
|
|
80048c2: 687b ldr r3, [r7, #4]
|
|
80048c4: 681b ldr r3, [r3, #0]
|
|
80048c6: f403 2300 and.w r3, r3, #524288 @ 0x80000
|
|
80048ca: 2b00 cmp r3, #0
|
|
80048cc: d028 beq.n 8004920 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
|
|
{
|
|
assert_param(IS_RCC_SDMMC1CLKSOURCE(PeriphClkInit->Sdmmc1ClockSelection));
|
|
__HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
|
|
80048ce: 4b23 ldr r3, [pc, #140] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80048d0: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80048d4: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
|
|
80048d8: 687b ldr r3, [r7, #4]
|
|
80048da: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
80048dc: 491f ldr r1, [pc, #124] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80048de: 4313 orrs r3, r2
|
|
80048e0: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
|
|
if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLL) /* PLL "Q" ? */
|
|
80048e4: 687b ldr r3, [r7, #4]
|
|
80048e6: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
80048e8: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
80048ec: d106 bne.n 80048fc <HAL_RCCEx_PeriphCLKConfig+0x48c>
|
|
{
|
|
/* Enable PLL48M1CLK output clock */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
|
|
80048ee: 4b1b ldr r3, [pc, #108] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80048f0: 68db ldr r3, [r3, #12]
|
|
80048f2: 4a1a ldr r2, [pc, #104] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
80048f4: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
80048f8: 60d3 str r3, [r2, #12]
|
|
80048fa: e011 b.n 8004920 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
|
|
{
|
|
/* Enable PLLSAI3CLK output */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SAI3CLK);
|
|
}
|
|
#endif
|
|
else if(PeriphClkInit->Sdmmc1ClockSelection == RCC_SDMMC1CLKSOURCE_PLLSAI1)
|
|
80048fc: 687b ldr r3, [r7, #4]
|
|
80048fe: 6f1b ldr r3, [r3, #112] @ 0x70
|
|
8004900: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
|
|
8004904: d10c bne.n 8004920 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
|
|
{
|
|
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
|
|
8004906: 687b ldr r3, [r7, #4]
|
|
8004908: 3304 adds r3, #4
|
|
800490a: 2101 movs r1, #1
|
|
800490c: 4618 mov r0, r3
|
|
800490e: f000 f899 bl 8004a44 <RCCEx_PLLSAI1_Config>
|
|
8004912: 4603 mov r3, r0
|
|
8004914: 74fb strb r3, [r7, #19]
|
|
|
|
if(ret != HAL_OK)
|
|
8004916: 7cfb ldrb r3, [r7, #19]
|
|
8004918: 2b00 cmp r3, #0
|
|
800491a: d001 beq.n 8004920 <HAL_RCCEx_PeriphCLKConfig+0x4b0>
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
800491c: 7cfb ldrb r3, [r7, #19]
|
|
800491e: 74bb strb r3, [r7, #18]
|
|
}
|
|
|
|
#endif /* SDMMC1 */
|
|
|
|
/*-------------------------- RNG clock source configuration ----------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
|
|
8004920: 687b ldr r3, [r7, #4]
|
|
8004922: 681b ldr r3, [r3, #0]
|
|
8004924: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
8004928: 2b00 cmp r3, #0
|
|
800492a: d02b beq.n 8004984 <HAL_RCCEx_PeriphCLKConfig+0x514>
|
|
{
|
|
assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
|
|
__HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
|
|
800492c: 4b0b ldr r3, [pc, #44] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
800492e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8004932: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
|
|
8004936: 687b ldr r3, [r7, #4]
|
|
8004938: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
800493a: 4908 ldr r1, [pc, #32] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
800493c: 4313 orrs r3, r2
|
|
800493e: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
|
|
if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
|
|
8004942: 687b ldr r3, [r7, #4]
|
|
8004944: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
8004946: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
|
|
800494a: d109 bne.n 8004960 <HAL_RCCEx_PeriphCLKConfig+0x4f0>
|
|
{
|
|
/* Enable PLL48M1CLK output clock */
|
|
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
|
|
800494c: 4b03 ldr r3, [pc, #12] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
800494e: 68db ldr r3, [r3, #12]
|
|
8004950: 4a02 ldr r2, [pc, #8] @ (800495c <HAL_RCCEx_PeriphCLKConfig+0x4ec>)
|
|
8004952: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
8004956: 60d3 str r3, [r2, #12]
|
|
8004958: e014 b.n 8004984 <HAL_RCCEx_PeriphCLKConfig+0x514>
|
|
800495a: bf00 nop
|
|
800495c: 40021000 .word 0x40021000
|
|
}
|
|
#if defined(RCC_PLLSAI1_SUPPORT)
|
|
else if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLLSAI1)
|
|
8004960: 687b ldr r3, [r7, #4]
|
|
8004962: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
8004964: f1b3 6f80 cmp.w r3, #67108864 @ 0x4000000
|
|
8004968: d10c bne.n 8004984 <HAL_RCCEx_PeriphCLKConfig+0x514>
|
|
{
|
|
/* PLLSAI1 input clock, parameters M, N & Q configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_Q_UPDATE);
|
|
800496a: 687b ldr r3, [r7, #4]
|
|
800496c: 3304 adds r3, #4
|
|
800496e: 2101 movs r1, #1
|
|
8004970: 4618 mov r0, r3
|
|
8004972: f000 f867 bl 8004a44 <RCCEx_PLLSAI1_Config>
|
|
8004976: 4603 mov r3, r0
|
|
8004978: 74fb strb r3, [r7, #19]
|
|
|
|
if(ret != HAL_OK)
|
|
800497a: 7cfb ldrb r3, [r7, #19]
|
|
800497c: 2b00 cmp r3, #0
|
|
800497e: d001 beq.n 8004984 <HAL_RCCEx_PeriphCLKConfig+0x514>
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
8004980: 7cfb ldrb r3, [r7, #19]
|
|
8004982: 74bb strb r3, [r7, #18]
|
|
}
|
|
}
|
|
|
|
/*-------------------------- ADC clock source configuration ----------------------*/
|
|
#if !defined(STM32L412xx) && !defined(STM32L422xx)
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
|
|
8004984: 687b ldr r3, [r7, #4]
|
|
8004986: 681b ldr r3, [r3, #0]
|
|
8004988: f403 4380 and.w r3, r3, #16384 @ 0x4000
|
|
800498c: 2b00 cmp r3, #0
|
|
800498e: d02f beq.n 80049f0 <HAL_RCCEx_PeriphCLKConfig+0x580>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
|
|
|
|
/* Configure the ADC interface clock source */
|
|
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
|
|
8004990: 4b2b ldr r3, [pc, #172] @ (8004a40 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
|
|
8004992: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8004996: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000
|
|
800499a: 687b ldr r3, [r7, #4]
|
|
800499c: 6f9b ldr r3, [r3, #120] @ 0x78
|
|
800499e: 4928 ldr r1, [pc, #160] @ (8004a40 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
|
|
80049a0: 4313 orrs r3, r2
|
|
80049a2: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
|
|
#if defined(RCC_PLLSAI1_SUPPORT)
|
|
if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)
|
|
80049a6: 687b ldr r3, [r7, #4]
|
|
80049a8: 6f9b ldr r3, [r3, #120] @ 0x78
|
|
80049aa: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
|
|
80049ae: d10d bne.n 80049cc <HAL_RCCEx_PeriphCLKConfig+0x55c>
|
|
{
|
|
/* PLLSAI1 input clock, parameters M, N & R configuration and clock output (PLLSAI1ClockOut) */
|
|
ret = RCCEx_PLLSAI1_Config(&(PeriphClkInit->PLLSAI1), DIVIDER_R_UPDATE);
|
|
80049b0: 687b ldr r3, [r7, #4]
|
|
80049b2: 3304 adds r3, #4
|
|
80049b4: 2102 movs r1, #2
|
|
80049b6: 4618 mov r0, r3
|
|
80049b8: f000 f844 bl 8004a44 <RCCEx_PLLSAI1_Config>
|
|
80049bc: 4603 mov r3, r0
|
|
80049be: 74fb strb r3, [r7, #19]
|
|
|
|
if(ret != HAL_OK)
|
|
80049c0: 7cfb ldrb r3, [r7, #19]
|
|
80049c2: 2b00 cmp r3, #0
|
|
80049c4: d014 beq.n 80049f0 <HAL_RCCEx_PeriphCLKConfig+0x580>
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
80049c6: 7cfb ldrb r3, [r7, #19]
|
|
80049c8: 74bb strb r3, [r7, #18]
|
|
80049ca: e011 b.n 80049f0 <HAL_RCCEx_PeriphCLKConfig+0x580>
|
|
}
|
|
#endif /* RCC_PLLSAI1_SUPPORT */
|
|
|
|
#if defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || defined(STM32L496xx) || defined(STM32L4A6xx)
|
|
|
|
else if(PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI2)
|
|
80049cc: 687b ldr r3, [r7, #4]
|
|
80049ce: 6f9b ldr r3, [r3, #120] @ 0x78
|
|
80049d0: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
|
|
80049d4: d10c bne.n 80049f0 <HAL_RCCEx_PeriphCLKConfig+0x580>
|
|
{
|
|
/* PLLSAI2 input clock, parameters M, N & R configuration and clock output (PLLSAI2ClockOut) */
|
|
ret = RCCEx_PLLSAI2_Config(&(PeriphClkInit->PLLSAI2), DIVIDER_R_UPDATE);
|
|
80049d6: 687b ldr r3, [r7, #4]
|
|
80049d8: 3320 adds r3, #32
|
|
80049da: 2102 movs r1, #2
|
|
80049dc: 4618 mov r0, r3
|
|
80049de: f000 f925 bl 8004c2c <RCCEx_PLLSAI2_Config>
|
|
80049e2: 4603 mov r3, r0
|
|
80049e4: 74fb strb r3, [r7, #19]
|
|
|
|
if(ret != HAL_OK)
|
|
80049e6: 7cfb ldrb r3, [r7, #19]
|
|
80049e8: 2b00 cmp r3, #0
|
|
80049ea: d001 beq.n 80049f0 <HAL_RCCEx_PeriphCLKConfig+0x580>
|
|
{
|
|
/* set overall return value */
|
|
status = ret;
|
|
80049ec: 7cfb ldrb r3, [r7, #19]
|
|
80049ee: 74bb strb r3, [r7, #18]
|
|
#endif /* !STM32L412xx && !STM32L422xx */
|
|
|
|
#if defined(SWPMI1)
|
|
|
|
/*-------------------------- SWPMI1 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SWPMI1) == RCC_PERIPHCLK_SWPMI1)
|
|
80049f0: 687b ldr r3, [r7, #4]
|
|
80049f2: 681b ldr r3, [r3, #0]
|
|
80049f4: f403 4300 and.w r3, r3, #32768 @ 0x8000
|
|
80049f8: 2b00 cmp r3, #0
|
|
80049fa: d00a beq.n 8004a12 <HAL_RCCEx_PeriphCLKConfig+0x5a2>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_SWPMI1CLKSOURCE(PeriphClkInit->Swpmi1ClockSelection));
|
|
|
|
/* Configure the SWPMI1 clock source */
|
|
__HAL_RCC_SWPMI1_CONFIG(PeriphClkInit->Swpmi1ClockSelection);
|
|
80049fc: 4b10 ldr r3, [pc, #64] @ (8004a40 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
|
|
80049fe: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8004a02: f023 4280 bic.w r2, r3, #1073741824 @ 0x40000000
|
|
8004a06: 687b ldr r3, [r7, #4]
|
|
8004a08: 6fdb ldr r3, [r3, #124] @ 0x7c
|
|
8004a0a: 490d ldr r1, [pc, #52] @ (8004a40 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
|
|
8004a0c: 4313 orrs r3, r2
|
|
8004a0e: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
#endif /* SWPMI1 */
|
|
|
|
#if defined(DFSDM1_Filter0)
|
|
|
|
/*-------------------------- DFSDM1 clock source configuration -------------------*/
|
|
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
|
|
8004a12: 687b ldr r3, [r7, #4]
|
|
8004a14: 681b ldr r3, [r3, #0]
|
|
8004a16: f403 3380 and.w r3, r3, #65536 @ 0x10000
|
|
8004a1a: 2b00 cmp r3, #0
|
|
8004a1c: d00b beq.n 8004a36 <HAL_RCCEx_PeriphCLKConfig+0x5c6>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
|
|
|
|
/* Configure the DFSDM1 interface clock source */
|
|
__HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
|
|
8004a1e: 4b08 ldr r3, [pc, #32] @ (8004a40 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
|
|
8004a20: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8004a24: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000
|
|
8004a28: 687b ldr r3, [r7, #4]
|
|
8004a2a: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
8004a2e: 4904 ldr r1, [pc, #16] @ (8004a40 <HAL_RCCEx_PeriphCLKConfig+0x5d0>)
|
|
8004a30: 4313 orrs r3, r2
|
|
8004a32: f8c1 3088 str.w r3, [r1, #136] @ 0x88
|
|
}
|
|
}
|
|
|
|
#endif /* OCTOSPI1 || OCTOSPI2 */
|
|
|
|
return status;
|
|
8004a36: 7cbb ldrb r3, [r7, #18]
|
|
}
|
|
8004a38: 4618 mov r0, r3
|
|
8004a3a: 3718 adds r7, #24
|
|
8004a3c: 46bd mov sp, r7
|
|
8004a3e: bd80 pop {r7, pc}
|
|
8004a40: 40021000 .word 0x40021000
|
|
|
|
08004a44 <RCCEx_PLLSAI1_Config>:
|
|
* @note PLLSAI1 is temporary disable to apply new parameters
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *PllSai1, uint32_t Divider)
|
|
{
|
|
8004a44: b580 push {r7, lr}
|
|
8004a46: b084 sub sp, #16
|
|
8004a48: af00 add r7, sp, #0
|
|
8004a4a: 6078 str r0, [r7, #4]
|
|
8004a4c: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8004a4e: 2300 movs r3, #0
|
|
8004a50: 73fb strb r3, [r7, #15]
|
|
assert_param(IS_RCC_PLLSAI1M_VALUE(PllSai1->PLLSAI1M));
|
|
assert_param(IS_RCC_PLLSAI1N_VALUE(PllSai1->PLLSAI1N));
|
|
assert_param(IS_RCC_PLLSAI1CLOCKOUT_VALUE(PllSai1->PLLSAI1ClockOut));
|
|
|
|
/* Check that PLLSAI1 clock source and divider M can be applied */
|
|
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
|
|
8004a52: 4b75 ldr r3, [pc, #468] @ (8004c28 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8004a54: 68db ldr r3, [r3, #12]
|
|
8004a56: f003 0303 and.w r3, r3, #3
|
|
8004a5a: 2b00 cmp r3, #0
|
|
8004a5c: d018 beq.n 8004a90 <RCCEx_PLLSAI1_Config+0x4c>
|
|
{
|
|
/* PLL clock source and divider M already set, check that no request for change */
|
|
if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai1->PLLSAI1Source)
|
|
8004a5e: 4b72 ldr r3, [pc, #456] @ (8004c28 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8004a60: 68db ldr r3, [r3, #12]
|
|
8004a62: f003 0203 and.w r2, r3, #3
|
|
8004a66: 687b ldr r3, [r7, #4]
|
|
8004a68: 681b ldr r3, [r3, #0]
|
|
8004a6a: 429a cmp r2, r3
|
|
8004a6c: d10d bne.n 8004a8a <RCCEx_PLLSAI1_Config+0x46>
|
|
||
|
|
(PllSai1->PLLSAI1Source == RCC_PLLSOURCE_NONE)
|
|
8004a6e: 687b ldr r3, [r7, #4]
|
|
8004a70: 681b ldr r3, [r3, #0]
|
|
||
|
|
8004a72: 2b00 cmp r3, #0
|
|
8004a74: d009 beq.n 8004a8a <RCCEx_PLLSAI1_Config+0x46>
|
|
#if !defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
|
|
||
|
|
(((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai1->PLLSAI1M)
|
|
8004a76: 4b6c ldr r3, [pc, #432] @ (8004c28 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8004a78: 68db ldr r3, [r3, #12]
|
|
8004a7a: 091b lsrs r3, r3, #4
|
|
8004a7c: f003 0307 and.w r3, r3, #7
|
|
8004a80: 1c5a adds r2, r3, #1
|
|
8004a82: 687b ldr r3, [r7, #4]
|
|
8004a84: 685b ldr r3, [r3, #4]
|
|
||
|
|
8004a86: 429a cmp r2, r3
|
|
8004a88: d047 beq.n 8004b1a <RCCEx_PLLSAI1_Config+0xd6>
|
|
#endif
|
|
)
|
|
{
|
|
status = HAL_ERROR;
|
|
8004a8a: 2301 movs r3, #1
|
|
8004a8c: 73fb strb r3, [r7, #15]
|
|
8004a8e: e044 b.n 8004b1a <RCCEx_PLLSAI1_Config+0xd6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check PLLSAI1 clock source availability */
|
|
switch(PllSai1->PLLSAI1Source)
|
|
8004a90: 687b ldr r3, [r7, #4]
|
|
8004a92: 681b ldr r3, [r3, #0]
|
|
8004a94: 2b03 cmp r3, #3
|
|
8004a96: d018 beq.n 8004aca <RCCEx_PLLSAI1_Config+0x86>
|
|
8004a98: 2b03 cmp r3, #3
|
|
8004a9a: d825 bhi.n 8004ae8 <RCCEx_PLLSAI1_Config+0xa4>
|
|
8004a9c: 2b01 cmp r3, #1
|
|
8004a9e: d002 beq.n 8004aa6 <RCCEx_PLLSAI1_Config+0x62>
|
|
8004aa0: 2b02 cmp r3, #2
|
|
8004aa2: d009 beq.n 8004ab8 <RCCEx_PLLSAI1_Config+0x74>
|
|
8004aa4: e020 b.n 8004ae8 <RCCEx_PLLSAI1_Config+0xa4>
|
|
{
|
|
case RCC_PLLSOURCE_MSI:
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
|
|
8004aa6: 4b60 ldr r3, [pc, #384] @ (8004c28 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8004aa8: 681b ldr r3, [r3, #0]
|
|
8004aaa: f003 0302 and.w r3, r3, #2
|
|
8004aae: 2b00 cmp r3, #0
|
|
8004ab0: d11d bne.n 8004aee <RCCEx_PLLSAI1_Config+0xaa>
|
|
{
|
|
status = HAL_ERROR;
|
|
8004ab2: 2301 movs r3, #1
|
|
8004ab4: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
8004ab6: e01a b.n 8004aee <RCCEx_PLLSAI1_Config+0xaa>
|
|
case RCC_PLLSOURCE_HSI:
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
|
|
8004ab8: 4b5b ldr r3, [pc, #364] @ (8004c28 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8004aba: 681b ldr r3, [r3, #0]
|
|
8004abc: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8004ac0: 2b00 cmp r3, #0
|
|
8004ac2: d116 bne.n 8004af2 <RCCEx_PLLSAI1_Config+0xae>
|
|
{
|
|
status = HAL_ERROR;
|
|
8004ac4: 2301 movs r3, #1
|
|
8004ac6: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
8004ac8: e013 b.n 8004af2 <RCCEx_PLLSAI1_Config+0xae>
|
|
case RCC_PLLSOURCE_HSE:
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
|
|
8004aca: 4b57 ldr r3, [pc, #348] @ (8004c28 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8004acc: 681b ldr r3, [r3, #0]
|
|
8004ace: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8004ad2: 2b00 cmp r3, #0
|
|
8004ad4: d10f bne.n 8004af6 <RCCEx_PLLSAI1_Config+0xb2>
|
|
{
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
|
|
8004ad6: 4b54 ldr r3, [pc, #336] @ (8004c28 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8004ad8: 681b ldr r3, [r3, #0]
|
|
8004ada: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
8004ade: 2b00 cmp r3, #0
|
|
8004ae0: d109 bne.n 8004af6 <RCCEx_PLLSAI1_Config+0xb2>
|
|
{
|
|
status = HAL_ERROR;
|
|
8004ae2: 2301 movs r3, #1
|
|
8004ae4: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
break;
|
|
8004ae6: e006 b.n 8004af6 <RCCEx_PLLSAI1_Config+0xb2>
|
|
default:
|
|
status = HAL_ERROR;
|
|
8004ae8: 2301 movs r3, #1
|
|
8004aea: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8004aec: e004 b.n 8004af8 <RCCEx_PLLSAI1_Config+0xb4>
|
|
break;
|
|
8004aee: bf00 nop
|
|
8004af0: e002 b.n 8004af8 <RCCEx_PLLSAI1_Config+0xb4>
|
|
break;
|
|
8004af2: bf00 nop
|
|
8004af4: e000 b.n 8004af8 <RCCEx_PLLSAI1_Config+0xb4>
|
|
break;
|
|
8004af6: bf00 nop
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
8004af8: 7bfb ldrb r3, [r7, #15]
|
|
8004afa: 2b00 cmp r3, #0
|
|
8004afc: d10d bne.n 8004b1a <RCCEx_PLLSAI1_Config+0xd6>
|
|
#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
|
|
/* Set PLLSAI1 clock source */
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai1->PLLSAI1Source);
|
|
#else
|
|
/* Set PLLSAI1 clock source and divider M */
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai1->PLLSAI1Source | (PllSai1->PLLSAI1M - 1U) << RCC_PLLCFGR_PLLM_Pos);
|
|
8004afe: 4b4a ldr r3, [pc, #296] @ (8004c28 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8004b00: 68db ldr r3, [r3, #12]
|
|
8004b02: f023 0273 bic.w r2, r3, #115 @ 0x73
|
|
8004b06: 687b ldr r3, [r7, #4]
|
|
8004b08: 6819 ldr r1, [r3, #0]
|
|
8004b0a: 687b ldr r3, [r7, #4]
|
|
8004b0c: 685b ldr r3, [r3, #4]
|
|
8004b0e: 3b01 subs r3, #1
|
|
8004b10: 011b lsls r3, r3, #4
|
|
8004b12: 430b orrs r3, r1
|
|
8004b14: 4944 ldr r1, [pc, #272] @ (8004c28 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8004b16: 4313 orrs r3, r2
|
|
8004b18: 60cb str r3, [r1, #12]
|
|
#endif
|
|
}
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
8004b1a: 7bfb ldrb r3, [r7, #15]
|
|
8004b1c: 2b00 cmp r3, #0
|
|
8004b1e: d17d bne.n 8004c1c <RCCEx_PLLSAI1_Config+0x1d8>
|
|
{
|
|
/* Disable the PLLSAI1 */
|
|
__HAL_RCC_PLLSAI1_DISABLE();
|
|
8004b20: 4b41 ldr r3, [pc, #260] @ (8004c28 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8004b22: 681b ldr r3, [r3, #0]
|
|
8004b24: 4a40 ldr r2, [pc, #256] @ (8004c28 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8004b26: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
|
|
8004b2a: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8004b2c: f7fd fc96 bl 800245c <HAL_GetTick>
|
|
8004b30: 60b8 str r0, [r7, #8]
|
|
|
|
/* Wait till PLLSAI1 is ready to be updated */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
|
|
8004b32: e009 b.n 8004b48 <RCCEx_PLLSAI1_Config+0x104>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
|
|
8004b34: f7fd fc92 bl 800245c <HAL_GetTick>
|
|
8004b38: 4602 mov r2, r0
|
|
8004b3a: 68bb ldr r3, [r7, #8]
|
|
8004b3c: 1ad3 subs r3, r2, r3
|
|
8004b3e: 2b02 cmp r3, #2
|
|
8004b40: d902 bls.n 8004b48 <RCCEx_PLLSAI1_Config+0x104>
|
|
{
|
|
status = HAL_TIMEOUT;
|
|
8004b42: 2303 movs r3, #3
|
|
8004b44: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8004b46: e005 b.n 8004b54 <RCCEx_PLLSAI1_Config+0x110>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) != 0U)
|
|
8004b48: 4b37 ldr r3, [pc, #220] @ (8004c28 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8004b4a: 681b ldr r3, [r3, #0]
|
|
8004b4c: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
|
|
8004b50: 2b00 cmp r3, #0
|
|
8004b52: d1ef bne.n 8004b34 <RCCEx_PLLSAI1_Config+0xf0>
|
|
}
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
8004b54: 7bfb ldrb r3, [r7, #15]
|
|
8004b56: 2b00 cmp r3, #0
|
|
8004b58: d160 bne.n 8004c1c <RCCEx_PLLSAI1_Config+0x1d8>
|
|
{
|
|
if(Divider == DIVIDER_P_UPDATE)
|
|
8004b5a: 683b ldr r3, [r7, #0]
|
|
8004b5c: 2b00 cmp r3, #0
|
|
8004b5e: d111 bne.n 8004b84 <RCCEx_PLLSAI1_Config+0x140>
|
|
MODIFY_REG(RCC->PLLSAI1CFGR,
|
|
RCC_PLLSAI1CFGR_PLLSAI1N | RCC_PLLSAI1CFGR_PLLSAI1PDIV,
|
|
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
|
|
(PllSai1->PLLSAI1P << RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos));
|
|
#else
|
|
MODIFY_REG(RCC->PLLSAI1CFGR,
|
|
8004b60: 4b31 ldr r3, [pc, #196] @ (8004c28 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8004b62: 691b ldr r3, [r3, #16]
|
|
8004b64: f423 331f bic.w r3, r3, #162816 @ 0x27c00
|
|
8004b68: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8004b6c: 687a ldr r2, [r7, #4]
|
|
8004b6e: 6892 ldr r2, [r2, #8]
|
|
8004b70: 0211 lsls r1, r2, #8
|
|
8004b72: 687a ldr r2, [r7, #4]
|
|
8004b74: 68d2 ldr r2, [r2, #12]
|
|
8004b76: 0912 lsrs r2, r2, #4
|
|
8004b78: 0452 lsls r2, r2, #17
|
|
8004b7a: 430a orrs r2, r1
|
|
8004b7c: 492a ldr r1, [pc, #168] @ (8004c28 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8004b7e: 4313 orrs r3, r2
|
|
8004b80: 610b str r3, [r1, #16]
|
|
8004b82: e027 b.n 8004bd4 <RCCEx_PLLSAI1_Config+0x190>
|
|
((PllSai1->PLLSAI1P >> 4U) << RCC_PLLSAI1CFGR_PLLSAI1P_Pos));
|
|
#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
|
|
|
|
#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
|
|
}
|
|
else if(Divider == DIVIDER_Q_UPDATE)
|
|
8004b84: 683b ldr r3, [r7, #0]
|
|
8004b86: 2b01 cmp r3, #1
|
|
8004b88: d112 bne.n 8004bb0 <RCCEx_PLLSAI1_Config+0x16c>
|
|
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
|
|
(((PllSai1->PLLSAI1Q >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) |
|
|
((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
|
|
#else
|
|
/* Configure the PLLSAI1 Division factor Q and Multiplication factor N*/
|
|
MODIFY_REG(RCC->PLLSAI1CFGR,
|
|
8004b8a: 4b27 ldr r3, [pc, #156] @ (8004c28 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8004b8c: 691b ldr r3, [r3, #16]
|
|
8004b8e: f423 03c0 bic.w r3, r3, #6291456 @ 0x600000
|
|
8004b92: f423 43fe bic.w r3, r3, #32512 @ 0x7f00
|
|
8004b96: 687a ldr r2, [r7, #4]
|
|
8004b98: 6892 ldr r2, [r2, #8]
|
|
8004b9a: 0211 lsls r1, r2, #8
|
|
8004b9c: 687a ldr r2, [r7, #4]
|
|
8004b9e: 6912 ldr r2, [r2, #16]
|
|
8004ba0: 0852 lsrs r2, r2, #1
|
|
8004ba2: 3a01 subs r2, #1
|
|
8004ba4: 0552 lsls r2, r2, #21
|
|
8004ba6: 430a orrs r2, r1
|
|
8004ba8: 491f ldr r1, [pc, #124] @ (8004c28 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8004baa: 4313 orrs r3, r2
|
|
8004bac: 610b str r3, [r1, #16]
|
|
8004bae: e011 b.n 8004bd4 <RCCEx_PLLSAI1_Config+0x190>
|
|
(PllSai1->PLLSAI1N << RCC_PLLSAI1CFGR_PLLSAI1N_Pos) |
|
|
(((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos) |
|
|
((PllSai1->PLLSAI1M - 1U) << RCC_PLLSAI1CFGR_PLLSAI1M_Pos));
|
|
#else
|
|
/* Configure the PLLSAI1 Division factor R and Multiplication factor N*/
|
|
MODIFY_REG(RCC->PLLSAI1CFGR,
|
|
8004bb0: 4b1d ldr r3, [pc, #116] @ (8004c28 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8004bb2: 691b ldr r3, [r3, #16]
|
|
8004bb4: f023 63c0 bic.w r3, r3, #100663296 @ 0x6000000
|
|
8004bb8: f423 43fe bic.w r3, r3, #32512 @ 0x7f00
|
|
8004bbc: 687a ldr r2, [r7, #4]
|
|
8004bbe: 6892 ldr r2, [r2, #8]
|
|
8004bc0: 0211 lsls r1, r2, #8
|
|
8004bc2: 687a ldr r2, [r7, #4]
|
|
8004bc4: 6952 ldr r2, [r2, #20]
|
|
8004bc6: 0852 lsrs r2, r2, #1
|
|
8004bc8: 3a01 subs r2, #1
|
|
8004bca: 0652 lsls r2, r2, #25
|
|
8004bcc: 430a orrs r2, r1
|
|
8004bce: 4916 ldr r1, [pc, #88] @ (8004c28 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8004bd0: 4313 orrs r3, r2
|
|
8004bd2: 610b str r3, [r1, #16]
|
|
(((PllSai1->PLLSAI1R >> 1U) - 1U) << RCC_PLLSAI1CFGR_PLLSAI1R_Pos));
|
|
#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
|
|
}
|
|
|
|
/* Enable the PLLSAI1 again by setting PLLSAI1ON to 1*/
|
|
__HAL_RCC_PLLSAI1_ENABLE();
|
|
8004bd4: 4b14 ldr r3, [pc, #80] @ (8004c28 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8004bd6: 681b ldr r3, [r3, #0]
|
|
8004bd8: 4a13 ldr r2, [pc, #76] @ (8004c28 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8004bda: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
|
|
8004bde: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8004be0: f7fd fc3c bl 800245c <HAL_GetTick>
|
|
8004be4: 60b8 str r0, [r7, #8]
|
|
|
|
/* Wait till PLLSAI1 is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
|
|
8004be6: e009 b.n 8004bfc <RCCEx_PLLSAI1_Config+0x1b8>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLLSAI1_TIMEOUT_VALUE)
|
|
8004be8: f7fd fc38 bl 800245c <HAL_GetTick>
|
|
8004bec: 4602 mov r2, r0
|
|
8004bee: 68bb ldr r3, [r7, #8]
|
|
8004bf0: 1ad3 subs r3, r2, r3
|
|
8004bf2: 2b02 cmp r3, #2
|
|
8004bf4: d902 bls.n 8004bfc <RCCEx_PLLSAI1_Config+0x1b8>
|
|
{
|
|
status = HAL_TIMEOUT;
|
|
8004bf6: 2303 movs r3, #3
|
|
8004bf8: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8004bfa: e005 b.n 8004c08 <RCCEx_PLLSAI1_Config+0x1c4>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == 0U)
|
|
8004bfc: 4b0a ldr r3, [pc, #40] @ (8004c28 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8004bfe: 681b ldr r3, [r3, #0]
|
|
8004c00: f003 6300 and.w r3, r3, #134217728 @ 0x8000000
|
|
8004c04: 2b00 cmp r3, #0
|
|
8004c06: d0ef beq.n 8004be8 <RCCEx_PLLSAI1_Config+0x1a4>
|
|
}
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
8004c08: 7bfb ldrb r3, [r7, #15]
|
|
8004c0a: 2b00 cmp r3, #0
|
|
8004c0c: d106 bne.n 8004c1c <RCCEx_PLLSAI1_Config+0x1d8>
|
|
{
|
|
/* Configure the PLLSAI1 Clock output(s) */
|
|
__HAL_RCC_PLLSAI1CLKOUT_ENABLE(PllSai1->PLLSAI1ClockOut);
|
|
8004c0e: 4b06 ldr r3, [pc, #24] @ (8004c28 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8004c10: 691a ldr r2, [r3, #16]
|
|
8004c12: 687b ldr r3, [r7, #4]
|
|
8004c14: 699b ldr r3, [r3, #24]
|
|
8004c16: 4904 ldr r1, [pc, #16] @ (8004c28 <RCCEx_PLLSAI1_Config+0x1e4>)
|
|
8004c18: 4313 orrs r3, r2
|
|
8004c1a: 610b str r3, [r1, #16]
|
|
}
|
|
}
|
|
}
|
|
|
|
return status;
|
|
8004c1c: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8004c1e: 4618 mov r0, r3
|
|
8004c20: 3710 adds r7, #16
|
|
8004c22: 46bd mov sp, r7
|
|
8004c24: bd80 pop {r7, pc}
|
|
8004c26: bf00 nop
|
|
8004c28: 40021000 .word 0x40021000
|
|
|
|
08004c2c <RCCEx_PLLSAI2_Config>:
|
|
* @note PLLSAI2 is temporary disable to apply new parameters
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *PllSai2, uint32_t Divider)
|
|
{
|
|
8004c2c: b580 push {r7, lr}
|
|
8004c2e: b084 sub sp, #16
|
|
8004c30: af00 add r7, sp, #0
|
|
8004c32: 6078 str r0, [r7, #4]
|
|
8004c34: 6039 str r1, [r7, #0]
|
|
uint32_t tickstart;
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
8004c36: 2300 movs r3, #0
|
|
8004c38: 73fb strb r3, [r7, #15]
|
|
assert_param(IS_RCC_PLLSAI2M_VALUE(PllSai2->PLLSAI2M));
|
|
assert_param(IS_RCC_PLLSAI2N_VALUE(PllSai2->PLLSAI2N));
|
|
assert_param(IS_RCC_PLLSAI2CLOCKOUT_VALUE(PllSai2->PLLSAI2ClockOut));
|
|
|
|
/* Check that PLLSAI2 clock source and divider M can be applied */
|
|
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_NONE)
|
|
8004c3a: 4b6a ldr r3, [pc, #424] @ (8004de4 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8004c3c: 68db ldr r3, [r3, #12]
|
|
8004c3e: f003 0303 and.w r3, r3, #3
|
|
8004c42: 2b00 cmp r3, #0
|
|
8004c44: d018 beq.n 8004c78 <RCCEx_PLLSAI2_Config+0x4c>
|
|
{
|
|
/* PLL clock source and divider M already set, check that no request for change */
|
|
if((__HAL_RCC_GET_PLL_OSCSOURCE() != PllSai2->PLLSAI2Source)
|
|
8004c46: 4b67 ldr r3, [pc, #412] @ (8004de4 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8004c48: 68db ldr r3, [r3, #12]
|
|
8004c4a: f003 0203 and.w r2, r3, #3
|
|
8004c4e: 687b ldr r3, [r7, #4]
|
|
8004c50: 681b ldr r3, [r3, #0]
|
|
8004c52: 429a cmp r2, r3
|
|
8004c54: d10d bne.n 8004c72 <RCCEx_PLLSAI2_Config+0x46>
|
|
||
|
|
(PllSai2->PLLSAI2Source == RCC_PLLSOURCE_NONE)
|
|
8004c56: 687b ldr r3, [r7, #4]
|
|
8004c58: 681b ldr r3, [r3, #0]
|
|
||
|
|
8004c5a: 2b00 cmp r3, #0
|
|
8004c5c: d009 beq.n 8004c72 <RCCEx_PLLSAI2_Config+0x46>
|
|
#if !defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
|
|
||
|
|
(((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U) != PllSai2->PLLSAI2M)
|
|
8004c5e: 4b61 ldr r3, [pc, #388] @ (8004de4 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8004c60: 68db ldr r3, [r3, #12]
|
|
8004c62: 091b lsrs r3, r3, #4
|
|
8004c64: f003 0307 and.w r3, r3, #7
|
|
8004c68: 1c5a adds r2, r3, #1
|
|
8004c6a: 687b ldr r3, [r7, #4]
|
|
8004c6c: 685b ldr r3, [r3, #4]
|
|
||
|
|
8004c6e: 429a cmp r2, r3
|
|
8004c70: d047 beq.n 8004d02 <RCCEx_PLLSAI2_Config+0xd6>
|
|
#endif
|
|
)
|
|
{
|
|
status = HAL_ERROR;
|
|
8004c72: 2301 movs r3, #1
|
|
8004c74: 73fb strb r3, [r7, #15]
|
|
8004c76: e044 b.n 8004d02 <RCCEx_PLLSAI2_Config+0xd6>
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/* Check PLLSAI2 clock source availability */
|
|
switch(PllSai2->PLLSAI2Source)
|
|
8004c78: 687b ldr r3, [r7, #4]
|
|
8004c7a: 681b ldr r3, [r3, #0]
|
|
8004c7c: 2b03 cmp r3, #3
|
|
8004c7e: d018 beq.n 8004cb2 <RCCEx_PLLSAI2_Config+0x86>
|
|
8004c80: 2b03 cmp r3, #3
|
|
8004c82: d825 bhi.n 8004cd0 <RCCEx_PLLSAI2_Config+0xa4>
|
|
8004c84: 2b01 cmp r3, #1
|
|
8004c86: d002 beq.n 8004c8e <RCCEx_PLLSAI2_Config+0x62>
|
|
8004c88: 2b02 cmp r3, #2
|
|
8004c8a: d009 beq.n 8004ca0 <RCCEx_PLLSAI2_Config+0x74>
|
|
8004c8c: e020 b.n 8004cd0 <RCCEx_PLLSAI2_Config+0xa4>
|
|
{
|
|
case RCC_PLLSOURCE_MSI:
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_MSIRDY))
|
|
8004c8e: 4b55 ldr r3, [pc, #340] @ (8004de4 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8004c90: 681b ldr r3, [r3, #0]
|
|
8004c92: f003 0302 and.w r3, r3, #2
|
|
8004c96: 2b00 cmp r3, #0
|
|
8004c98: d11d bne.n 8004cd6 <RCCEx_PLLSAI2_Config+0xaa>
|
|
{
|
|
status = HAL_ERROR;
|
|
8004c9a: 2301 movs r3, #1
|
|
8004c9c: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
8004c9e: e01a b.n 8004cd6 <RCCEx_PLLSAI2_Config+0xaa>
|
|
case RCC_PLLSOURCE_HSI:
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSIRDY))
|
|
8004ca0: 4b50 ldr r3, [pc, #320] @ (8004de4 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8004ca2: 681b ldr r3, [r3, #0]
|
|
8004ca4: f403 6380 and.w r3, r3, #1024 @ 0x400
|
|
8004ca8: 2b00 cmp r3, #0
|
|
8004caa: d116 bne.n 8004cda <RCCEx_PLLSAI2_Config+0xae>
|
|
{
|
|
status = HAL_ERROR;
|
|
8004cac: 2301 movs r3, #1
|
|
8004cae: 73fb strb r3, [r7, #15]
|
|
}
|
|
break;
|
|
8004cb0: e013 b.n 8004cda <RCCEx_PLLSAI2_Config+0xae>
|
|
case RCC_PLLSOURCE_HSE:
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSERDY))
|
|
8004cb2: 4b4c ldr r3, [pc, #304] @ (8004de4 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8004cb4: 681b ldr r3, [r3, #0]
|
|
8004cb6: f403 3300 and.w r3, r3, #131072 @ 0x20000
|
|
8004cba: 2b00 cmp r3, #0
|
|
8004cbc: d10f bne.n 8004cde <RCCEx_PLLSAI2_Config+0xb2>
|
|
{
|
|
if(HAL_IS_BIT_CLR(RCC->CR, RCC_CR_HSEBYP))
|
|
8004cbe: 4b49 ldr r3, [pc, #292] @ (8004de4 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8004cc0: 681b ldr r3, [r3, #0]
|
|
8004cc2: f403 2380 and.w r3, r3, #262144 @ 0x40000
|
|
8004cc6: 2b00 cmp r3, #0
|
|
8004cc8: d109 bne.n 8004cde <RCCEx_PLLSAI2_Config+0xb2>
|
|
{
|
|
status = HAL_ERROR;
|
|
8004cca: 2301 movs r3, #1
|
|
8004ccc: 73fb strb r3, [r7, #15]
|
|
}
|
|
}
|
|
break;
|
|
8004cce: e006 b.n 8004cde <RCCEx_PLLSAI2_Config+0xb2>
|
|
default:
|
|
status = HAL_ERROR;
|
|
8004cd0: 2301 movs r3, #1
|
|
8004cd2: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8004cd4: e004 b.n 8004ce0 <RCCEx_PLLSAI2_Config+0xb4>
|
|
break;
|
|
8004cd6: bf00 nop
|
|
8004cd8: e002 b.n 8004ce0 <RCCEx_PLLSAI2_Config+0xb4>
|
|
break;
|
|
8004cda: bf00 nop
|
|
8004cdc: e000 b.n 8004ce0 <RCCEx_PLLSAI2_Config+0xb4>
|
|
break;
|
|
8004cde: bf00 nop
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
8004ce0: 7bfb ldrb r3, [r7, #15]
|
|
8004ce2: 2b00 cmp r3, #0
|
|
8004ce4: d10d bne.n 8004d02 <RCCEx_PLLSAI2_Config+0xd6>
|
|
#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
|
|
/* Set PLLSAI2 clock source */
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PllSai2->PLLSAI2Source);
|
|
#else
|
|
/* Set PLLSAI2 clock source and divider M */
|
|
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, PllSai2->PLLSAI2Source | (PllSai2->PLLSAI2M - 1U) << RCC_PLLCFGR_PLLM_Pos);
|
|
8004ce6: 4b3f ldr r3, [pc, #252] @ (8004de4 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8004ce8: 68db ldr r3, [r3, #12]
|
|
8004cea: f023 0273 bic.w r2, r3, #115 @ 0x73
|
|
8004cee: 687b ldr r3, [r7, #4]
|
|
8004cf0: 6819 ldr r1, [r3, #0]
|
|
8004cf2: 687b ldr r3, [r7, #4]
|
|
8004cf4: 685b ldr r3, [r3, #4]
|
|
8004cf6: 3b01 subs r3, #1
|
|
8004cf8: 011b lsls r3, r3, #4
|
|
8004cfa: 430b orrs r3, r1
|
|
8004cfc: 4939 ldr r1, [pc, #228] @ (8004de4 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8004cfe: 4313 orrs r3, r2
|
|
8004d00: 60cb str r3, [r1, #12]
|
|
#endif
|
|
}
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
8004d02: 7bfb ldrb r3, [r7, #15]
|
|
8004d04: 2b00 cmp r3, #0
|
|
8004d06: d167 bne.n 8004dd8 <RCCEx_PLLSAI2_Config+0x1ac>
|
|
{
|
|
/* Disable the PLLSAI2 */
|
|
__HAL_RCC_PLLSAI2_DISABLE();
|
|
8004d08: 4b36 ldr r3, [pc, #216] @ (8004de4 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8004d0a: 681b ldr r3, [r3, #0]
|
|
8004d0c: 4a35 ldr r2, [pc, #212] @ (8004de4 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8004d0e: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
|
|
8004d12: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8004d14: f7fd fba2 bl 800245c <HAL_GetTick>
|
|
8004d18: 60b8 str r0, [r7, #8]
|
|
|
|
/* Wait till PLLSAI2 is ready to be updated */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
|
|
8004d1a: e009 b.n 8004d30 <RCCEx_PLLSAI2_Config+0x104>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
|
|
8004d1c: f7fd fb9e bl 800245c <HAL_GetTick>
|
|
8004d20: 4602 mov r2, r0
|
|
8004d22: 68bb ldr r3, [r7, #8]
|
|
8004d24: 1ad3 subs r3, r2, r3
|
|
8004d26: 2b02 cmp r3, #2
|
|
8004d28: d902 bls.n 8004d30 <RCCEx_PLLSAI2_Config+0x104>
|
|
{
|
|
status = HAL_TIMEOUT;
|
|
8004d2a: 2303 movs r3, #3
|
|
8004d2c: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8004d2e: e005 b.n 8004d3c <RCCEx_PLLSAI2_Config+0x110>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) != 0U)
|
|
8004d30: 4b2c ldr r3, [pc, #176] @ (8004de4 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8004d32: 681b ldr r3, [r3, #0]
|
|
8004d34: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
|
|
8004d38: 2b00 cmp r3, #0
|
|
8004d3a: d1ef bne.n 8004d1c <RCCEx_PLLSAI2_Config+0xf0>
|
|
}
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
8004d3c: 7bfb ldrb r3, [r7, #15]
|
|
8004d3e: 2b00 cmp r3, #0
|
|
8004d40: d14a bne.n 8004dd8 <RCCEx_PLLSAI2_Config+0x1ac>
|
|
{
|
|
if(Divider == DIVIDER_P_UPDATE)
|
|
8004d42: 683b ldr r3, [r7, #0]
|
|
8004d44: 2b00 cmp r3, #0
|
|
8004d46: d111 bne.n 8004d6c <RCCEx_PLLSAI2_Config+0x140>
|
|
MODIFY_REG(RCC->PLLSAI2CFGR,
|
|
RCC_PLLSAI2CFGR_PLLSAI2N | RCC_PLLSAI2CFGR_PLLSAI2PDIV,
|
|
(PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
|
|
(PllSai2->PLLSAI2P << RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos));
|
|
#else
|
|
MODIFY_REG(RCC->PLLSAI2CFGR,
|
|
8004d48: 4b26 ldr r3, [pc, #152] @ (8004de4 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8004d4a: 695b ldr r3, [r3, #20]
|
|
8004d4c: f423 331f bic.w r3, r3, #162816 @ 0x27c00
|
|
8004d50: f423 7340 bic.w r3, r3, #768 @ 0x300
|
|
8004d54: 687a ldr r2, [r7, #4]
|
|
8004d56: 6892 ldr r2, [r2, #8]
|
|
8004d58: 0211 lsls r1, r2, #8
|
|
8004d5a: 687a ldr r2, [r7, #4]
|
|
8004d5c: 68d2 ldr r2, [r2, #12]
|
|
8004d5e: 0912 lsrs r2, r2, #4
|
|
8004d60: 0452 lsls r2, r2, #17
|
|
8004d62: 430a orrs r2, r1
|
|
8004d64: 491f ldr r1, [pc, #124] @ (8004de4 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8004d66: 4313 orrs r3, r2
|
|
8004d68: 614b str r3, [r1, #20]
|
|
8004d6a: e011 b.n 8004d90 <RCCEx_PLLSAI2_Config+0x164>
|
|
(PllSai2->PLLSAI2N << RCC_PLLSAI2CFGR_PLLSAI2N_Pos) |
|
|
(((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos) |
|
|
((PllSai2->PLLSAI2M - 1U) << RCC_PLLSAI2CFGR_PLLSAI2M_Pos));
|
|
#else
|
|
/* Configure the PLLSAI2 Division factor R and Multiplication factor N*/
|
|
MODIFY_REG(RCC->PLLSAI2CFGR,
|
|
8004d6c: 4b1d ldr r3, [pc, #116] @ (8004de4 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8004d6e: 695b ldr r3, [r3, #20]
|
|
8004d70: f023 63c0 bic.w r3, r3, #100663296 @ 0x6000000
|
|
8004d74: f423 43fe bic.w r3, r3, #32512 @ 0x7f00
|
|
8004d78: 687a ldr r2, [r7, #4]
|
|
8004d7a: 6892 ldr r2, [r2, #8]
|
|
8004d7c: 0211 lsls r1, r2, #8
|
|
8004d7e: 687a ldr r2, [r7, #4]
|
|
8004d80: 6912 ldr r2, [r2, #16]
|
|
8004d82: 0852 lsrs r2, r2, #1
|
|
8004d84: 3a01 subs r2, #1
|
|
8004d86: 0652 lsls r2, r2, #25
|
|
8004d88: 430a orrs r2, r1
|
|
8004d8a: 4916 ldr r1, [pc, #88] @ (8004de4 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8004d8c: 4313 orrs r3, r2
|
|
8004d8e: 614b str r3, [r1, #20]
|
|
(((PllSai2->PLLSAI2R >> 1U) - 1U) << RCC_PLLSAI2CFGR_PLLSAI2R_Pos));
|
|
#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
|
|
}
|
|
|
|
/* Enable the PLLSAI2 again by setting PLLSAI2ON to 1*/
|
|
__HAL_RCC_PLLSAI2_ENABLE();
|
|
8004d90: 4b14 ldr r3, [pc, #80] @ (8004de4 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8004d92: 681b ldr r3, [r3, #0]
|
|
8004d94: 4a13 ldr r2, [pc, #76] @ (8004de4 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8004d96: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
|
|
8004d9a: 6013 str r3, [r2, #0]
|
|
|
|
/* Get Start Tick*/
|
|
tickstart = HAL_GetTick();
|
|
8004d9c: f7fd fb5e bl 800245c <HAL_GetTick>
|
|
8004da0: 60b8 str r0, [r7, #8]
|
|
|
|
/* Wait till PLLSAI2 is ready */
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
|
|
8004da2: e009 b.n 8004db8 <RCCEx_PLLSAI2_Config+0x18c>
|
|
{
|
|
if((HAL_GetTick() - tickstart) > PLLSAI2_TIMEOUT_VALUE)
|
|
8004da4: f7fd fb5a bl 800245c <HAL_GetTick>
|
|
8004da8: 4602 mov r2, r0
|
|
8004daa: 68bb ldr r3, [r7, #8]
|
|
8004dac: 1ad3 subs r3, r2, r3
|
|
8004dae: 2b02 cmp r3, #2
|
|
8004db0: d902 bls.n 8004db8 <RCCEx_PLLSAI2_Config+0x18c>
|
|
{
|
|
status = HAL_TIMEOUT;
|
|
8004db2: 2303 movs r3, #3
|
|
8004db4: 73fb strb r3, [r7, #15]
|
|
break;
|
|
8004db6: e005 b.n 8004dc4 <RCCEx_PLLSAI2_Config+0x198>
|
|
while(READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == 0U)
|
|
8004db8: 4b0a ldr r3, [pc, #40] @ (8004de4 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8004dba: 681b ldr r3, [r3, #0]
|
|
8004dbc: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
|
|
8004dc0: 2b00 cmp r3, #0
|
|
8004dc2: d0ef beq.n 8004da4 <RCCEx_PLLSAI2_Config+0x178>
|
|
}
|
|
}
|
|
|
|
if(status == HAL_OK)
|
|
8004dc4: 7bfb ldrb r3, [r7, #15]
|
|
8004dc6: 2b00 cmp r3, #0
|
|
8004dc8: d106 bne.n 8004dd8 <RCCEx_PLLSAI2_Config+0x1ac>
|
|
{
|
|
/* Configure the PLLSAI2 Clock output(s) */
|
|
__HAL_RCC_PLLSAI2CLKOUT_ENABLE(PllSai2->PLLSAI2ClockOut);
|
|
8004dca: 4b06 ldr r3, [pc, #24] @ (8004de4 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8004dcc: 695a ldr r2, [r3, #20]
|
|
8004dce: 687b ldr r3, [r7, #4]
|
|
8004dd0: 695b ldr r3, [r3, #20]
|
|
8004dd2: 4904 ldr r1, [pc, #16] @ (8004de4 <RCCEx_PLLSAI2_Config+0x1b8>)
|
|
8004dd4: 4313 orrs r3, r2
|
|
8004dd6: 614b str r3, [r1, #20]
|
|
}
|
|
}
|
|
}
|
|
|
|
return status;
|
|
8004dd8: 7bfb ldrb r3, [r7, #15]
|
|
}
|
|
8004dda: 4618 mov r0, r3
|
|
8004ddc: 3710 adds r7, #16
|
|
8004dde: 46bd mov sp, r7
|
|
8004de0: bd80 pop {r7, pc}
|
|
8004de2: bf00 nop
|
|
8004de4: 40021000 .word 0x40021000
|
|
|
|
08004de8 <HAL_UART_Init>:
|
|
* parameters in the UART_InitTypeDef and initialize the associated handle.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
|
{
|
|
8004de8: b580 push {r7, lr}
|
|
8004dea: b082 sub sp, #8
|
|
8004dec: af00 add r7, sp, #0
|
|
8004dee: 6078 str r0, [r7, #4]
|
|
/* Check the UART handle allocation */
|
|
if (huart == NULL)
|
|
8004df0: 687b ldr r3, [r7, #4]
|
|
8004df2: 2b00 cmp r3, #0
|
|
8004df4: d101 bne.n 8004dfa <HAL_UART_Init+0x12>
|
|
{
|
|
return HAL_ERROR;
|
|
8004df6: 2301 movs r3, #1
|
|
8004df8: e040 b.n 8004e7c <HAL_UART_Init+0x94>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
|
|
}
|
|
|
|
if (huart->gState == HAL_UART_STATE_RESET)
|
|
8004dfa: 687b ldr r3, [r7, #4]
|
|
8004dfc: 6fdb ldr r3, [r3, #124] @ 0x7c
|
|
8004dfe: 2b00 cmp r3, #0
|
|
8004e00: d106 bne.n 8004e10 <HAL_UART_Init+0x28>
|
|
{
|
|
/* Allocate lock resource and initialize it */
|
|
huart->Lock = HAL_UNLOCKED;
|
|
8004e02: 687b ldr r3, [r7, #4]
|
|
8004e04: 2200 movs r2, #0
|
|
8004e06: f883 2078 strb.w r2, [r3, #120] @ 0x78
|
|
|
|
/* Init the low level hardware */
|
|
huart->MspInitCallback(huart);
|
|
#else
|
|
/* Init the low level hardware : GPIO, CLOCK */
|
|
HAL_UART_MspInit(huart);
|
|
8004e0a: 6878 ldr r0, [r7, #4]
|
|
8004e0c: f7fd f91c bl 8002048 <HAL_UART_MspInit>
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
8004e10: 687b ldr r3, [r7, #4]
|
|
8004e12: 2224 movs r2, #36 @ 0x24
|
|
8004e14: 67da str r2, [r3, #124] @ 0x7c
|
|
|
|
__HAL_UART_DISABLE(huart);
|
|
8004e16: 687b ldr r3, [r7, #4]
|
|
8004e18: 681b ldr r3, [r3, #0]
|
|
8004e1a: 681a ldr r2, [r3, #0]
|
|
8004e1c: 687b ldr r3, [r7, #4]
|
|
8004e1e: 681b ldr r3, [r3, #0]
|
|
8004e20: f022 0201 bic.w r2, r2, #1
|
|
8004e24: 601a str r2, [r3, #0]
|
|
|
|
/* Perform advanced settings configuration */
|
|
/* For some items, configuration requires to be done prior TE and RE bits are set */
|
|
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
|
8004e26: 687b ldr r3, [r7, #4]
|
|
8004e28: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8004e2a: 2b00 cmp r3, #0
|
|
8004e2c: d002 beq.n 8004e34 <HAL_UART_Init+0x4c>
|
|
{
|
|
UART_AdvFeatureConfig(huart);
|
|
8004e2e: 6878 ldr r0, [r7, #4]
|
|
8004e30: f000 fedc bl 8005bec <UART_AdvFeatureConfig>
|
|
}
|
|
|
|
/* Set the UART Communication parameters */
|
|
if (UART_SetConfig(huart) == HAL_ERROR)
|
|
8004e34: 6878 ldr r0, [r7, #4]
|
|
8004e36: f000 fc21 bl 800567c <UART_SetConfig>
|
|
8004e3a: 4603 mov r3, r0
|
|
8004e3c: 2b01 cmp r3, #1
|
|
8004e3e: d101 bne.n 8004e44 <HAL_UART_Init+0x5c>
|
|
{
|
|
return HAL_ERROR;
|
|
8004e40: 2301 movs r3, #1
|
|
8004e42: e01b b.n 8004e7c <HAL_UART_Init+0x94>
|
|
}
|
|
|
|
/* In asynchronous mode, the following bits must be kept cleared:
|
|
- LINEN and CLKEN bits in the USART_CR2 register,
|
|
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
|
|
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
|
8004e44: 687b ldr r3, [r7, #4]
|
|
8004e46: 681b ldr r3, [r3, #0]
|
|
8004e48: 685a ldr r2, [r3, #4]
|
|
8004e4a: 687b ldr r3, [r7, #4]
|
|
8004e4c: 681b ldr r3, [r3, #0]
|
|
8004e4e: f422 4290 bic.w r2, r2, #18432 @ 0x4800
|
|
8004e52: 605a str r2, [r3, #4]
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
|
|
8004e54: 687b ldr r3, [r7, #4]
|
|
8004e56: 681b ldr r3, [r3, #0]
|
|
8004e58: 689a ldr r2, [r3, #8]
|
|
8004e5a: 687b ldr r3, [r7, #4]
|
|
8004e5c: 681b ldr r3, [r3, #0]
|
|
8004e5e: f022 022a bic.w r2, r2, #42 @ 0x2a
|
|
8004e62: 609a str r2, [r3, #8]
|
|
|
|
__HAL_UART_ENABLE(huart);
|
|
8004e64: 687b ldr r3, [r7, #4]
|
|
8004e66: 681b ldr r3, [r3, #0]
|
|
8004e68: 681a ldr r2, [r3, #0]
|
|
8004e6a: 687b ldr r3, [r7, #4]
|
|
8004e6c: 681b ldr r3, [r3, #0]
|
|
8004e6e: f042 0201 orr.w r2, r2, #1
|
|
8004e72: 601a str r2, [r3, #0]
|
|
|
|
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
|
|
return (UART_CheckIdleState(huart));
|
|
8004e74: 6878 ldr r0, [r7, #4]
|
|
8004e76: f000 ff5b bl 8005d30 <UART_CheckIdleState>
|
|
8004e7a: 4603 mov r3, r0
|
|
}
|
|
8004e7c: 4618 mov r0, r3
|
|
8004e7e: 3708 adds r7, #8
|
|
8004e80: 46bd mov sp, r7
|
|
8004e82: bd80 pop {r7, pc}
|
|
|
|
08004e84 <HAL_UART_Transmit>:
|
|
* @param Size Amount of data elements (u8 or u16) to be sent.
|
|
* @param Timeout Timeout duration.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
|
|
{
|
|
8004e84: b580 push {r7, lr}
|
|
8004e86: b08a sub sp, #40 @ 0x28
|
|
8004e88: af02 add r7, sp, #8
|
|
8004e8a: 60f8 str r0, [r7, #12]
|
|
8004e8c: 60b9 str r1, [r7, #8]
|
|
8004e8e: 603b str r3, [r7, #0]
|
|
8004e90: 4613 mov r3, r2
|
|
8004e92: 80fb strh r3, [r7, #6]
|
|
const uint8_t *pdata8bits;
|
|
const uint16_t *pdata16bits;
|
|
uint32_t tickstart;
|
|
|
|
/* Check that a Tx process is not already ongoing */
|
|
if (huart->gState == HAL_UART_STATE_READY)
|
|
8004e94: 68fb ldr r3, [r7, #12]
|
|
8004e96: 6fdb ldr r3, [r3, #124] @ 0x7c
|
|
8004e98: 2b20 cmp r3, #32
|
|
8004e9a: d177 bne.n 8004f8c <HAL_UART_Transmit+0x108>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8004e9c: 68bb ldr r3, [r7, #8]
|
|
8004e9e: 2b00 cmp r3, #0
|
|
8004ea0: d002 beq.n 8004ea8 <HAL_UART_Transmit+0x24>
|
|
8004ea2: 88fb ldrh r3, [r7, #6]
|
|
8004ea4: 2b00 cmp r3, #0
|
|
8004ea6: d101 bne.n 8004eac <HAL_UART_Transmit+0x28>
|
|
{
|
|
return HAL_ERROR;
|
|
8004ea8: 2301 movs r3, #1
|
|
8004eaa: e070 b.n 8004f8e <HAL_UART_Transmit+0x10a>
|
|
}
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8004eac: 68fb ldr r3, [r7, #12]
|
|
8004eae: 2200 movs r2, #0
|
|
8004eb0: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
huart->gState = HAL_UART_STATE_BUSY_TX;
|
|
8004eb4: 68fb ldr r3, [r7, #12]
|
|
8004eb6: 2221 movs r2, #33 @ 0x21
|
|
8004eb8: 67da str r2, [r3, #124] @ 0x7c
|
|
|
|
/* Init tickstart for timeout management */
|
|
tickstart = HAL_GetTick();
|
|
8004eba: f7fd facf bl 800245c <HAL_GetTick>
|
|
8004ebe: 6178 str r0, [r7, #20]
|
|
|
|
huart->TxXferSize = Size;
|
|
8004ec0: 68fb ldr r3, [r7, #12]
|
|
8004ec2: 88fa ldrh r2, [r7, #6]
|
|
8004ec4: f8a3 2050 strh.w r2, [r3, #80] @ 0x50
|
|
huart->TxXferCount = Size;
|
|
8004ec8: 68fb ldr r3, [r7, #12]
|
|
8004eca: 88fa ldrh r2, [r7, #6]
|
|
8004ecc: f8a3 2052 strh.w r2, [r3, #82] @ 0x52
|
|
|
|
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
8004ed0: 68fb ldr r3, [r7, #12]
|
|
8004ed2: 689b ldr r3, [r3, #8]
|
|
8004ed4: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
8004ed8: d108 bne.n 8004eec <HAL_UART_Transmit+0x68>
|
|
8004eda: 68fb ldr r3, [r7, #12]
|
|
8004edc: 691b ldr r3, [r3, #16]
|
|
8004ede: 2b00 cmp r3, #0
|
|
8004ee0: d104 bne.n 8004eec <HAL_UART_Transmit+0x68>
|
|
{
|
|
pdata8bits = NULL;
|
|
8004ee2: 2300 movs r3, #0
|
|
8004ee4: 61fb str r3, [r7, #28]
|
|
pdata16bits = (const uint16_t *) pData;
|
|
8004ee6: 68bb ldr r3, [r7, #8]
|
|
8004ee8: 61bb str r3, [r7, #24]
|
|
8004eea: e003 b.n 8004ef4 <HAL_UART_Transmit+0x70>
|
|
}
|
|
else
|
|
{
|
|
pdata8bits = pData;
|
|
8004eec: 68bb ldr r3, [r7, #8]
|
|
8004eee: 61fb str r3, [r7, #28]
|
|
pdata16bits = NULL;
|
|
8004ef0: 2300 movs r3, #0
|
|
8004ef2: 61bb str r3, [r7, #24]
|
|
}
|
|
|
|
while (huart->TxXferCount > 0U)
|
|
8004ef4: e02f b.n 8004f56 <HAL_UART_Transmit+0xd2>
|
|
{
|
|
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
|
|
8004ef6: 683b ldr r3, [r7, #0]
|
|
8004ef8: 9300 str r3, [sp, #0]
|
|
8004efa: 697b ldr r3, [r7, #20]
|
|
8004efc: 2200 movs r2, #0
|
|
8004efe: 2180 movs r1, #128 @ 0x80
|
|
8004f00: 68f8 ldr r0, [r7, #12]
|
|
8004f02: f000 ffbd bl 8005e80 <UART_WaitOnFlagUntilTimeout>
|
|
8004f06: 4603 mov r3, r0
|
|
8004f08: 2b00 cmp r3, #0
|
|
8004f0a: d004 beq.n 8004f16 <HAL_UART_Transmit+0x92>
|
|
{
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8004f0c: 68fb ldr r3, [r7, #12]
|
|
8004f0e: 2220 movs r2, #32
|
|
8004f10: 67da str r2, [r3, #124] @ 0x7c
|
|
|
|
return HAL_TIMEOUT;
|
|
8004f12: 2303 movs r3, #3
|
|
8004f14: e03b b.n 8004f8e <HAL_UART_Transmit+0x10a>
|
|
}
|
|
if (pdata8bits == NULL)
|
|
8004f16: 69fb ldr r3, [r7, #28]
|
|
8004f18: 2b00 cmp r3, #0
|
|
8004f1a: d10b bne.n 8004f34 <HAL_UART_Transmit+0xb0>
|
|
{
|
|
huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
|
|
8004f1c: 69bb ldr r3, [r7, #24]
|
|
8004f1e: 881a ldrh r2, [r3, #0]
|
|
8004f20: 68fb ldr r3, [r7, #12]
|
|
8004f22: 681b ldr r3, [r3, #0]
|
|
8004f24: f3c2 0208 ubfx r2, r2, #0, #9
|
|
8004f28: b292 uxth r2, r2
|
|
8004f2a: 851a strh r2, [r3, #40] @ 0x28
|
|
pdata16bits++;
|
|
8004f2c: 69bb ldr r3, [r7, #24]
|
|
8004f2e: 3302 adds r3, #2
|
|
8004f30: 61bb str r3, [r7, #24]
|
|
8004f32: e007 b.n 8004f44 <HAL_UART_Transmit+0xc0>
|
|
}
|
|
else
|
|
{
|
|
huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
|
|
8004f34: 69fb ldr r3, [r7, #28]
|
|
8004f36: 781a ldrb r2, [r3, #0]
|
|
8004f38: 68fb ldr r3, [r7, #12]
|
|
8004f3a: 681b ldr r3, [r3, #0]
|
|
8004f3c: 851a strh r2, [r3, #40] @ 0x28
|
|
pdata8bits++;
|
|
8004f3e: 69fb ldr r3, [r7, #28]
|
|
8004f40: 3301 adds r3, #1
|
|
8004f42: 61fb str r3, [r7, #28]
|
|
}
|
|
huart->TxXferCount--;
|
|
8004f44: 68fb ldr r3, [r7, #12]
|
|
8004f46: f8b3 3052 ldrh.w r3, [r3, #82] @ 0x52
|
|
8004f4a: b29b uxth r3, r3
|
|
8004f4c: 3b01 subs r3, #1
|
|
8004f4e: b29a uxth r2, r3
|
|
8004f50: 68fb ldr r3, [r7, #12]
|
|
8004f52: f8a3 2052 strh.w r2, [r3, #82] @ 0x52
|
|
while (huart->TxXferCount > 0U)
|
|
8004f56: 68fb ldr r3, [r7, #12]
|
|
8004f58: f8b3 3052 ldrh.w r3, [r3, #82] @ 0x52
|
|
8004f5c: b29b uxth r3, r3
|
|
8004f5e: 2b00 cmp r3, #0
|
|
8004f60: d1c9 bne.n 8004ef6 <HAL_UART_Transmit+0x72>
|
|
}
|
|
|
|
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
|
|
8004f62: 683b ldr r3, [r7, #0]
|
|
8004f64: 9300 str r3, [sp, #0]
|
|
8004f66: 697b ldr r3, [r7, #20]
|
|
8004f68: 2200 movs r2, #0
|
|
8004f6a: 2140 movs r1, #64 @ 0x40
|
|
8004f6c: 68f8 ldr r0, [r7, #12]
|
|
8004f6e: f000 ff87 bl 8005e80 <UART_WaitOnFlagUntilTimeout>
|
|
8004f72: 4603 mov r3, r0
|
|
8004f74: 2b00 cmp r3, #0
|
|
8004f76: d004 beq.n 8004f82 <HAL_UART_Transmit+0xfe>
|
|
{
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8004f78: 68fb ldr r3, [r7, #12]
|
|
8004f7a: 2220 movs r2, #32
|
|
8004f7c: 67da str r2, [r3, #124] @ 0x7c
|
|
|
|
return HAL_TIMEOUT;
|
|
8004f7e: 2303 movs r3, #3
|
|
8004f80: e005 b.n 8004f8e <HAL_UART_Transmit+0x10a>
|
|
}
|
|
|
|
/* At end of Tx process, restore huart->gState to Ready */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8004f82: 68fb ldr r3, [r7, #12]
|
|
8004f84: 2220 movs r2, #32
|
|
8004f86: 67da str r2, [r3, #124] @ 0x7c
|
|
|
|
return HAL_OK;
|
|
8004f88: 2300 movs r3, #0
|
|
8004f8a: e000 b.n 8004f8e <HAL_UART_Transmit+0x10a>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8004f8c: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8004f8e: 4618 mov r0, r3
|
|
8004f90: 3720 adds r7, #32
|
|
8004f92: 46bd mov sp, r7
|
|
8004f94: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08004f98 <HAL_UART_Receive_IT>:
|
|
* @param pData Pointer to data buffer (u8 or u16 data elements).
|
|
* @param Size Amount of data elements (u8 or u16) to be received.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
|
|
{
|
|
8004f98: b580 push {r7, lr}
|
|
8004f9a: b08a sub sp, #40 @ 0x28
|
|
8004f9c: af00 add r7, sp, #0
|
|
8004f9e: 60f8 str r0, [r7, #12]
|
|
8004fa0: 60b9 str r1, [r7, #8]
|
|
8004fa2: 4613 mov r3, r2
|
|
8004fa4: 80fb strh r3, [r7, #6]
|
|
/* Check that a Rx process is not already ongoing */
|
|
if (huart->RxState == HAL_UART_STATE_READY)
|
|
8004fa6: 68fb ldr r3, [r7, #12]
|
|
8004fa8: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
8004fac: 2b20 cmp r3, #32
|
|
8004fae: d137 bne.n 8005020 <HAL_UART_Receive_IT+0x88>
|
|
{
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8004fb0: 68bb ldr r3, [r7, #8]
|
|
8004fb2: 2b00 cmp r3, #0
|
|
8004fb4: d002 beq.n 8004fbc <HAL_UART_Receive_IT+0x24>
|
|
8004fb6: 88fb ldrh r3, [r7, #6]
|
|
8004fb8: 2b00 cmp r3, #0
|
|
8004fba: d101 bne.n 8004fc0 <HAL_UART_Receive_IT+0x28>
|
|
{
|
|
return HAL_ERROR;
|
|
8004fbc: 2301 movs r3, #1
|
|
8004fbe: e030 b.n 8005022 <HAL_UART_Receive_IT+0x8a>
|
|
}
|
|
|
|
/* Set Reception type to Standard reception */
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8004fc0: 68fb ldr r3, [r7, #12]
|
|
8004fc2: 2200 movs r2, #0
|
|
8004fc4: 661a str r2, [r3, #96] @ 0x60
|
|
|
|
if (!(IS_LPUART_INSTANCE(huart->Instance)))
|
|
8004fc6: 68fb ldr r3, [r7, #12]
|
|
8004fc8: 681b ldr r3, [r3, #0]
|
|
8004fca: 4a18 ldr r2, [pc, #96] @ (800502c <HAL_UART_Receive_IT+0x94>)
|
|
8004fcc: 4293 cmp r3, r2
|
|
8004fce: d01f beq.n 8005010 <HAL_UART_Receive_IT+0x78>
|
|
{
|
|
/* Check that USART RTOEN bit is set */
|
|
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
|
|
8004fd0: 68fb ldr r3, [r7, #12]
|
|
8004fd2: 681b ldr r3, [r3, #0]
|
|
8004fd4: 685b ldr r3, [r3, #4]
|
|
8004fd6: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
8004fda: 2b00 cmp r3, #0
|
|
8004fdc: d018 beq.n 8005010 <HAL_UART_Receive_IT+0x78>
|
|
{
|
|
/* Enable the UART Receiver Timeout Interrupt */
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
|
|
8004fde: 68fb ldr r3, [r7, #12]
|
|
8004fe0: 681b ldr r3, [r3, #0]
|
|
8004fe2: 617b str r3, [r7, #20]
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8004fe4: 697b ldr r3, [r7, #20]
|
|
8004fe6: e853 3f00 ldrex r3, [r3]
|
|
8004fea: 613b str r3, [r7, #16]
|
|
return(result);
|
|
8004fec: 693b ldr r3, [r7, #16]
|
|
8004fee: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
|
|
8004ff2: 627b str r3, [r7, #36] @ 0x24
|
|
8004ff4: 68fb ldr r3, [r7, #12]
|
|
8004ff6: 681b ldr r3, [r3, #0]
|
|
8004ff8: 461a mov r2, r3
|
|
8004ffa: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8004ffc: 623b str r3, [r7, #32]
|
|
8004ffe: 61fa str r2, [r7, #28]
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005000: 69f9 ldr r1, [r7, #28]
|
|
8005002: 6a3a ldr r2, [r7, #32]
|
|
8005004: e841 2300 strex r3, r2, [r1]
|
|
8005008: 61bb str r3, [r7, #24]
|
|
return(result);
|
|
800500a: 69bb ldr r3, [r7, #24]
|
|
800500c: 2b00 cmp r3, #0
|
|
800500e: d1e6 bne.n 8004fde <HAL_UART_Receive_IT+0x46>
|
|
}
|
|
}
|
|
|
|
return (UART_Start_Receive_IT(huart, pData, Size));
|
|
8005010: 88fb ldrh r3, [r7, #6]
|
|
8005012: 461a mov r2, r3
|
|
8005014: 68b9 ldr r1, [r7, #8]
|
|
8005016: 68f8 ldr r0, [r7, #12]
|
|
8005018: f000 ffa0 bl 8005f5c <UART_Start_Receive_IT>
|
|
800501c: 4603 mov r3, r0
|
|
800501e: e000 b.n 8005022 <HAL_UART_Receive_IT+0x8a>
|
|
}
|
|
else
|
|
{
|
|
return HAL_BUSY;
|
|
8005020: 2302 movs r3, #2
|
|
}
|
|
}
|
|
8005022: 4618 mov r0, r3
|
|
8005024: 3728 adds r7, #40 @ 0x28
|
|
8005026: 46bd mov sp, r7
|
|
8005028: bd80 pop {r7, pc}
|
|
800502a: bf00 nop
|
|
800502c: 40008000 .word 0x40008000
|
|
|
|
08005030 <HAL_UART_IRQHandler>:
|
|
* @brief Handle UART interrupt request.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
|
|
{
|
|
8005030: b580 push {r7, lr}
|
|
8005032: b0ba sub sp, #232 @ 0xe8
|
|
8005034: af00 add r7, sp, #0
|
|
8005036: 6078 str r0, [r7, #4]
|
|
uint32_t isrflags = READ_REG(huart->Instance->ISR);
|
|
8005038: 687b ldr r3, [r7, #4]
|
|
800503a: 681b ldr r3, [r3, #0]
|
|
800503c: 69db ldr r3, [r3, #28]
|
|
800503e: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
|
|
uint32_t cr1its = READ_REG(huart->Instance->CR1);
|
|
8005042: 687b ldr r3, [r7, #4]
|
|
8005044: 681b ldr r3, [r3, #0]
|
|
8005046: 681b ldr r3, [r3, #0]
|
|
8005048: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
|
|
uint32_t cr3its = READ_REG(huart->Instance->CR3);
|
|
800504c: 687b ldr r3, [r7, #4]
|
|
800504e: 681b ldr r3, [r3, #0]
|
|
8005050: 689b ldr r3, [r3, #8]
|
|
8005052: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
|
|
|
|
uint32_t errorflags;
|
|
uint32_t errorcode;
|
|
|
|
/* If no error occurs */
|
|
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
|
|
8005056: f8d7 20e4 ldr.w r2, [r7, #228] @ 0xe4
|
|
800505a: f640 030f movw r3, #2063 @ 0x80f
|
|
800505e: 4013 ands r3, r2
|
|
8005060: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
|
|
if (errorflags == 0U)
|
|
8005064: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
|
|
8005068: 2b00 cmp r3, #0
|
|
800506a: d115 bne.n 8005098 <HAL_UART_IRQHandler+0x68>
|
|
#if defined(USART_CR1_FIFOEN)
|
|
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
|
|
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
|
|
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
|
|
#else
|
|
if (((isrflags & USART_ISR_RXNE) != 0U)
|
|
800506c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8005070: f003 0320 and.w r3, r3, #32
|
|
8005074: 2b00 cmp r3, #0
|
|
8005076: d00f beq.n 8005098 <HAL_UART_IRQHandler+0x68>
|
|
&& ((cr1its & USART_CR1_RXNEIE) != 0U))
|
|
8005078: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
800507c: f003 0320 and.w r3, r3, #32
|
|
8005080: 2b00 cmp r3, #0
|
|
8005082: d009 beq.n 8005098 <HAL_UART_IRQHandler+0x68>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
{
|
|
if (huart->RxISR != NULL)
|
|
8005084: 687b ldr r3, [r7, #4]
|
|
8005086: 6e9b ldr r3, [r3, #104] @ 0x68
|
|
8005088: 2b00 cmp r3, #0
|
|
800508a: f000 82ca beq.w 8005622 <HAL_UART_IRQHandler+0x5f2>
|
|
{
|
|
huart->RxISR(huart);
|
|
800508e: 687b ldr r3, [r7, #4]
|
|
8005090: 6e9b ldr r3, [r3, #104] @ 0x68
|
|
8005092: 6878 ldr r0, [r7, #4]
|
|
8005094: 4798 blx r3
|
|
}
|
|
return;
|
|
8005096: e2c4 b.n 8005622 <HAL_UART_IRQHandler+0x5f2>
|
|
#if defined(USART_CR1_FIFOEN)
|
|
if ((errorflags != 0U)
|
|
&& ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
|
|
|| ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
|
|
#else
|
|
if ((errorflags != 0U)
|
|
8005098: f8d7 30d8 ldr.w r3, [r7, #216] @ 0xd8
|
|
800509c: 2b00 cmp r3, #0
|
|
800509e: f000 8117 beq.w 80052d0 <HAL_UART_IRQHandler+0x2a0>
|
|
&& (((cr3its & USART_CR3_EIE) != 0U)
|
|
80050a2: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
80050a6: f003 0301 and.w r3, r3, #1
|
|
80050aa: 2b00 cmp r3, #0
|
|
80050ac: d106 bne.n 80050bc <HAL_UART_IRQHandler+0x8c>
|
|
|| ((cr1its & (USART_CR1_RXNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))
|
|
80050ae: f8d7 20e0 ldr.w r2, [r7, #224] @ 0xe0
|
|
80050b2: 4b85 ldr r3, [pc, #532] @ (80052c8 <HAL_UART_IRQHandler+0x298>)
|
|
80050b4: 4013 ands r3, r2
|
|
80050b6: 2b00 cmp r3, #0
|
|
80050b8: f000 810a beq.w 80052d0 <HAL_UART_IRQHandler+0x2a0>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
{
|
|
/* UART parity error interrupt occurred -------------------------------------*/
|
|
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
|
|
80050bc: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
80050c0: f003 0301 and.w r3, r3, #1
|
|
80050c4: 2b00 cmp r3, #0
|
|
80050c6: d011 beq.n 80050ec <HAL_UART_IRQHandler+0xbc>
|
|
80050c8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
80050cc: f403 7380 and.w r3, r3, #256 @ 0x100
|
|
80050d0: 2b00 cmp r3, #0
|
|
80050d2: d00b beq.n 80050ec <HAL_UART_IRQHandler+0xbc>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
|
|
80050d4: 687b ldr r3, [r7, #4]
|
|
80050d6: 681b ldr r3, [r3, #0]
|
|
80050d8: 2201 movs r2, #1
|
|
80050da: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_PE;
|
|
80050dc: 687b ldr r3, [r7, #4]
|
|
80050de: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
80050e2: f043 0201 orr.w r2, r3, #1
|
|
80050e6: 687b ldr r3, [r7, #4]
|
|
80050e8: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
}
|
|
|
|
/* UART frame error interrupt occurred --------------------------------------*/
|
|
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
|
80050ec: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
80050f0: f003 0302 and.w r3, r3, #2
|
|
80050f4: 2b00 cmp r3, #0
|
|
80050f6: d011 beq.n 800511c <HAL_UART_IRQHandler+0xec>
|
|
80050f8: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
80050fc: f003 0301 and.w r3, r3, #1
|
|
8005100: 2b00 cmp r3, #0
|
|
8005102: d00b beq.n 800511c <HAL_UART_IRQHandler+0xec>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
|
|
8005104: 687b ldr r3, [r7, #4]
|
|
8005106: 681b ldr r3, [r3, #0]
|
|
8005108: 2202 movs r2, #2
|
|
800510a: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_FE;
|
|
800510c: 687b ldr r3, [r7, #4]
|
|
800510e: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8005112: f043 0204 orr.w r2, r3, #4
|
|
8005116: 687b ldr r3, [r7, #4]
|
|
8005118: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
}
|
|
|
|
/* UART noise error interrupt occurred --------------------------------------*/
|
|
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
|
800511c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8005120: f003 0304 and.w r3, r3, #4
|
|
8005124: 2b00 cmp r3, #0
|
|
8005126: d011 beq.n 800514c <HAL_UART_IRQHandler+0x11c>
|
|
8005128: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
800512c: f003 0301 and.w r3, r3, #1
|
|
8005130: 2b00 cmp r3, #0
|
|
8005132: d00b beq.n 800514c <HAL_UART_IRQHandler+0x11c>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
|
|
8005134: 687b ldr r3, [r7, #4]
|
|
8005136: 681b ldr r3, [r3, #0]
|
|
8005138: 2204 movs r2, #4
|
|
800513a: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_NE;
|
|
800513c: 687b ldr r3, [r7, #4]
|
|
800513e: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
8005142: f043 0202 orr.w r2, r3, #2
|
|
8005146: 687b ldr r3, [r7, #4]
|
|
8005148: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
#if defined(USART_CR1_FIFOEN)
|
|
if (((isrflags & USART_ISR_ORE) != 0U)
|
|
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
|
|
((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
|
|
#else
|
|
if (((isrflags & USART_ISR_ORE) != 0U)
|
|
800514c: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8005150: f003 0308 and.w r3, r3, #8
|
|
8005154: 2b00 cmp r3, #0
|
|
8005156: d017 beq.n 8005188 <HAL_UART_IRQHandler+0x158>
|
|
&& (((cr1its & USART_CR1_RXNEIE) != 0U) ||
|
|
8005158: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
800515c: f003 0320 and.w r3, r3, #32
|
|
8005160: 2b00 cmp r3, #0
|
|
8005162: d105 bne.n 8005170 <HAL_UART_IRQHandler+0x140>
|
|
((cr3its & USART_CR3_EIE) != 0U)))
|
|
8005164: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
8005168: f003 0301 and.w r3, r3, #1
|
|
&& (((cr1its & USART_CR1_RXNEIE) != 0U) ||
|
|
800516c: 2b00 cmp r3, #0
|
|
800516e: d00b beq.n 8005188 <HAL_UART_IRQHandler+0x158>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
|
|
8005170: 687b ldr r3, [r7, #4]
|
|
8005172: 681b ldr r3, [r3, #0]
|
|
8005174: 2208 movs r2, #8
|
|
8005176: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_ORE;
|
|
8005178: 687b ldr r3, [r7, #4]
|
|
800517a: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
800517e: f043 0208 orr.w r2, r3, #8
|
|
8005182: 687b ldr r3, [r7, #4]
|
|
8005184: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
}
|
|
|
|
/* UART Receiver Timeout interrupt occurred ---------------------------------*/
|
|
if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
|
|
8005188: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
800518c: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
8005190: 2b00 cmp r3, #0
|
|
8005192: d012 beq.n 80051ba <HAL_UART_IRQHandler+0x18a>
|
|
8005194: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8005198: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
|
|
800519c: 2b00 cmp r3, #0
|
|
800519e: d00c beq.n 80051ba <HAL_UART_IRQHandler+0x18a>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
|
|
80051a0: 687b ldr r3, [r7, #4]
|
|
80051a2: 681b ldr r3, [r3, #0]
|
|
80051a4: f44f 6200 mov.w r2, #2048 @ 0x800
|
|
80051a8: 621a str r2, [r3, #32]
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_RTO;
|
|
80051aa: 687b ldr r3, [r7, #4]
|
|
80051ac: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
80051b0: f043 0220 orr.w r2, r3, #32
|
|
80051b4: 687b ldr r3, [r7, #4]
|
|
80051b6: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
}
|
|
|
|
/* Call UART Error Call back function if need be ----------------------------*/
|
|
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
|
|
80051ba: 687b ldr r3, [r7, #4]
|
|
80051bc: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
80051c0: 2b00 cmp r3, #0
|
|
80051c2: f000 8230 beq.w 8005626 <HAL_UART_IRQHandler+0x5f6>
|
|
#if defined(USART_CR1_FIFOEN)
|
|
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
|
|
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
|
|
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
|
|
#else
|
|
if (((isrflags & USART_ISR_RXNE) != 0U)
|
|
80051c6: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
80051ca: f003 0320 and.w r3, r3, #32
|
|
80051ce: 2b00 cmp r3, #0
|
|
80051d0: d00d beq.n 80051ee <HAL_UART_IRQHandler+0x1be>
|
|
&& ((cr1its & USART_CR1_RXNEIE) != 0U))
|
|
80051d2: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
80051d6: f003 0320 and.w r3, r3, #32
|
|
80051da: 2b00 cmp r3, #0
|
|
80051dc: d007 beq.n 80051ee <HAL_UART_IRQHandler+0x1be>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
{
|
|
if (huart->RxISR != NULL)
|
|
80051de: 687b ldr r3, [r7, #4]
|
|
80051e0: 6e9b ldr r3, [r3, #104] @ 0x68
|
|
80051e2: 2b00 cmp r3, #0
|
|
80051e4: d003 beq.n 80051ee <HAL_UART_IRQHandler+0x1be>
|
|
{
|
|
huart->RxISR(huart);
|
|
80051e6: 687b ldr r3, [r7, #4]
|
|
80051e8: 6e9b ldr r3, [r3, #104] @ 0x68
|
|
80051ea: 6878 ldr r0, [r7, #4]
|
|
80051ec: 4798 blx r3
|
|
/* If Error is to be considered as blocking :
|
|
- Receiver Timeout error in Reception
|
|
- Overrun error in Reception
|
|
- any error occurs in DMA mode reception
|
|
*/
|
|
errorcode = huart->ErrorCode;
|
|
80051ee: 687b ldr r3, [r7, #4]
|
|
80051f0: f8d3 3084 ldr.w r3, [r3, #132] @ 0x84
|
|
80051f4: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
|
|
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
|
|
80051f8: 687b ldr r3, [r7, #4]
|
|
80051fa: 681b ldr r3, [r3, #0]
|
|
80051fc: 689b ldr r3, [r3, #8]
|
|
80051fe: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8005202: 2b40 cmp r3, #64 @ 0x40
|
|
8005204: d005 beq.n 8005212 <HAL_UART_IRQHandler+0x1e2>
|
|
((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
|
|
8005206: f8d7 30d4 ldr.w r3, [r7, #212] @ 0xd4
|
|
800520a: f003 0328 and.w r3, r3, #40 @ 0x28
|
|
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
|
|
800520e: 2b00 cmp r3, #0
|
|
8005210: d04f beq.n 80052b2 <HAL_UART_IRQHandler+0x282>
|
|
{
|
|
/* Blocking error : transfer is aborted
|
|
Set the UART state ready to be able to start again the process,
|
|
Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
|
|
UART_EndRxTransfer(huart);
|
|
8005212: 6878 ldr r0, [r7, #4]
|
|
8005214: f000 ff68 bl 80060e8 <UART_EndRxTransfer>
|
|
|
|
/* Abort the UART DMA Rx channel if enabled */
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8005218: 687b ldr r3, [r7, #4]
|
|
800521a: 681b ldr r3, [r3, #0]
|
|
800521c: 689b ldr r3, [r3, #8]
|
|
800521e: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8005222: 2b40 cmp r3, #64 @ 0x40
|
|
8005224: d141 bne.n 80052aa <HAL_UART_IRQHandler+0x27a>
|
|
{
|
|
/* Disable the UART DMA Rx request if enabled */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
8005226: 687b ldr r3, [r7, #4]
|
|
8005228: 681b ldr r3, [r3, #0]
|
|
800522a: 3308 adds r3, #8
|
|
800522c: f8c7 309c str.w r3, [r7, #156] @ 0x9c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005230: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
|
|
8005234: e853 3f00 ldrex r3, [r3]
|
|
8005238: f8c7 3098 str.w r3, [r7, #152] @ 0x98
|
|
return(result);
|
|
800523c: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
|
|
8005240: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
8005244: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
|
|
8005248: 687b ldr r3, [r7, #4]
|
|
800524a: 681b ldr r3, [r3, #0]
|
|
800524c: 3308 adds r3, #8
|
|
800524e: f8d7 20d0 ldr.w r2, [r7, #208] @ 0xd0
|
|
8005252: f8c7 20a8 str.w r2, [r7, #168] @ 0xa8
|
|
8005256: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800525a: f8d7 10a4 ldr.w r1, [r7, #164] @ 0xa4
|
|
800525e: f8d7 20a8 ldr.w r2, [r7, #168] @ 0xa8
|
|
8005262: e841 2300 strex r3, r2, [r1]
|
|
8005266: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
|
|
return(result);
|
|
800526a: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
|
|
800526e: 2b00 cmp r3, #0
|
|
8005270: d1d9 bne.n 8005226 <HAL_UART_IRQHandler+0x1f6>
|
|
|
|
/* Abort the UART DMA Rx channel */
|
|
if (huart->hdmarx != NULL)
|
|
8005272: 687b ldr r3, [r7, #4]
|
|
8005274: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
8005276: 2b00 cmp r3, #0
|
|
8005278: d013 beq.n 80052a2 <HAL_UART_IRQHandler+0x272>
|
|
{
|
|
/* Set the UART DMA Abort callback :
|
|
will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
|
|
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
|
|
800527a: 687b ldr r3, [r7, #4]
|
|
800527c: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
800527e: 4a13 ldr r2, [pc, #76] @ (80052cc <HAL_UART_IRQHandler+0x29c>)
|
|
8005280: 639a str r2, [r3, #56] @ 0x38
|
|
|
|
/* Abort DMA RX */
|
|
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
|
|
8005282: 687b ldr r3, [r7, #4]
|
|
8005284: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
8005286: 4618 mov r0, r3
|
|
8005288: f7fd fa67 bl 800275a <HAL_DMA_Abort_IT>
|
|
800528c: 4603 mov r3, r0
|
|
800528e: 2b00 cmp r3, #0
|
|
8005290: d017 beq.n 80052c2 <HAL_UART_IRQHandler+0x292>
|
|
{
|
|
/* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
|
|
huart->hdmarx->XferAbortCallback(huart->hdmarx);
|
|
8005292: 687b ldr r3, [r7, #4]
|
|
8005294: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
8005296: 6b9b ldr r3, [r3, #56] @ 0x38
|
|
8005298: 687a ldr r2, [r7, #4]
|
|
800529a: 6f52 ldr r2, [r2, #116] @ 0x74
|
|
800529c: 4610 mov r0, r2
|
|
800529e: 4798 blx r3
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
80052a0: e00f b.n 80052c2 <HAL_UART_IRQHandler+0x292>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
80052a2: 6878 ldr r0, [r7, #4]
|
|
80052a4: f000 f9d4 bl 8005650 <HAL_UART_ErrorCallback>
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
80052a8: e00b b.n 80052c2 <HAL_UART_IRQHandler+0x292>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
80052aa: 6878 ldr r0, [r7, #4]
|
|
80052ac: f000 f9d0 bl 8005650 <HAL_UART_ErrorCallback>
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
80052b0: e007 b.n 80052c2 <HAL_UART_IRQHandler+0x292>
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
80052b2: 6878 ldr r0, [r7, #4]
|
|
80052b4: f000 f9cc bl 8005650 <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
80052b8: 687b ldr r3, [r7, #4]
|
|
80052ba: 2200 movs r2, #0
|
|
80052bc: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
}
|
|
}
|
|
return;
|
|
80052c0: e1b1 b.n 8005626 <HAL_UART_IRQHandler+0x5f6>
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
80052c2: bf00 nop
|
|
return;
|
|
80052c4: e1af b.n 8005626 <HAL_UART_IRQHandler+0x5f6>
|
|
80052c6: bf00 nop
|
|
80052c8: 04000120 .word 0x04000120
|
|
80052cc: 080061b1 .word 0x080061b1
|
|
|
|
} /* End if some error occurs */
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : */
|
|
if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
80052d0: 687b ldr r3, [r7, #4]
|
|
80052d2: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
80052d4: 2b01 cmp r3, #1
|
|
80052d6: f040 816a bne.w 80055ae <HAL_UART_IRQHandler+0x57e>
|
|
&& ((isrflags & USART_ISR_IDLE) != 0U)
|
|
80052da: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
80052de: f003 0310 and.w r3, r3, #16
|
|
80052e2: 2b00 cmp r3, #0
|
|
80052e4: f000 8163 beq.w 80055ae <HAL_UART_IRQHandler+0x57e>
|
|
&& ((cr1its & USART_ISR_IDLE) != 0U))
|
|
80052e8: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
80052ec: f003 0310 and.w r3, r3, #16
|
|
80052f0: 2b00 cmp r3, #0
|
|
80052f2: f000 815c beq.w 80055ae <HAL_UART_IRQHandler+0x57e>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
|
80052f6: 687b ldr r3, [r7, #4]
|
|
80052f8: 681b ldr r3, [r3, #0]
|
|
80052fa: 2210 movs r2, #16
|
|
80052fc: 621a str r2, [r3, #32]
|
|
|
|
/* Check if DMA mode is enabled in UART */
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
80052fe: 687b ldr r3, [r7, #4]
|
|
8005300: 681b ldr r3, [r3, #0]
|
|
8005302: 689b ldr r3, [r3, #8]
|
|
8005304: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8005308: 2b40 cmp r3, #64 @ 0x40
|
|
800530a: f040 80d4 bne.w 80054b6 <HAL_UART_IRQHandler+0x486>
|
|
{
|
|
/* DMA mode enabled */
|
|
/* Check received length : If all expected data are received, do nothing,
|
|
(DMA cplt callback will be called).
|
|
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
|
|
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
|
|
800530e: 687b ldr r3, [r7, #4]
|
|
8005310: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
8005312: 681b ldr r3, [r3, #0]
|
|
8005314: 685b ldr r3, [r3, #4]
|
|
8005316: f8a7 30be strh.w r3, [r7, #190] @ 0xbe
|
|
if ((nb_remaining_rx_data > 0U)
|
|
800531a: f8b7 30be ldrh.w r3, [r7, #190] @ 0xbe
|
|
800531e: 2b00 cmp r3, #0
|
|
8005320: f000 80ad beq.w 800547e <HAL_UART_IRQHandler+0x44e>
|
|
&& (nb_remaining_rx_data < huart->RxXferSize))
|
|
8005324: 687b ldr r3, [r7, #4]
|
|
8005326: f8b3 3058 ldrh.w r3, [r3, #88] @ 0x58
|
|
800532a: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
|
|
800532e: 429a cmp r2, r3
|
|
8005330: f080 80a5 bcs.w 800547e <HAL_UART_IRQHandler+0x44e>
|
|
{
|
|
/* Reception is not complete */
|
|
huart->RxXferCount = nb_remaining_rx_data;
|
|
8005334: 687b ldr r3, [r7, #4]
|
|
8005336: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
|
|
800533a: f8a3 205a strh.w r2, [r3, #90] @ 0x5a
|
|
|
|
/* In Normal mode, end DMA xfer and HAL UART Rx process*/
|
|
if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
|
|
800533e: 687b ldr r3, [r7, #4]
|
|
8005340: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
8005342: 681b ldr r3, [r3, #0]
|
|
8005344: 681b ldr r3, [r3, #0]
|
|
8005346: f003 0320 and.w r3, r3, #32
|
|
800534a: 2b00 cmp r3, #0
|
|
800534c: f040 8086 bne.w 800545c <HAL_UART_IRQHandler+0x42c>
|
|
{
|
|
/* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|
8005350: 687b ldr r3, [r7, #4]
|
|
8005352: 681b ldr r3, [r3, #0]
|
|
8005354: f8c7 3088 str.w r3, [r7, #136] @ 0x88
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005358: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
|
|
800535c: e853 3f00 ldrex r3, [r3]
|
|
8005360: f8c7 3084 str.w r3, [r7, #132] @ 0x84
|
|
return(result);
|
|
8005364: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
|
|
8005368: f423 7380 bic.w r3, r3, #256 @ 0x100
|
|
800536c: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
|
|
8005370: 687b ldr r3, [r7, #4]
|
|
8005372: 681b ldr r3, [r3, #0]
|
|
8005374: 461a mov r2, r3
|
|
8005376: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
|
|
800537a: f8c7 3094 str.w r3, [r7, #148] @ 0x94
|
|
800537e: f8c7 2090 str.w r2, [r7, #144] @ 0x90
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005382: f8d7 1090 ldr.w r1, [r7, #144] @ 0x90
|
|
8005386: f8d7 2094 ldr.w r2, [r7, #148] @ 0x94
|
|
800538a: e841 2300 strex r3, r2, [r1]
|
|
800538e: f8c7 308c str.w r3, [r7, #140] @ 0x8c
|
|
return(result);
|
|
8005392: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
|
|
8005396: 2b00 cmp r3, #0
|
|
8005398: d1da bne.n 8005350 <HAL_UART_IRQHandler+0x320>
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
800539a: 687b ldr r3, [r7, #4]
|
|
800539c: 681b ldr r3, [r3, #0]
|
|
800539e: 3308 adds r3, #8
|
|
80053a0: 677b str r3, [r7, #116] @ 0x74
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80053a2: 6f7b ldr r3, [r7, #116] @ 0x74
|
|
80053a4: e853 3f00 ldrex r3, [r3]
|
|
80053a8: 673b str r3, [r7, #112] @ 0x70
|
|
return(result);
|
|
80053aa: 6f3b ldr r3, [r7, #112] @ 0x70
|
|
80053ac: f023 0301 bic.w r3, r3, #1
|
|
80053b0: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
|
|
80053b4: 687b ldr r3, [r7, #4]
|
|
80053b6: 681b ldr r3, [r3, #0]
|
|
80053b8: 3308 adds r3, #8
|
|
80053ba: f8d7 20b4 ldr.w r2, [r7, #180] @ 0xb4
|
|
80053be: f8c7 2080 str.w r2, [r7, #128] @ 0x80
|
|
80053c2: 67fb str r3, [r7, #124] @ 0x7c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80053c4: 6ff9 ldr r1, [r7, #124] @ 0x7c
|
|
80053c6: f8d7 2080 ldr.w r2, [r7, #128] @ 0x80
|
|
80053ca: e841 2300 strex r3, r2, [r1]
|
|
80053ce: 67bb str r3, [r7, #120] @ 0x78
|
|
return(result);
|
|
80053d0: 6fbb ldr r3, [r7, #120] @ 0x78
|
|
80053d2: 2b00 cmp r3, #0
|
|
80053d4: d1e1 bne.n 800539a <HAL_UART_IRQHandler+0x36a>
|
|
|
|
/* Disable the DMA transfer for the receiver request by resetting the DMAR bit
|
|
in the UART CR3 register */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
80053d6: 687b ldr r3, [r7, #4]
|
|
80053d8: 681b ldr r3, [r3, #0]
|
|
80053da: 3308 adds r3, #8
|
|
80053dc: 663b str r3, [r7, #96] @ 0x60
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80053de: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
80053e0: e853 3f00 ldrex r3, [r3]
|
|
80053e4: 65fb str r3, [r7, #92] @ 0x5c
|
|
return(result);
|
|
80053e6: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
80053e8: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
80053ec: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
|
|
80053f0: 687b ldr r3, [r7, #4]
|
|
80053f2: 681b ldr r3, [r3, #0]
|
|
80053f4: 3308 adds r3, #8
|
|
80053f6: f8d7 20b0 ldr.w r2, [r7, #176] @ 0xb0
|
|
80053fa: 66fa str r2, [r7, #108] @ 0x6c
|
|
80053fc: 66bb str r3, [r7, #104] @ 0x68
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80053fe: 6eb9 ldr r1, [r7, #104] @ 0x68
|
|
8005400: 6efa ldr r2, [r7, #108] @ 0x6c
|
|
8005402: e841 2300 strex r3, r2, [r1]
|
|
8005406: 667b str r3, [r7, #100] @ 0x64
|
|
return(result);
|
|
8005408: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
800540a: 2b00 cmp r3, #0
|
|
800540c: d1e3 bne.n 80053d6 <HAL_UART_IRQHandler+0x3a6>
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
800540e: 687b ldr r3, [r7, #4]
|
|
8005410: 2220 movs r2, #32
|
|
8005412: f8c3 2080 str.w r2, [r3, #128] @ 0x80
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8005416: 687b ldr r3, [r7, #4]
|
|
8005418: 2200 movs r2, #0
|
|
800541a: 661a str r2, [r3, #96] @ 0x60
|
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
800541c: 687b ldr r3, [r7, #4]
|
|
800541e: 681b ldr r3, [r3, #0]
|
|
8005420: 64fb str r3, [r7, #76] @ 0x4c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005422: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
8005424: e853 3f00 ldrex r3, [r3]
|
|
8005428: 64bb str r3, [r7, #72] @ 0x48
|
|
return(result);
|
|
800542a: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800542c: f023 0310 bic.w r3, r3, #16
|
|
8005430: f8c7 30ac str.w r3, [r7, #172] @ 0xac
|
|
8005434: 687b ldr r3, [r7, #4]
|
|
8005436: 681b ldr r3, [r3, #0]
|
|
8005438: 461a mov r2, r3
|
|
800543a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
|
|
800543e: 65bb str r3, [r7, #88] @ 0x58
|
|
8005440: 657a str r2, [r7, #84] @ 0x54
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005442: 6d79 ldr r1, [r7, #84] @ 0x54
|
|
8005444: 6dba ldr r2, [r7, #88] @ 0x58
|
|
8005446: e841 2300 strex r3, r2, [r1]
|
|
800544a: 653b str r3, [r7, #80] @ 0x50
|
|
return(result);
|
|
800544c: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
800544e: 2b00 cmp r3, #0
|
|
8005450: d1e4 bne.n 800541c <HAL_UART_IRQHandler+0x3ec>
|
|
|
|
/* Last bytes received, so no need as the abort is immediate */
|
|
(void)HAL_DMA_Abort(huart->hdmarx);
|
|
8005452: 687b ldr r3, [r7, #4]
|
|
8005454: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
8005456: 4618 mov r0, r3
|
|
8005458: f7fd f941 bl 80026de <HAL_DMA_Abort>
|
|
}
|
|
|
|
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
|
|
In this case, Rx Event type is Idle Event */
|
|
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
|
|
800545c: 687b ldr r3, [r7, #4]
|
|
800545e: 2202 movs r2, #2
|
|
8005460: 665a str r2, [r3, #100] @ 0x64
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
|
|
8005462: 687b ldr r3, [r7, #4]
|
|
8005464: f8b3 2058 ldrh.w r2, [r3, #88] @ 0x58
|
|
8005468: 687b ldr r3, [r7, #4]
|
|
800546a: f8b3 305a ldrh.w r3, [r3, #90] @ 0x5a
|
|
800546e: b29b uxth r3, r3
|
|
8005470: 1ad3 subs r3, r2, r3
|
|
8005472: b29b uxth r3, r3
|
|
8005474: 4619 mov r1, r3
|
|
8005476: 6878 ldr r0, [r7, #4]
|
|
8005478: f000 f8f4 bl 8005664 <HAL_UARTEx_RxEventCallback>
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
}
|
|
}
|
|
return;
|
|
800547c: e0d5 b.n 800562a <HAL_UART_IRQHandler+0x5fa>
|
|
if (nb_remaining_rx_data == huart->RxXferSize)
|
|
800547e: 687b ldr r3, [r7, #4]
|
|
8005480: f8b3 3058 ldrh.w r3, [r3, #88] @ 0x58
|
|
8005484: f8b7 20be ldrh.w r2, [r7, #190] @ 0xbe
|
|
8005488: 429a cmp r2, r3
|
|
800548a: f040 80ce bne.w 800562a <HAL_UART_IRQHandler+0x5fa>
|
|
if (HAL_IS_BIT_SET(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
|
|
800548e: 687b ldr r3, [r7, #4]
|
|
8005490: 6f5b ldr r3, [r3, #116] @ 0x74
|
|
8005492: 681b ldr r3, [r3, #0]
|
|
8005494: 681b ldr r3, [r3, #0]
|
|
8005496: f003 0320 and.w r3, r3, #32
|
|
800549a: 2b20 cmp r3, #32
|
|
800549c: f040 80c5 bne.w 800562a <HAL_UART_IRQHandler+0x5fa>
|
|
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
|
|
80054a0: 687b ldr r3, [r7, #4]
|
|
80054a2: 2202 movs r2, #2
|
|
80054a4: 665a str r2, [r3, #100] @ 0x64
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
80054a6: 687b ldr r3, [r7, #4]
|
|
80054a8: f8b3 3058 ldrh.w r3, [r3, #88] @ 0x58
|
|
80054ac: 4619 mov r1, r3
|
|
80054ae: 6878 ldr r0, [r7, #4]
|
|
80054b0: f000 f8d8 bl 8005664 <HAL_UARTEx_RxEventCallback>
|
|
return;
|
|
80054b4: e0b9 b.n 800562a <HAL_UART_IRQHandler+0x5fa>
|
|
else
|
|
{
|
|
/* DMA mode not enabled */
|
|
/* Check received length : If all expected data are received, do nothing.
|
|
Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
|
|
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
|
|
80054b6: 687b ldr r3, [r7, #4]
|
|
80054b8: f8b3 2058 ldrh.w r2, [r3, #88] @ 0x58
|
|
80054bc: 687b ldr r3, [r7, #4]
|
|
80054be: f8b3 305a ldrh.w r3, [r3, #90] @ 0x5a
|
|
80054c2: b29b uxth r3, r3
|
|
80054c4: 1ad3 subs r3, r2, r3
|
|
80054c6: f8a7 30ce strh.w r3, [r7, #206] @ 0xce
|
|
if ((huart->RxXferCount > 0U)
|
|
80054ca: 687b ldr r3, [r7, #4]
|
|
80054cc: f8b3 305a ldrh.w r3, [r3, #90] @ 0x5a
|
|
80054d0: b29b uxth r3, r3
|
|
80054d2: 2b00 cmp r3, #0
|
|
80054d4: f000 80ab beq.w 800562e <HAL_UART_IRQHandler+0x5fe>
|
|
&& (nb_rx_data > 0U))
|
|
80054d8: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce
|
|
80054dc: 2b00 cmp r3, #0
|
|
80054de: f000 80a6 beq.w 800562e <HAL_UART_IRQHandler+0x5fe>
|
|
|
|
/* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
|
#else
|
|
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|
80054e2: 687b ldr r3, [r7, #4]
|
|
80054e4: 681b ldr r3, [r3, #0]
|
|
80054e6: 63bb str r3, [r7, #56] @ 0x38
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80054e8: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
80054ea: e853 3f00 ldrex r3, [r3]
|
|
80054ee: 637b str r3, [r7, #52] @ 0x34
|
|
return(result);
|
|
80054f0: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
80054f2: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
80054f6: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
|
|
80054fa: 687b ldr r3, [r7, #4]
|
|
80054fc: 681b ldr r3, [r3, #0]
|
|
80054fe: 461a mov r2, r3
|
|
8005500: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
|
|
8005504: 647b str r3, [r7, #68] @ 0x44
|
|
8005506: 643a str r2, [r7, #64] @ 0x40
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005508: 6c39 ldr r1, [r7, #64] @ 0x40
|
|
800550a: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
800550c: e841 2300 strex r3, r2, [r1]
|
|
8005510: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
8005512: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8005514: 2b00 cmp r3, #0
|
|
8005516: d1e4 bne.n 80054e2 <HAL_UART_IRQHandler+0x4b2>
|
|
|
|
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8005518: 687b ldr r3, [r7, #4]
|
|
800551a: 681b ldr r3, [r3, #0]
|
|
800551c: 3308 adds r3, #8
|
|
800551e: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005520: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8005522: e853 3f00 ldrex r3, [r3]
|
|
8005526: 623b str r3, [r7, #32]
|
|
return(result);
|
|
8005528: 6a3b ldr r3, [r7, #32]
|
|
800552a: f023 0301 bic.w r3, r3, #1
|
|
800552e: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4
|
|
8005532: 687b ldr r3, [r7, #4]
|
|
8005534: 681b ldr r3, [r3, #0]
|
|
8005536: 3308 adds r3, #8
|
|
8005538: f8d7 20c4 ldr.w r2, [r7, #196] @ 0xc4
|
|
800553c: 633a str r2, [r7, #48] @ 0x30
|
|
800553e: 62fb str r3, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005540: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
8005542: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
8005544: e841 2300 strex r3, r2, [r1]
|
|
8005548: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
800554a: 6abb ldr r3, [r7, #40] @ 0x28
|
|
800554c: 2b00 cmp r3, #0
|
|
800554e: d1e3 bne.n 8005518 <HAL_UART_IRQHandler+0x4e8>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8005550: 687b ldr r3, [r7, #4]
|
|
8005552: 2220 movs r2, #32
|
|
8005554: f8c3 2080 str.w r2, [r3, #128] @ 0x80
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8005558: 687b ldr r3, [r7, #4]
|
|
800555a: 2200 movs r2, #0
|
|
800555c: 661a str r2, [r3, #96] @ 0x60
|
|
|
|
/* Clear RxISR function pointer */
|
|
huart->RxISR = NULL;
|
|
800555e: 687b ldr r3, [r7, #4]
|
|
8005560: 2200 movs r2, #0
|
|
8005562: 669a str r2, [r3, #104] @ 0x68
|
|
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8005564: 687b ldr r3, [r7, #4]
|
|
8005566: 681b ldr r3, [r3, #0]
|
|
8005568: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800556a: 693b ldr r3, [r7, #16]
|
|
800556c: e853 3f00 ldrex r3, [r3]
|
|
8005570: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
8005572: 68fb ldr r3, [r7, #12]
|
|
8005574: f023 0310 bic.w r3, r3, #16
|
|
8005578: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
|
|
800557c: 687b ldr r3, [r7, #4]
|
|
800557e: 681b ldr r3, [r3, #0]
|
|
8005580: 461a mov r2, r3
|
|
8005582: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0
|
|
8005586: 61fb str r3, [r7, #28]
|
|
8005588: 61ba str r2, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800558a: 69b9 ldr r1, [r7, #24]
|
|
800558c: 69fa ldr r2, [r7, #28]
|
|
800558e: e841 2300 strex r3, r2, [r1]
|
|
8005592: 617b str r3, [r7, #20]
|
|
return(result);
|
|
8005594: 697b ldr r3, [r7, #20]
|
|
8005596: 2b00 cmp r3, #0
|
|
8005598: d1e4 bne.n 8005564 <HAL_UART_IRQHandler+0x534>
|
|
|
|
/* Initialize type of RxEvent that correspond to RxEvent callback execution;
|
|
In this case, Rx Event type is Idle Event */
|
|
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
|
|
800559a: 687b ldr r3, [r7, #4]
|
|
800559c: 2202 movs r2, #2
|
|
800559e: 665a str r2, [r3, #100] @ 0x64
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx complete callback*/
|
|
huart->RxEventCallback(huart, nb_rx_data);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
|
|
80055a0: f8b7 30ce ldrh.w r3, [r7, #206] @ 0xce
|
|
80055a4: 4619 mov r1, r3
|
|
80055a6: 6878 ldr r0, [r7, #4]
|
|
80055a8: f000 f85c bl 8005664 <HAL_UARTEx_RxEventCallback>
|
|
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
|
|
}
|
|
return;
|
|
80055ac: e03f b.n 800562e <HAL_UART_IRQHandler+0x5fe>
|
|
}
|
|
}
|
|
|
|
/* UART wakeup from Stop mode interrupt occurred ---------------------------*/
|
|
if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
|
|
80055ae: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
80055b2: f403 1380 and.w r3, r3, #1048576 @ 0x100000
|
|
80055b6: 2b00 cmp r3, #0
|
|
80055b8: d00e beq.n 80055d8 <HAL_UART_IRQHandler+0x5a8>
|
|
80055ba: f8d7 30dc ldr.w r3, [r7, #220] @ 0xdc
|
|
80055be: f403 0380 and.w r3, r3, #4194304 @ 0x400000
|
|
80055c2: 2b00 cmp r3, #0
|
|
80055c4: d008 beq.n 80055d8 <HAL_UART_IRQHandler+0x5a8>
|
|
{
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
|
|
80055c6: 687b ldr r3, [r7, #4]
|
|
80055c8: 681b ldr r3, [r3, #0]
|
|
80055ca: f44f 1280 mov.w r2, #1048576 @ 0x100000
|
|
80055ce: 621a str r2, [r3, #32]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/* Call registered Wakeup Callback */
|
|
huart->WakeupCallback(huart);
|
|
#else
|
|
/* Call legacy weak Wakeup Callback */
|
|
HAL_UARTEx_WakeupCallback(huart);
|
|
80055d0: 6878 ldr r0, [r7, #4]
|
|
80055d2: f000 ffe9 bl 80065a8 <HAL_UARTEx_WakeupCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
return;
|
|
80055d6: e02d b.n 8005634 <HAL_UART_IRQHandler+0x604>
|
|
#if defined(USART_CR1_FIFOEN)
|
|
if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
|
|
&& (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
|
|
|| ((cr3its & USART_CR3_TXFTIE) != 0U)))
|
|
#else
|
|
if (((isrflags & USART_ISR_TXE) != 0U)
|
|
80055d8: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
80055dc: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
80055e0: 2b00 cmp r3, #0
|
|
80055e2: d00e beq.n 8005602 <HAL_UART_IRQHandler+0x5d2>
|
|
&& ((cr1its & USART_CR1_TXEIE) != 0U))
|
|
80055e4: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
80055e8: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
80055ec: 2b00 cmp r3, #0
|
|
80055ee: d008 beq.n 8005602 <HAL_UART_IRQHandler+0x5d2>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
{
|
|
if (huart->TxISR != NULL)
|
|
80055f0: 687b ldr r3, [r7, #4]
|
|
80055f2: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
80055f4: 2b00 cmp r3, #0
|
|
80055f6: d01c beq.n 8005632 <HAL_UART_IRQHandler+0x602>
|
|
{
|
|
huart->TxISR(huart);
|
|
80055f8: 687b ldr r3, [r7, #4]
|
|
80055fa: 6edb ldr r3, [r3, #108] @ 0x6c
|
|
80055fc: 6878 ldr r0, [r7, #4]
|
|
80055fe: 4798 blx r3
|
|
}
|
|
return;
|
|
8005600: e017 b.n 8005632 <HAL_UART_IRQHandler+0x602>
|
|
}
|
|
|
|
/* UART in mode Transmitter (transmission end) -----------------------------*/
|
|
if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
|
|
8005602: f8d7 30e4 ldr.w r3, [r7, #228] @ 0xe4
|
|
8005606: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
800560a: 2b00 cmp r3, #0
|
|
800560c: d012 beq.n 8005634 <HAL_UART_IRQHandler+0x604>
|
|
800560e: f8d7 30e0 ldr.w r3, [r7, #224] @ 0xe0
|
|
8005612: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8005616: 2b00 cmp r3, #0
|
|
8005618: d00c beq.n 8005634 <HAL_UART_IRQHandler+0x604>
|
|
{
|
|
UART_EndTransmit_IT(huart);
|
|
800561a: 6878 ldr r0, [r7, #4]
|
|
800561c: f000 fdde bl 80061dc <UART_EndTransmit_IT>
|
|
return;
|
|
8005620: e008 b.n 8005634 <HAL_UART_IRQHandler+0x604>
|
|
return;
|
|
8005622: bf00 nop
|
|
8005624: e006 b.n 8005634 <HAL_UART_IRQHandler+0x604>
|
|
return;
|
|
8005626: bf00 nop
|
|
8005628: e004 b.n 8005634 <HAL_UART_IRQHandler+0x604>
|
|
return;
|
|
800562a: bf00 nop
|
|
800562c: e002 b.n 8005634 <HAL_UART_IRQHandler+0x604>
|
|
return;
|
|
800562e: bf00 nop
|
|
8005630: e000 b.n 8005634 <HAL_UART_IRQHandler+0x604>
|
|
return;
|
|
8005632: bf00 nop
|
|
HAL_UARTEx_RxFifoFullCallback(huart);
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
return;
|
|
}
|
|
#endif /* USART_CR1_FIFOEN */
|
|
}
|
|
8005634: 37e8 adds r7, #232 @ 0xe8
|
|
8005636: 46bd mov sp, r7
|
|
8005638: bd80 pop {r7, pc}
|
|
800563a: bf00 nop
|
|
|
|
0800563c <HAL_UART_TxCpltCallback>:
|
|
* @brief Tx Transfer completed callback.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
800563c: b480 push {r7}
|
|
800563e: b083 sub sp, #12
|
|
8005640: af00 add r7, sp, #0
|
|
8005642: 6078 str r0, [r7, #4]
|
|
UNUSED(huart);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UART_TxCpltCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
8005644: bf00 nop
|
|
8005646: 370c adds r7, #12
|
|
8005648: 46bd mov sp, r7
|
|
800564a: f85d 7b04 ldr.w r7, [sp], #4
|
|
800564e: 4770 bx lr
|
|
|
|
08005650 <HAL_UART_ErrorCallback>:
|
|
* @brief UART error callback.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
8005650: b480 push {r7}
|
|
8005652: b083 sub sp, #12
|
|
8005654: af00 add r7, sp, #0
|
|
8005656: 6078 str r0, [r7, #4]
|
|
UNUSED(huart);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UART_ErrorCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
8005658: bf00 nop
|
|
800565a: 370c adds r7, #12
|
|
800565c: 46bd mov sp, r7
|
|
800565e: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005662: 4770 bx lr
|
|
|
|
08005664 <HAL_UARTEx_RxEventCallback>:
|
|
* @param Size Number of data available in application reception buffer (indicates a position in
|
|
* reception buffer until which, data are available)
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
|
|
{
|
|
8005664: b480 push {r7}
|
|
8005666: b083 sub sp, #12
|
|
8005668: af00 add r7, sp, #0
|
|
800566a: 6078 str r0, [r7, #4]
|
|
800566c: 460b mov r3, r1
|
|
800566e: 807b strh r3, [r7, #2]
|
|
UNUSED(Size);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UARTEx_RxEventCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
8005670: bf00 nop
|
|
8005672: 370c adds r7, #12
|
|
8005674: 46bd mov sp, r7
|
|
8005676: f85d 7b04 ldr.w r7, [sp], #4
|
|
800567a: 4770 bx lr
|
|
|
|
0800567c <UART_SetConfig>:
|
|
* @brief Configure the UART peripheral.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
800567c: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
|
|
8005680: b08a sub sp, #40 @ 0x28
|
|
8005682: af00 add r7, sp, #0
|
|
8005684: 60f8 str r0, [r7, #12]
|
|
uint32_t tmpreg;
|
|
uint16_t brrtemp;
|
|
UART_ClockSourceTypeDef clocksource;
|
|
uint32_t usartdiv;
|
|
HAL_StatusTypeDef ret = HAL_OK;
|
|
8005686: 2300 movs r3, #0
|
|
8005688: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
* the UART Word Length, Parity, Mode and oversampling:
|
|
* set the M bits according to huart->Init.WordLength value
|
|
* set PCE and PS bits according to huart->Init.Parity value
|
|
* set TE and RE bits according to huart->Init.Mode value
|
|
* set OVER8 bit according to huart->Init.OverSampling value */
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
|
|
800568c: 68fb ldr r3, [r7, #12]
|
|
800568e: 689a ldr r2, [r3, #8]
|
|
8005690: 68fb ldr r3, [r7, #12]
|
|
8005692: 691b ldr r3, [r3, #16]
|
|
8005694: 431a orrs r2, r3
|
|
8005696: 68fb ldr r3, [r7, #12]
|
|
8005698: 695b ldr r3, [r3, #20]
|
|
800569a: 431a orrs r2, r3
|
|
800569c: 68fb ldr r3, [r7, #12]
|
|
800569e: 69db ldr r3, [r3, #28]
|
|
80056a0: 4313 orrs r3, r2
|
|
80056a2: 627b str r3, [r7, #36] @ 0x24
|
|
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
|
|
80056a4: 68fb ldr r3, [r7, #12]
|
|
80056a6: 681b ldr r3, [r3, #0]
|
|
80056a8: 681a ldr r2, [r3, #0]
|
|
80056aa: 4ba4 ldr r3, [pc, #656] @ (800593c <UART_SetConfig+0x2c0>)
|
|
80056ac: 4013 ands r3, r2
|
|
80056ae: 68fa ldr r2, [r7, #12]
|
|
80056b0: 6812 ldr r2, [r2, #0]
|
|
80056b2: 6a79 ldr r1, [r7, #36] @ 0x24
|
|
80056b4: 430b orrs r3, r1
|
|
80056b6: 6013 str r3, [r2, #0]
|
|
|
|
/*-------------------------- USART CR2 Configuration -----------------------*/
|
|
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
|
|
* to huart->Init.StopBits value */
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
|
|
80056b8: 68fb ldr r3, [r7, #12]
|
|
80056ba: 681b ldr r3, [r3, #0]
|
|
80056bc: 685b ldr r3, [r3, #4]
|
|
80056be: f423 5140 bic.w r1, r3, #12288 @ 0x3000
|
|
80056c2: 68fb ldr r3, [r7, #12]
|
|
80056c4: 68da ldr r2, [r3, #12]
|
|
80056c6: 68fb ldr r3, [r7, #12]
|
|
80056c8: 681b ldr r3, [r3, #0]
|
|
80056ca: 430a orrs r2, r1
|
|
80056cc: 605a str r2, [r3, #4]
|
|
/* Configure
|
|
* - UART HardWare Flow Control: set CTSE and RTSE bits according
|
|
* to huart->Init.HwFlowCtl value
|
|
* - one-bit sampling method versus three samples' majority rule according
|
|
* to huart->Init.OneBitSampling (not applicable to LPUART) */
|
|
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
|
|
80056ce: 68fb ldr r3, [r7, #12]
|
|
80056d0: 699b ldr r3, [r3, #24]
|
|
80056d2: 627b str r3, [r7, #36] @ 0x24
|
|
|
|
if (!(UART_INSTANCE_LOWPOWER(huart)))
|
|
80056d4: 68fb ldr r3, [r7, #12]
|
|
80056d6: 681b ldr r3, [r3, #0]
|
|
80056d8: 4a99 ldr r2, [pc, #612] @ (8005940 <UART_SetConfig+0x2c4>)
|
|
80056da: 4293 cmp r3, r2
|
|
80056dc: d004 beq.n 80056e8 <UART_SetConfig+0x6c>
|
|
{
|
|
tmpreg |= huart->Init.OneBitSampling;
|
|
80056de: 68fb ldr r3, [r7, #12]
|
|
80056e0: 6a1b ldr r3, [r3, #32]
|
|
80056e2: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80056e4: 4313 orrs r3, r2
|
|
80056e6: 627b str r3, [r7, #36] @ 0x24
|
|
}
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
|
|
80056e8: 68fb ldr r3, [r7, #12]
|
|
80056ea: 681b ldr r3, [r3, #0]
|
|
80056ec: 689b ldr r3, [r3, #8]
|
|
80056ee: f423 6130 bic.w r1, r3, #2816 @ 0xb00
|
|
80056f2: 68fb ldr r3, [r7, #12]
|
|
80056f4: 681b ldr r3, [r3, #0]
|
|
80056f6: 6a7a ldr r2, [r7, #36] @ 0x24
|
|
80056f8: 430a orrs r2, r1
|
|
80056fa: 609a str r2, [r3, #8]
|
|
* - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
|
|
MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
|
|
#endif /* USART_PRESC_PRESCALER */
|
|
|
|
/*-------------------------- USART BRR Configuration -----------------------*/
|
|
UART_GETCLOCKSOURCE(huart, clocksource);
|
|
80056fc: 68fb ldr r3, [r7, #12]
|
|
80056fe: 681b ldr r3, [r3, #0]
|
|
8005700: 4a90 ldr r2, [pc, #576] @ (8005944 <UART_SetConfig+0x2c8>)
|
|
8005702: 4293 cmp r3, r2
|
|
8005704: d126 bne.n 8005754 <UART_SetConfig+0xd8>
|
|
8005706: 4b90 ldr r3, [pc, #576] @ (8005948 <UART_SetConfig+0x2cc>)
|
|
8005708: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
800570c: f003 0303 and.w r3, r3, #3
|
|
8005710: 2b03 cmp r3, #3
|
|
8005712: d81b bhi.n 800574c <UART_SetConfig+0xd0>
|
|
8005714: a201 add r2, pc, #4 @ (adr r2, 800571c <UART_SetConfig+0xa0>)
|
|
8005716: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800571a: bf00 nop
|
|
800571c: 0800572d .word 0x0800572d
|
|
8005720: 0800573d .word 0x0800573d
|
|
8005724: 08005735 .word 0x08005735
|
|
8005728: 08005745 .word 0x08005745
|
|
800572c: 2301 movs r3, #1
|
|
800572e: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8005732: e116 b.n 8005962 <UART_SetConfig+0x2e6>
|
|
8005734: 2302 movs r3, #2
|
|
8005736: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800573a: e112 b.n 8005962 <UART_SetConfig+0x2e6>
|
|
800573c: 2304 movs r3, #4
|
|
800573e: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8005742: e10e b.n 8005962 <UART_SetConfig+0x2e6>
|
|
8005744: 2308 movs r3, #8
|
|
8005746: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800574a: e10a b.n 8005962 <UART_SetConfig+0x2e6>
|
|
800574c: 2310 movs r3, #16
|
|
800574e: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8005752: e106 b.n 8005962 <UART_SetConfig+0x2e6>
|
|
8005754: 68fb ldr r3, [r7, #12]
|
|
8005756: 681b ldr r3, [r3, #0]
|
|
8005758: 4a7c ldr r2, [pc, #496] @ (800594c <UART_SetConfig+0x2d0>)
|
|
800575a: 4293 cmp r3, r2
|
|
800575c: d138 bne.n 80057d0 <UART_SetConfig+0x154>
|
|
800575e: 4b7a ldr r3, [pc, #488] @ (8005948 <UART_SetConfig+0x2cc>)
|
|
8005760: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8005764: f003 030c and.w r3, r3, #12
|
|
8005768: 2b0c cmp r3, #12
|
|
800576a: d82d bhi.n 80057c8 <UART_SetConfig+0x14c>
|
|
800576c: a201 add r2, pc, #4 @ (adr r2, 8005774 <UART_SetConfig+0xf8>)
|
|
800576e: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8005772: bf00 nop
|
|
8005774: 080057a9 .word 0x080057a9
|
|
8005778: 080057c9 .word 0x080057c9
|
|
800577c: 080057c9 .word 0x080057c9
|
|
8005780: 080057c9 .word 0x080057c9
|
|
8005784: 080057b9 .word 0x080057b9
|
|
8005788: 080057c9 .word 0x080057c9
|
|
800578c: 080057c9 .word 0x080057c9
|
|
8005790: 080057c9 .word 0x080057c9
|
|
8005794: 080057b1 .word 0x080057b1
|
|
8005798: 080057c9 .word 0x080057c9
|
|
800579c: 080057c9 .word 0x080057c9
|
|
80057a0: 080057c9 .word 0x080057c9
|
|
80057a4: 080057c1 .word 0x080057c1
|
|
80057a8: 2300 movs r3, #0
|
|
80057aa: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80057ae: e0d8 b.n 8005962 <UART_SetConfig+0x2e6>
|
|
80057b0: 2302 movs r3, #2
|
|
80057b2: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80057b6: e0d4 b.n 8005962 <UART_SetConfig+0x2e6>
|
|
80057b8: 2304 movs r3, #4
|
|
80057ba: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80057be: e0d0 b.n 8005962 <UART_SetConfig+0x2e6>
|
|
80057c0: 2308 movs r3, #8
|
|
80057c2: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80057c6: e0cc b.n 8005962 <UART_SetConfig+0x2e6>
|
|
80057c8: 2310 movs r3, #16
|
|
80057ca: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80057ce: e0c8 b.n 8005962 <UART_SetConfig+0x2e6>
|
|
80057d0: 68fb ldr r3, [r7, #12]
|
|
80057d2: 681b ldr r3, [r3, #0]
|
|
80057d4: 4a5e ldr r2, [pc, #376] @ (8005950 <UART_SetConfig+0x2d4>)
|
|
80057d6: 4293 cmp r3, r2
|
|
80057d8: d125 bne.n 8005826 <UART_SetConfig+0x1aa>
|
|
80057da: 4b5b ldr r3, [pc, #364] @ (8005948 <UART_SetConfig+0x2cc>)
|
|
80057dc: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80057e0: f003 0330 and.w r3, r3, #48 @ 0x30
|
|
80057e4: 2b30 cmp r3, #48 @ 0x30
|
|
80057e6: d016 beq.n 8005816 <UART_SetConfig+0x19a>
|
|
80057e8: 2b30 cmp r3, #48 @ 0x30
|
|
80057ea: d818 bhi.n 800581e <UART_SetConfig+0x1a2>
|
|
80057ec: 2b20 cmp r3, #32
|
|
80057ee: d00a beq.n 8005806 <UART_SetConfig+0x18a>
|
|
80057f0: 2b20 cmp r3, #32
|
|
80057f2: d814 bhi.n 800581e <UART_SetConfig+0x1a2>
|
|
80057f4: 2b00 cmp r3, #0
|
|
80057f6: d002 beq.n 80057fe <UART_SetConfig+0x182>
|
|
80057f8: 2b10 cmp r3, #16
|
|
80057fa: d008 beq.n 800580e <UART_SetConfig+0x192>
|
|
80057fc: e00f b.n 800581e <UART_SetConfig+0x1a2>
|
|
80057fe: 2300 movs r3, #0
|
|
8005800: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8005804: e0ad b.n 8005962 <UART_SetConfig+0x2e6>
|
|
8005806: 2302 movs r3, #2
|
|
8005808: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800580c: e0a9 b.n 8005962 <UART_SetConfig+0x2e6>
|
|
800580e: 2304 movs r3, #4
|
|
8005810: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8005814: e0a5 b.n 8005962 <UART_SetConfig+0x2e6>
|
|
8005816: 2308 movs r3, #8
|
|
8005818: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800581c: e0a1 b.n 8005962 <UART_SetConfig+0x2e6>
|
|
800581e: 2310 movs r3, #16
|
|
8005820: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8005824: e09d b.n 8005962 <UART_SetConfig+0x2e6>
|
|
8005826: 68fb ldr r3, [r7, #12]
|
|
8005828: 681b ldr r3, [r3, #0]
|
|
800582a: 4a4a ldr r2, [pc, #296] @ (8005954 <UART_SetConfig+0x2d8>)
|
|
800582c: 4293 cmp r3, r2
|
|
800582e: d125 bne.n 800587c <UART_SetConfig+0x200>
|
|
8005830: 4b45 ldr r3, [pc, #276] @ (8005948 <UART_SetConfig+0x2cc>)
|
|
8005832: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
8005836: f003 03c0 and.w r3, r3, #192 @ 0xc0
|
|
800583a: 2bc0 cmp r3, #192 @ 0xc0
|
|
800583c: d016 beq.n 800586c <UART_SetConfig+0x1f0>
|
|
800583e: 2bc0 cmp r3, #192 @ 0xc0
|
|
8005840: d818 bhi.n 8005874 <UART_SetConfig+0x1f8>
|
|
8005842: 2b80 cmp r3, #128 @ 0x80
|
|
8005844: d00a beq.n 800585c <UART_SetConfig+0x1e0>
|
|
8005846: 2b80 cmp r3, #128 @ 0x80
|
|
8005848: d814 bhi.n 8005874 <UART_SetConfig+0x1f8>
|
|
800584a: 2b00 cmp r3, #0
|
|
800584c: d002 beq.n 8005854 <UART_SetConfig+0x1d8>
|
|
800584e: 2b40 cmp r3, #64 @ 0x40
|
|
8005850: d008 beq.n 8005864 <UART_SetConfig+0x1e8>
|
|
8005852: e00f b.n 8005874 <UART_SetConfig+0x1f8>
|
|
8005854: 2300 movs r3, #0
|
|
8005856: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800585a: e082 b.n 8005962 <UART_SetConfig+0x2e6>
|
|
800585c: 2302 movs r3, #2
|
|
800585e: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8005862: e07e b.n 8005962 <UART_SetConfig+0x2e6>
|
|
8005864: 2304 movs r3, #4
|
|
8005866: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800586a: e07a b.n 8005962 <UART_SetConfig+0x2e6>
|
|
800586c: 2308 movs r3, #8
|
|
800586e: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8005872: e076 b.n 8005962 <UART_SetConfig+0x2e6>
|
|
8005874: 2310 movs r3, #16
|
|
8005876: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800587a: e072 b.n 8005962 <UART_SetConfig+0x2e6>
|
|
800587c: 68fb ldr r3, [r7, #12]
|
|
800587e: 681b ldr r3, [r3, #0]
|
|
8005880: 4a35 ldr r2, [pc, #212] @ (8005958 <UART_SetConfig+0x2dc>)
|
|
8005882: 4293 cmp r3, r2
|
|
8005884: d12a bne.n 80058dc <UART_SetConfig+0x260>
|
|
8005886: 4b30 ldr r3, [pc, #192] @ (8005948 <UART_SetConfig+0x2cc>)
|
|
8005888: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
800588c: f403 7340 and.w r3, r3, #768 @ 0x300
|
|
8005890: f5b3 7f40 cmp.w r3, #768 @ 0x300
|
|
8005894: d01a beq.n 80058cc <UART_SetConfig+0x250>
|
|
8005896: f5b3 7f40 cmp.w r3, #768 @ 0x300
|
|
800589a: d81b bhi.n 80058d4 <UART_SetConfig+0x258>
|
|
800589c: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
80058a0: d00c beq.n 80058bc <UART_SetConfig+0x240>
|
|
80058a2: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
80058a6: d815 bhi.n 80058d4 <UART_SetConfig+0x258>
|
|
80058a8: 2b00 cmp r3, #0
|
|
80058aa: d003 beq.n 80058b4 <UART_SetConfig+0x238>
|
|
80058ac: f5b3 7f80 cmp.w r3, #256 @ 0x100
|
|
80058b0: d008 beq.n 80058c4 <UART_SetConfig+0x248>
|
|
80058b2: e00f b.n 80058d4 <UART_SetConfig+0x258>
|
|
80058b4: 2300 movs r3, #0
|
|
80058b6: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80058ba: e052 b.n 8005962 <UART_SetConfig+0x2e6>
|
|
80058bc: 2302 movs r3, #2
|
|
80058be: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80058c2: e04e b.n 8005962 <UART_SetConfig+0x2e6>
|
|
80058c4: 2304 movs r3, #4
|
|
80058c6: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80058ca: e04a b.n 8005962 <UART_SetConfig+0x2e6>
|
|
80058cc: 2308 movs r3, #8
|
|
80058ce: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80058d2: e046 b.n 8005962 <UART_SetConfig+0x2e6>
|
|
80058d4: 2310 movs r3, #16
|
|
80058d6: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
80058da: e042 b.n 8005962 <UART_SetConfig+0x2e6>
|
|
80058dc: 68fb ldr r3, [r7, #12]
|
|
80058de: 681b ldr r3, [r3, #0]
|
|
80058e0: 4a17 ldr r2, [pc, #92] @ (8005940 <UART_SetConfig+0x2c4>)
|
|
80058e2: 4293 cmp r3, r2
|
|
80058e4: d13a bne.n 800595c <UART_SetConfig+0x2e0>
|
|
80058e6: 4b18 ldr r3, [pc, #96] @ (8005948 <UART_SetConfig+0x2cc>)
|
|
80058e8: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
|
|
80058ec: f403 6340 and.w r3, r3, #3072 @ 0xc00
|
|
80058f0: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
|
|
80058f4: d01a beq.n 800592c <UART_SetConfig+0x2b0>
|
|
80058f6: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
|
|
80058fa: d81b bhi.n 8005934 <UART_SetConfig+0x2b8>
|
|
80058fc: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
8005900: d00c beq.n 800591c <UART_SetConfig+0x2a0>
|
|
8005902: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
8005906: d815 bhi.n 8005934 <UART_SetConfig+0x2b8>
|
|
8005908: 2b00 cmp r3, #0
|
|
800590a: d003 beq.n 8005914 <UART_SetConfig+0x298>
|
|
800590c: f5b3 6f80 cmp.w r3, #1024 @ 0x400
|
|
8005910: d008 beq.n 8005924 <UART_SetConfig+0x2a8>
|
|
8005912: e00f b.n 8005934 <UART_SetConfig+0x2b8>
|
|
8005914: 2300 movs r3, #0
|
|
8005916: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800591a: e022 b.n 8005962 <UART_SetConfig+0x2e6>
|
|
800591c: 2302 movs r3, #2
|
|
800591e: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8005922: e01e b.n 8005962 <UART_SetConfig+0x2e6>
|
|
8005924: 2304 movs r3, #4
|
|
8005926: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800592a: e01a b.n 8005962 <UART_SetConfig+0x2e6>
|
|
800592c: 2308 movs r3, #8
|
|
800592e: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
8005932: e016 b.n 8005962 <UART_SetConfig+0x2e6>
|
|
8005934: 2310 movs r3, #16
|
|
8005936: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
800593a: e012 b.n 8005962 <UART_SetConfig+0x2e6>
|
|
800593c: efff69f3 .word 0xefff69f3
|
|
8005940: 40008000 .word 0x40008000
|
|
8005944: 40013800 .word 0x40013800
|
|
8005948: 40021000 .word 0x40021000
|
|
800594c: 40004400 .word 0x40004400
|
|
8005950: 40004800 .word 0x40004800
|
|
8005954: 40004c00 .word 0x40004c00
|
|
8005958: 40005000 .word 0x40005000
|
|
800595c: 2310 movs r3, #16
|
|
800595e: f887 3023 strb.w r3, [r7, #35] @ 0x23
|
|
|
|
/* Check LPUART instance */
|
|
if (UART_INSTANCE_LOWPOWER(huart))
|
|
8005962: 68fb ldr r3, [r7, #12]
|
|
8005964: 681b ldr r3, [r3, #0]
|
|
8005966: 4a9f ldr r2, [pc, #636] @ (8005be4 <UART_SetConfig+0x568>)
|
|
8005968: 4293 cmp r3, r2
|
|
800596a: d17a bne.n 8005a62 <UART_SetConfig+0x3e6>
|
|
{
|
|
/* Retrieve frequency clock */
|
|
switch (clocksource)
|
|
800596c: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
|
|
8005970: 2b08 cmp r3, #8
|
|
8005972: d824 bhi.n 80059be <UART_SetConfig+0x342>
|
|
8005974: a201 add r2, pc, #4 @ (adr r2, 800597c <UART_SetConfig+0x300>)
|
|
8005976: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
800597a: bf00 nop
|
|
800597c: 080059a1 .word 0x080059a1
|
|
8005980: 080059bf .word 0x080059bf
|
|
8005984: 080059a9 .word 0x080059a9
|
|
8005988: 080059bf .word 0x080059bf
|
|
800598c: 080059af .word 0x080059af
|
|
8005990: 080059bf .word 0x080059bf
|
|
8005994: 080059bf .word 0x080059bf
|
|
8005998: 080059bf .word 0x080059bf
|
|
800599c: 080059b7 .word 0x080059b7
|
|
{
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
80059a0: f7fe fcda bl 8004358 <HAL_RCC_GetPCLK1Freq>
|
|
80059a4: 61f8 str r0, [r7, #28]
|
|
break;
|
|
80059a6: e010 b.n 80059ca <UART_SetConfig+0x34e>
|
|
case UART_CLOCKSOURCE_HSI:
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
80059a8: 4b8f ldr r3, [pc, #572] @ (8005be8 <UART_SetConfig+0x56c>)
|
|
80059aa: 61fb str r3, [r7, #28]
|
|
break;
|
|
80059ac: e00d b.n 80059ca <UART_SetConfig+0x34e>
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
80059ae: f7fe fc3b bl 8004228 <HAL_RCC_GetSysClockFreq>
|
|
80059b2: 61f8 str r0, [r7, #28]
|
|
break;
|
|
80059b4: e009 b.n 80059ca <UART_SetConfig+0x34e>
|
|
case UART_CLOCKSOURCE_LSE:
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
80059b6: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
80059ba: 61fb str r3, [r7, #28]
|
|
break;
|
|
80059bc: e005 b.n 80059ca <UART_SetConfig+0x34e>
|
|
default:
|
|
pclk = 0U;
|
|
80059be: 2300 movs r3, #0
|
|
80059c0: 61fb str r3, [r7, #28]
|
|
ret = HAL_ERROR;
|
|
80059c2: 2301 movs r3, #1
|
|
80059c4: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
break;
|
|
80059c8: bf00 nop
|
|
}
|
|
|
|
/* If proper clock source reported */
|
|
if (pclk != 0U)
|
|
80059ca: 69fb ldr r3, [r7, #28]
|
|
80059cc: 2b00 cmp r3, #0
|
|
80059ce: f000 80fb beq.w 8005bc8 <UART_SetConfig+0x54c>
|
|
} /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
|
|
(lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
|
|
#else
|
|
/* No Prescaler applicable */
|
|
/* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
|
|
if ((pclk < (3U * huart->Init.BaudRate)) ||
|
|
80059d2: 68fb ldr r3, [r7, #12]
|
|
80059d4: 685a ldr r2, [r3, #4]
|
|
80059d6: 4613 mov r3, r2
|
|
80059d8: 005b lsls r3, r3, #1
|
|
80059da: 4413 add r3, r2
|
|
80059dc: 69fa ldr r2, [r7, #28]
|
|
80059de: 429a cmp r2, r3
|
|
80059e0: d305 bcc.n 80059ee <UART_SetConfig+0x372>
|
|
(pclk > (4096U * huart->Init.BaudRate)))
|
|
80059e2: 68fb ldr r3, [r7, #12]
|
|
80059e4: 685b ldr r3, [r3, #4]
|
|
80059e6: 031b lsls r3, r3, #12
|
|
if ((pclk < (3U * huart->Init.BaudRate)) ||
|
|
80059e8: 69fa ldr r2, [r7, #28]
|
|
80059ea: 429a cmp r2, r3
|
|
80059ec: d903 bls.n 80059f6 <UART_SetConfig+0x37a>
|
|
{
|
|
ret = HAL_ERROR;
|
|
80059ee: 2301 movs r3, #1
|
|
80059f0: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
80059f4: e0e8 b.n 8005bc8 <UART_SetConfig+0x54c>
|
|
}
|
|
else
|
|
{
|
|
usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate));
|
|
80059f6: 69fb ldr r3, [r7, #28]
|
|
80059f8: 2200 movs r2, #0
|
|
80059fa: 461c mov r4, r3
|
|
80059fc: 4615 mov r5, r2
|
|
80059fe: f04f 0200 mov.w r2, #0
|
|
8005a02: f04f 0300 mov.w r3, #0
|
|
8005a06: 022b lsls r3, r5, #8
|
|
8005a08: ea43 6314 orr.w r3, r3, r4, lsr #24
|
|
8005a0c: 0222 lsls r2, r4, #8
|
|
8005a0e: 68f9 ldr r1, [r7, #12]
|
|
8005a10: 6849 ldr r1, [r1, #4]
|
|
8005a12: 0849 lsrs r1, r1, #1
|
|
8005a14: 2000 movs r0, #0
|
|
8005a16: 4688 mov r8, r1
|
|
8005a18: 4681 mov r9, r0
|
|
8005a1a: eb12 0a08 adds.w sl, r2, r8
|
|
8005a1e: eb43 0b09 adc.w fp, r3, r9
|
|
8005a22: 68fb ldr r3, [r7, #12]
|
|
8005a24: 685b ldr r3, [r3, #4]
|
|
8005a26: 2200 movs r2, #0
|
|
8005a28: 603b str r3, [r7, #0]
|
|
8005a2a: 607a str r2, [r7, #4]
|
|
8005a2c: e9d7 2300 ldrd r2, r3, [r7]
|
|
8005a30: 4650 mov r0, sl
|
|
8005a32: 4659 mov r1, fp
|
|
8005a34: f7fb f908 bl 8000c48 <__aeabi_uldivmod>
|
|
8005a38: 4602 mov r2, r0
|
|
8005a3a: 460b mov r3, r1
|
|
8005a3c: 4613 mov r3, r2
|
|
8005a3e: 61bb str r3, [r7, #24]
|
|
if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
|
|
8005a40: 69bb ldr r3, [r7, #24]
|
|
8005a42: f5b3 7f40 cmp.w r3, #768 @ 0x300
|
|
8005a46: d308 bcc.n 8005a5a <UART_SetConfig+0x3de>
|
|
8005a48: 69bb ldr r3, [r7, #24]
|
|
8005a4a: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
8005a4e: d204 bcs.n 8005a5a <UART_SetConfig+0x3de>
|
|
{
|
|
huart->Instance->BRR = usartdiv;
|
|
8005a50: 68fb ldr r3, [r7, #12]
|
|
8005a52: 681b ldr r3, [r3, #0]
|
|
8005a54: 69ba ldr r2, [r7, #24]
|
|
8005a56: 60da str r2, [r3, #12]
|
|
8005a58: e0b6 b.n 8005bc8 <UART_SetConfig+0x54c>
|
|
}
|
|
else
|
|
{
|
|
ret = HAL_ERROR;
|
|
8005a5a: 2301 movs r3, #1
|
|
8005a5c: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
8005a60: e0b2 b.n 8005bc8 <UART_SetConfig+0x54c>
|
|
} /* if ( (pclk < (3 * huart->Init.BaudRate) ) || (pclk > (4096 * huart->Init.BaudRate) )) */
|
|
#endif /* USART_PRESC_PRESCALER */
|
|
} /* if (pclk != 0) */
|
|
}
|
|
/* Check UART Over Sampling to set Baud Rate Register */
|
|
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
|
|
8005a62: 68fb ldr r3, [r7, #12]
|
|
8005a64: 69db ldr r3, [r3, #28]
|
|
8005a66: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
|
|
8005a6a: d15e bne.n 8005b2a <UART_SetConfig+0x4ae>
|
|
{
|
|
switch (clocksource)
|
|
8005a6c: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
|
|
8005a70: 2b08 cmp r3, #8
|
|
8005a72: d828 bhi.n 8005ac6 <UART_SetConfig+0x44a>
|
|
8005a74: a201 add r2, pc, #4 @ (adr r2, 8005a7c <UART_SetConfig+0x400>)
|
|
8005a76: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8005a7a: bf00 nop
|
|
8005a7c: 08005aa1 .word 0x08005aa1
|
|
8005a80: 08005aa9 .word 0x08005aa9
|
|
8005a84: 08005ab1 .word 0x08005ab1
|
|
8005a88: 08005ac7 .word 0x08005ac7
|
|
8005a8c: 08005ab7 .word 0x08005ab7
|
|
8005a90: 08005ac7 .word 0x08005ac7
|
|
8005a94: 08005ac7 .word 0x08005ac7
|
|
8005a98: 08005ac7 .word 0x08005ac7
|
|
8005a9c: 08005abf .word 0x08005abf
|
|
{
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
8005aa0: f7fe fc5a bl 8004358 <HAL_RCC_GetPCLK1Freq>
|
|
8005aa4: 61f8 str r0, [r7, #28]
|
|
break;
|
|
8005aa6: e014 b.n 8005ad2 <UART_SetConfig+0x456>
|
|
case UART_CLOCKSOURCE_PCLK2:
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
8005aa8: f7fe fc6c bl 8004384 <HAL_RCC_GetPCLK2Freq>
|
|
8005aac: 61f8 str r0, [r7, #28]
|
|
break;
|
|
8005aae: e010 b.n 8005ad2 <UART_SetConfig+0x456>
|
|
case UART_CLOCKSOURCE_HSI:
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
8005ab0: 4b4d ldr r3, [pc, #308] @ (8005be8 <UART_SetConfig+0x56c>)
|
|
8005ab2: 61fb str r3, [r7, #28]
|
|
break;
|
|
8005ab4: e00d b.n 8005ad2 <UART_SetConfig+0x456>
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
8005ab6: f7fe fbb7 bl 8004228 <HAL_RCC_GetSysClockFreq>
|
|
8005aba: 61f8 str r0, [r7, #28]
|
|
break;
|
|
8005abc: e009 b.n 8005ad2 <UART_SetConfig+0x456>
|
|
case UART_CLOCKSOURCE_LSE:
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
8005abe: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
8005ac2: 61fb str r3, [r7, #28]
|
|
break;
|
|
8005ac4: e005 b.n 8005ad2 <UART_SetConfig+0x456>
|
|
default:
|
|
pclk = 0U;
|
|
8005ac6: 2300 movs r3, #0
|
|
8005ac8: 61fb str r3, [r7, #28]
|
|
ret = HAL_ERROR;
|
|
8005aca: 2301 movs r3, #1
|
|
8005acc: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
break;
|
|
8005ad0: bf00 nop
|
|
}
|
|
|
|
/* USARTDIV must be greater than or equal to 0d16 */
|
|
if (pclk != 0U)
|
|
8005ad2: 69fb ldr r3, [r7, #28]
|
|
8005ad4: 2b00 cmp r3, #0
|
|
8005ad6: d077 beq.n 8005bc8 <UART_SetConfig+0x54c>
|
|
{
|
|
#if defined(USART_PRESC_PRESCALER)
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
|
|
#else
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate));
|
|
8005ad8: 69fb ldr r3, [r7, #28]
|
|
8005ada: 005a lsls r2, r3, #1
|
|
8005adc: 68fb ldr r3, [r7, #12]
|
|
8005ade: 685b ldr r3, [r3, #4]
|
|
8005ae0: 085b lsrs r3, r3, #1
|
|
8005ae2: 441a add r2, r3
|
|
8005ae4: 68fb ldr r3, [r7, #12]
|
|
8005ae6: 685b ldr r3, [r3, #4]
|
|
8005ae8: fbb2 f3f3 udiv r3, r2, r3
|
|
8005aec: 61bb str r3, [r7, #24]
|
|
#endif /* USART_PRESC_PRESCALER */
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
|
8005aee: 69bb ldr r3, [r7, #24]
|
|
8005af0: 2b0f cmp r3, #15
|
|
8005af2: d916 bls.n 8005b22 <UART_SetConfig+0x4a6>
|
|
8005af4: 69bb ldr r3, [r7, #24]
|
|
8005af6: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8005afa: d212 bcs.n 8005b22 <UART_SetConfig+0x4a6>
|
|
{
|
|
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
|
|
8005afc: 69bb ldr r3, [r7, #24]
|
|
8005afe: b29b uxth r3, r3
|
|
8005b00: f023 030f bic.w r3, r3, #15
|
|
8005b04: 82fb strh r3, [r7, #22]
|
|
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
|
|
8005b06: 69bb ldr r3, [r7, #24]
|
|
8005b08: 085b lsrs r3, r3, #1
|
|
8005b0a: b29b uxth r3, r3
|
|
8005b0c: f003 0307 and.w r3, r3, #7
|
|
8005b10: b29a uxth r2, r3
|
|
8005b12: 8afb ldrh r3, [r7, #22]
|
|
8005b14: 4313 orrs r3, r2
|
|
8005b16: 82fb strh r3, [r7, #22]
|
|
huart->Instance->BRR = brrtemp;
|
|
8005b18: 68fb ldr r3, [r7, #12]
|
|
8005b1a: 681b ldr r3, [r3, #0]
|
|
8005b1c: 8afa ldrh r2, [r7, #22]
|
|
8005b1e: 60da str r2, [r3, #12]
|
|
8005b20: e052 b.n 8005bc8 <UART_SetConfig+0x54c>
|
|
}
|
|
else
|
|
{
|
|
ret = HAL_ERROR;
|
|
8005b22: 2301 movs r3, #1
|
|
8005b24: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
8005b28: e04e b.n 8005bc8 <UART_SetConfig+0x54c>
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
switch (clocksource)
|
|
8005b2a: f897 3023 ldrb.w r3, [r7, #35] @ 0x23
|
|
8005b2e: 2b08 cmp r3, #8
|
|
8005b30: d827 bhi.n 8005b82 <UART_SetConfig+0x506>
|
|
8005b32: a201 add r2, pc, #4 @ (adr r2, 8005b38 <UART_SetConfig+0x4bc>)
|
|
8005b34: f852 f023 ldr.w pc, [r2, r3, lsl #2]
|
|
8005b38: 08005b5d .word 0x08005b5d
|
|
8005b3c: 08005b65 .word 0x08005b65
|
|
8005b40: 08005b6d .word 0x08005b6d
|
|
8005b44: 08005b83 .word 0x08005b83
|
|
8005b48: 08005b73 .word 0x08005b73
|
|
8005b4c: 08005b83 .word 0x08005b83
|
|
8005b50: 08005b83 .word 0x08005b83
|
|
8005b54: 08005b83 .word 0x08005b83
|
|
8005b58: 08005b7b .word 0x08005b7b
|
|
{
|
|
case UART_CLOCKSOURCE_PCLK1:
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
8005b5c: f7fe fbfc bl 8004358 <HAL_RCC_GetPCLK1Freq>
|
|
8005b60: 61f8 str r0, [r7, #28]
|
|
break;
|
|
8005b62: e014 b.n 8005b8e <UART_SetConfig+0x512>
|
|
case UART_CLOCKSOURCE_PCLK2:
|
|
pclk = HAL_RCC_GetPCLK2Freq();
|
|
8005b64: f7fe fc0e bl 8004384 <HAL_RCC_GetPCLK2Freq>
|
|
8005b68: 61f8 str r0, [r7, #28]
|
|
break;
|
|
8005b6a: e010 b.n 8005b8e <UART_SetConfig+0x512>
|
|
case UART_CLOCKSOURCE_HSI:
|
|
pclk = (uint32_t) HSI_VALUE;
|
|
8005b6c: 4b1e ldr r3, [pc, #120] @ (8005be8 <UART_SetConfig+0x56c>)
|
|
8005b6e: 61fb str r3, [r7, #28]
|
|
break;
|
|
8005b70: e00d b.n 8005b8e <UART_SetConfig+0x512>
|
|
case UART_CLOCKSOURCE_SYSCLK:
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
8005b72: f7fe fb59 bl 8004228 <HAL_RCC_GetSysClockFreq>
|
|
8005b76: 61f8 str r0, [r7, #28]
|
|
break;
|
|
8005b78: e009 b.n 8005b8e <UART_SetConfig+0x512>
|
|
case UART_CLOCKSOURCE_LSE:
|
|
pclk = (uint32_t) LSE_VALUE;
|
|
8005b7a: f44f 4300 mov.w r3, #32768 @ 0x8000
|
|
8005b7e: 61fb str r3, [r7, #28]
|
|
break;
|
|
8005b80: e005 b.n 8005b8e <UART_SetConfig+0x512>
|
|
default:
|
|
pclk = 0U;
|
|
8005b82: 2300 movs r3, #0
|
|
8005b84: 61fb str r3, [r7, #28]
|
|
ret = HAL_ERROR;
|
|
8005b86: 2301 movs r3, #1
|
|
8005b88: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
break;
|
|
8005b8c: bf00 nop
|
|
}
|
|
|
|
if (pclk != 0U)
|
|
8005b8e: 69fb ldr r3, [r7, #28]
|
|
8005b90: 2b00 cmp r3, #0
|
|
8005b92: d019 beq.n 8005bc8 <UART_SetConfig+0x54c>
|
|
{
|
|
/* USARTDIV must be greater than or equal to 0d16 */
|
|
#if defined(USART_PRESC_PRESCALER)
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
|
|
#else
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate));
|
|
8005b94: 68fb ldr r3, [r7, #12]
|
|
8005b96: 685b ldr r3, [r3, #4]
|
|
8005b98: 085a lsrs r2, r3, #1
|
|
8005b9a: 69fb ldr r3, [r7, #28]
|
|
8005b9c: 441a add r2, r3
|
|
8005b9e: 68fb ldr r3, [r7, #12]
|
|
8005ba0: 685b ldr r3, [r3, #4]
|
|
8005ba2: fbb2 f3f3 udiv r3, r2, r3
|
|
8005ba6: 61bb str r3, [r7, #24]
|
|
#endif /* USART_PRESC_PRESCALER */
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
|
8005ba8: 69bb ldr r3, [r7, #24]
|
|
8005baa: 2b0f cmp r3, #15
|
|
8005bac: d909 bls.n 8005bc2 <UART_SetConfig+0x546>
|
|
8005bae: 69bb ldr r3, [r7, #24]
|
|
8005bb0: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
|
|
8005bb4: d205 bcs.n 8005bc2 <UART_SetConfig+0x546>
|
|
{
|
|
huart->Instance->BRR = (uint16_t)usartdiv;
|
|
8005bb6: 69bb ldr r3, [r7, #24]
|
|
8005bb8: b29a uxth r2, r3
|
|
8005bba: 68fb ldr r3, [r7, #12]
|
|
8005bbc: 681b ldr r3, [r3, #0]
|
|
8005bbe: 60da str r2, [r3, #12]
|
|
8005bc0: e002 b.n 8005bc8 <UART_SetConfig+0x54c>
|
|
}
|
|
else
|
|
{
|
|
ret = HAL_ERROR;
|
|
8005bc2: 2301 movs r3, #1
|
|
8005bc4: f887 3022 strb.w r3, [r7, #34] @ 0x22
|
|
huart->NbTxDataToProcess = 1;
|
|
huart->NbRxDataToProcess = 1;
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
|
/* Clear ISR function pointers */
|
|
huart->RxISR = NULL;
|
|
8005bc8: 68fb ldr r3, [r7, #12]
|
|
8005bca: 2200 movs r2, #0
|
|
8005bcc: 669a str r2, [r3, #104] @ 0x68
|
|
huart->TxISR = NULL;
|
|
8005bce: 68fb ldr r3, [r7, #12]
|
|
8005bd0: 2200 movs r2, #0
|
|
8005bd2: 66da str r2, [r3, #108] @ 0x6c
|
|
|
|
return ret;
|
|
8005bd4: f897 3022 ldrb.w r3, [r7, #34] @ 0x22
|
|
}
|
|
8005bd8: 4618 mov r0, r3
|
|
8005bda: 3728 adds r7, #40 @ 0x28
|
|
8005bdc: 46bd mov sp, r7
|
|
8005bde: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
|
|
8005be2: bf00 nop
|
|
8005be4: 40008000 .word 0x40008000
|
|
8005be8: 00f42400 .word 0x00f42400
|
|
|
|
08005bec <UART_AdvFeatureConfig>:
|
|
* @brief Configure the UART peripheral advanced features.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
|
|
{
|
|
8005bec: b480 push {r7}
|
|
8005bee: b083 sub sp, #12
|
|
8005bf0: af00 add r7, sp, #0
|
|
8005bf2: 6078 str r0, [r7, #4]
|
|
/* Check whether the set of advanced features to configure is properly set */
|
|
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
|
|
|
|
/* if required, configure RX/TX pins swap */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
|
|
8005bf4: 687b ldr r3, [r7, #4]
|
|
8005bf6: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8005bf8: f003 0308 and.w r3, r3, #8
|
|
8005bfc: 2b00 cmp r3, #0
|
|
8005bfe: d00a beq.n 8005c16 <UART_AdvFeatureConfig+0x2a>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
|
|
8005c00: 687b ldr r3, [r7, #4]
|
|
8005c02: 681b ldr r3, [r3, #0]
|
|
8005c04: 685b ldr r3, [r3, #4]
|
|
8005c06: f423 4100 bic.w r1, r3, #32768 @ 0x8000
|
|
8005c0a: 687b ldr r3, [r7, #4]
|
|
8005c0c: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
8005c0e: 687b ldr r3, [r7, #4]
|
|
8005c10: 681b ldr r3, [r3, #0]
|
|
8005c12: 430a orrs r2, r1
|
|
8005c14: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure TX pin active level inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
|
|
8005c16: 687b ldr r3, [r7, #4]
|
|
8005c18: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8005c1a: f003 0301 and.w r3, r3, #1
|
|
8005c1e: 2b00 cmp r3, #0
|
|
8005c20: d00a beq.n 8005c38 <UART_AdvFeatureConfig+0x4c>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
|
|
8005c22: 687b ldr r3, [r7, #4]
|
|
8005c24: 681b ldr r3, [r3, #0]
|
|
8005c26: 685b ldr r3, [r3, #4]
|
|
8005c28: f423 3100 bic.w r1, r3, #131072 @ 0x20000
|
|
8005c2c: 687b ldr r3, [r7, #4]
|
|
8005c2e: 6a9a ldr r2, [r3, #40] @ 0x28
|
|
8005c30: 687b ldr r3, [r7, #4]
|
|
8005c32: 681b ldr r3, [r3, #0]
|
|
8005c34: 430a orrs r2, r1
|
|
8005c36: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure RX pin active level inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
|
|
8005c38: 687b ldr r3, [r7, #4]
|
|
8005c3a: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8005c3c: f003 0302 and.w r3, r3, #2
|
|
8005c40: 2b00 cmp r3, #0
|
|
8005c42: d00a beq.n 8005c5a <UART_AdvFeatureConfig+0x6e>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
|
|
8005c44: 687b ldr r3, [r7, #4]
|
|
8005c46: 681b ldr r3, [r3, #0]
|
|
8005c48: 685b ldr r3, [r3, #4]
|
|
8005c4a: f423 3180 bic.w r1, r3, #65536 @ 0x10000
|
|
8005c4e: 687b ldr r3, [r7, #4]
|
|
8005c50: 6ada ldr r2, [r3, #44] @ 0x2c
|
|
8005c52: 687b ldr r3, [r7, #4]
|
|
8005c54: 681b ldr r3, [r3, #0]
|
|
8005c56: 430a orrs r2, r1
|
|
8005c58: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure data inversion */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
|
|
8005c5a: 687b ldr r3, [r7, #4]
|
|
8005c5c: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8005c5e: f003 0304 and.w r3, r3, #4
|
|
8005c62: 2b00 cmp r3, #0
|
|
8005c64: d00a beq.n 8005c7c <UART_AdvFeatureConfig+0x90>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
|
|
8005c66: 687b ldr r3, [r7, #4]
|
|
8005c68: 681b ldr r3, [r3, #0]
|
|
8005c6a: 685b ldr r3, [r3, #4]
|
|
8005c6c: f423 2180 bic.w r1, r3, #262144 @ 0x40000
|
|
8005c70: 687b ldr r3, [r7, #4]
|
|
8005c72: 6b1a ldr r2, [r3, #48] @ 0x30
|
|
8005c74: 687b ldr r3, [r7, #4]
|
|
8005c76: 681b ldr r3, [r3, #0]
|
|
8005c78: 430a orrs r2, r1
|
|
8005c7a: 605a str r2, [r3, #4]
|
|
}
|
|
|
|
/* if required, configure RX overrun detection disabling */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
|
|
8005c7c: 687b ldr r3, [r7, #4]
|
|
8005c7e: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8005c80: f003 0310 and.w r3, r3, #16
|
|
8005c84: 2b00 cmp r3, #0
|
|
8005c86: d00a beq.n 8005c9e <UART_AdvFeatureConfig+0xb2>
|
|
{
|
|
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
|
|
8005c88: 687b ldr r3, [r7, #4]
|
|
8005c8a: 681b ldr r3, [r3, #0]
|
|
8005c8c: 689b ldr r3, [r3, #8]
|
|
8005c8e: f423 5180 bic.w r1, r3, #4096 @ 0x1000
|
|
8005c92: 687b ldr r3, [r7, #4]
|
|
8005c94: 6b9a ldr r2, [r3, #56] @ 0x38
|
|
8005c96: 687b ldr r3, [r7, #4]
|
|
8005c98: 681b ldr r3, [r3, #0]
|
|
8005c9a: 430a orrs r2, r1
|
|
8005c9c: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* if required, configure DMA disabling on reception error */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
|
|
8005c9e: 687b ldr r3, [r7, #4]
|
|
8005ca0: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8005ca2: f003 0320 and.w r3, r3, #32
|
|
8005ca6: 2b00 cmp r3, #0
|
|
8005ca8: d00a beq.n 8005cc0 <UART_AdvFeatureConfig+0xd4>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
|
|
8005caa: 687b ldr r3, [r7, #4]
|
|
8005cac: 681b ldr r3, [r3, #0]
|
|
8005cae: 689b ldr r3, [r3, #8]
|
|
8005cb0: f423 5100 bic.w r1, r3, #8192 @ 0x2000
|
|
8005cb4: 687b ldr r3, [r7, #4]
|
|
8005cb6: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
8005cb8: 687b ldr r3, [r7, #4]
|
|
8005cba: 681b ldr r3, [r3, #0]
|
|
8005cbc: 430a orrs r2, r1
|
|
8005cbe: 609a str r2, [r3, #8]
|
|
}
|
|
|
|
/* if required, configure auto Baud rate detection scheme */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
|
|
8005cc0: 687b ldr r3, [r7, #4]
|
|
8005cc2: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8005cc4: f003 0340 and.w r3, r3, #64 @ 0x40
|
|
8005cc8: 2b00 cmp r3, #0
|
|
8005cca: d01a beq.n 8005d02 <UART_AdvFeatureConfig+0x116>
|
|
{
|
|
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
|
|
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
|
|
8005ccc: 687b ldr r3, [r7, #4]
|
|
8005cce: 681b ldr r3, [r3, #0]
|
|
8005cd0: 685b ldr r3, [r3, #4]
|
|
8005cd2: f423 1180 bic.w r1, r3, #1048576 @ 0x100000
|
|
8005cd6: 687b ldr r3, [r7, #4]
|
|
8005cd8: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
8005cda: 687b ldr r3, [r7, #4]
|
|
8005cdc: 681b ldr r3, [r3, #0]
|
|
8005cde: 430a orrs r2, r1
|
|
8005ce0: 605a str r2, [r3, #4]
|
|
/* set auto Baudrate detection parameters if detection is enabled */
|
|
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
|
|
8005ce2: 687b ldr r3, [r7, #4]
|
|
8005ce4: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8005ce6: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
|
|
8005cea: d10a bne.n 8005d02 <UART_AdvFeatureConfig+0x116>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
|
|
8005cec: 687b ldr r3, [r7, #4]
|
|
8005cee: 681b ldr r3, [r3, #0]
|
|
8005cf0: 685b ldr r3, [r3, #4]
|
|
8005cf2: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000
|
|
8005cf6: 687b ldr r3, [r7, #4]
|
|
8005cf8: 6c5a ldr r2, [r3, #68] @ 0x44
|
|
8005cfa: 687b ldr r3, [r7, #4]
|
|
8005cfc: 681b ldr r3, [r3, #0]
|
|
8005cfe: 430a orrs r2, r1
|
|
8005d00: 605a str r2, [r3, #4]
|
|
}
|
|
}
|
|
|
|
/* if required, configure MSB first on communication line */
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
|
|
8005d02: 687b ldr r3, [r7, #4]
|
|
8005d04: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
8005d06: f003 0380 and.w r3, r3, #128 @ 0x80
|
|
8005d0a: 2b00 cmp r3, #0
|
|
8005d0c: d00a beq.n 8005d24 <UART_AdvFeatureConfig+0x138>
|
|
{
|
|
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
|
|
8005d0e: 687b ldr r3, [r7, #4]
|
|
8005d10: 681b ldr r3, [r3, #0]
|
|
8005d12: 685b ldr r3, [r3, #4]
|
|
8005d14: f423 2100 bic.w r1, r3, #524288 @ 0x80000
|
|
8005d18: 687b ldr r3, [r7, #4]
|
|
8005d1a: 6c9a ldr r2, [r3, #72] @ 0x48
|
|
8005d1c: 687b ldr r3, [r7, #4]
|
|
8005d1e: 681b ldr r3, [r3, #0]
|
|
8005d20: 430a orrs r2, r1
|
|
8005d22: 605a str r2, [r3, #4]
|
|
}
|
|
}
|
|
8005d24: bf00 nop
|
|
8005d26: 370c adds r7, #12
|
|
8005d28: 46bd mov sp, r7
|
|
8005d2a: f85d 7b04 ldr.w r7, [sp], #4
|
|
8005d2e: 4770 bx lr
|
|
|
|
08005d30 <UART_CheckIdleState>:
|
|
* @brief Check the UART Idle State.
|
|
* @param huart UART handle.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
|
|
{
|
|
8005d30: b580 push {r7, lr}
|
|
8005d32: b098 sub sp, #96 @ 0x60
|
|
8005d34: af02 add r7, sp, #8
|
|
8005d36: 6078 str r0, [r7, #4]
|
|
uint32_t tickstart;
|
|
|
|
/* Initialize the UART ErrorCode */
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8005d38: 687b ldr r3, [r7, #4]
|
|
8005d3a: 2200 movs r2, #0
|
|
8005d3c: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
|
|
/* Init tickstart for timeout management */
|
|
tickstart = HAL_GetTick();
|
|
8005d40: f7fc fb8c bl 800245c <HAL_GetTick>
|
|
8005d44: 6578 str r0, [r7, #84] @ 0x54
|
|
|
|
/* Check if the Transmitter is enabled */
|
|
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
|
|
8005d46: 687b ldr r3, [r7, #4]
|
|
8005d48: 681b ldr r3, [r3, #0]
|
|
8005d4a: 681b ldr r3, [r3, #0]
|
|
8005d4c: f003 0308 and.w r3, r3, #8
|
|
8005d50: 2b08 cmp r3, #8
|
|
8005d52: d12e bne.n 8005db2 <UART_CheckIdleState+0x82>
|
|
{
|
|
/* Wait until TEACK flag is set */
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
|
8005d54: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
|
|
8005d58: 9300 str r3, [sp, #0]
|
|
8005d5a: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8005d5c: 2200 movs r2, #0
|
|
8005d5e: f44f 1100 mov.w r1, #2097152 @ 0x200000
|
|
8005d62: 6878 ldr r0, [r7, #4]
|
|
8005d64: f000 f88c bl 8005e80 <UART_WaitOnFlagUntilTimeout>
|
|
8005d68: 4603 mov r3, r0
|
|
8005d6a: 2b00 cmp r3, #0
|
|
8005d6c: d021 beq.n 8005db2 <UART_CheckIdleState+0x82>
|
|
{
|
|
/* Disable TXE interrupt for the interrupt process */
|
|
#if defined(USART_CR1_FIFOEN)
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
|
|
#else
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE));
|
|
8005d6e: 687b ldr r3, [r7, #4]
|
|
8005d70: 681b ldr r3, [r3, #0]
|
|
8005d72: 63bb str r3, [r7, #56] @ 0x38
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005d74: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8005d76: e853 3f00 ldrex r3, [r3]
|
|
8005d7a: 637b str r3, [r7, #52] @ 0x34
|
|
return(result);
|
|
8005d7c: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8005d7e: f023 0380 bic.w r3, r3, #128 @ 0x80
|
|
8005d82: 653b str r3, [r7, #80] @ 0x50
|
|
8005d84: 687b ldr r3, [r7, #4]
|
|
8005d86: 681b ldr r3, [r3, #0]
|
|
8005d88: 461a mov r2, r3
|
|
8005d8a: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
8005d8c: 647b str r3, [r7, #68] @ 0x44
|
|
8005d8e: 643a str r2, [r7, #64] @ 0x40
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005d90: 6c39 ldr r1, [r7, #64] @ 0x40
|
|
8005d92: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
8005d94: e841 2300 strex r3, r2, [r1]
|
|
8005d98: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
8005d9a: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
8005d9c: 2b00 cmp r3, #0
|
|
8005d9e: d1e6 bne.n 8005d6e <UART_CheckIdleState+0x3e>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8005da0: 687b ldr r3, [r7, #4]
|
|
8005da2: 2220 movs r2, #32
|
|
8005da4: 67da str r2, [r3, #124] @ 0x7c
|
|
|
|
__HAL_UNLOCK(huart);
|
|
8005da6: 687b ldr r3, [r7, #4]
|
|
8005da8: 2200 movs r2, #0
|
|
8005daa: f883 2078 strb.w r2, [r3, #120] @ 0x78
|
|
|
|
/* Timeout occurred */
|
|
return HAL_TIMEOUT;
|
|
8005dae: 2303 movs r3, #3
|
|
8005db0: e062 b.n 8005e78 <UART_CheckIdleState+0x148>
|
|
}
|
|
}
|
|
|
|
/* Check if the Receiver is enabled */
|
|
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
|
|
8005db2: 687b ldr r3, [r7, #4]
|
|
8005db4: 681b ldr r3, [r3, #0]
|
|
8005db6: 681b ldr r3, [r3, #0]
|
|
8005db8: f003 0304 and.w r3, r3, #4
|
|
8005dbc: 2b04 cmp r3, #4
|
|
8005dbe: d149 bne.n 8005e54 <UART_CheckIdleState+0x124>
|
|
{
|
|
/* Wait until REACK flag is set */
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
|
8005dc0: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
|
|
8005dc4: 9300 str r3, [sp, #0]
|
|
8005dc6: 6d7b ldr r3, [r7, #84] @ 0x54
|
|
8005dc8: 2200 movs r2, #0
|
|
8005dca: f44f 0180 mov.w r1, #4194304 @ 0x400000
|
|
8005dce: 6878 ldr r0, [r7, #4]
|
|
8005dd0: f000 f856 bl 8005e80 <UART_WaitOnFlagUntilTimeout>
|
|
8005dd4: 4603 mov r3, r0
|
|
8005dd6: 2b00 cmp r3, #0
|
|
8005dd8: d03c beq.n 8005e54 <UART_CheckIdleState+0x124>
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
|
|
interrupts for the interrupt process */
|
|
#if defined(USART_CR1_FIFOEN)
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
#else
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|
8005dda: 687b ldr r3, [r7, #4]
|
|
8005ddc: 681b ldr r3, [r3, #0]
|
|
8005dde: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005de0: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8005de2: e853 3f00 ldrex r3, [r3]
|
|
8005de6: 623b str r3, [r7, #32]
|
|
return(result);
|
|
8005de8: 6a3b ldr r3, [r7, #32]
|
|
8005dea: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
8005dee: 64fb str r3, [r7, #76] @ 0x4c
|
|
8005df0: 687b ldr r3, [r7, #4]
|
|
8005df2: 681b ldr r3, [r3, #0]
|
|
8005df4: 461a mov r2, r3
|
|
8005df6: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
8005df8: 633b str r3, [r7, #48] @ 0x30
|
|
8005dfa: 62fa str r2, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005dfc: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
8005dfe: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
8005e00: e841 2300 strex r3, r2, [r1]
|
|
8005e04: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
8005e06: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8005e08: 2b00 cmp r3, #0
|
|
8005e0a: d1e6 bne.n 8005dda <UART_CheckIdleState+0xaa>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8005e0c: 687b ldr r3, [r7, #4]
|
|
8005e0e: 681b ldr r3, [r3, #0]
|
|
8005e10: 3308 adds r3, #8
|
|
8005e12: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8005e14: 693b ldr r3, [r7, #16]
|
|
8005e16: e853 3f00 ldrex r3, [r3]
|
|
8005e1a: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
8005e1c: 68fb ldr r3, [r7, #12]
|
|
8005e1e: f023 0301 bic.w r3, r3, #1
|
|
8005e22: 64bb str r3, [r7, #72] @ 0x48
|
|
8005e24: 687b ldr r3, [r7, #4]
|
|
8005e26: 681b ldr r3, [r3, #0]
|
|
8005e28: 3308 adds r3, #8
|
|
8005e2a: 6cba ldr r2, [r7, #72] @ 0x48
|
|
8005e2c: 61fa str r2, [r7, #28]
|
|
8005e2e: 61bb str r3, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8005e30: 69b9 ldr r1, [r7, #24]
|
|
8005e32: 69fa ldr r2, [r7, #28]
|
|
8005e34: e841 2300 strex r3, r2, [r1]
|
|
8005e38: 617b str r3, [r7, #20]
|
|
return(result);
|
|
8005e3a: 697b ldr r3, [r7, #20]
|
|
8005e3c: 2b00 cmp r3, #0
|
|
8005e3e: d1e5 bne.n 8005e0c <UART_CheckIdleState+0xdc>
|
|
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8005e40: 687b ldr r3, [r7, #4]
|
|
8005e42: 2220 movs r2, #32
|
|
8005e44: f8c3 2080 str.w r2, [r3, #128] @ 0x80
|
|
|
|
__HAL_UNLOCK(huart);
|
|
8005e48: 687b ldr r3, [r7, #4]
|
|
8005e4a: 2200 movs r2, #0
|
|
8005e4c: f883 2078 strb.w r2, [r3, #120] @ 0x78
|
|
|
|
/* Timeout occurred */
|
|
return HAL_TIMEOUT;
|
|
8005e50: 2303 movs r3, #3
|
|
8005e52: e011 b.n 8005e78 <UART_CheckIdleState+0x148>
|
|
}
|
|
}
|
|
|
|
/* Initialize the UART State */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8005e54: 687b ldr r3, [r7, #4]
|
|
8005e56: 2220 movs r2, #32
|
|
8005e58: 67da str r2, [r3, #124] @ 0x7c
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8005e5a: 687b ldr r3, [r7, #4]
|
|
8005e5c: 2220 movs r2, #32
|
|
8005e5e: f8c3 2080 str.w r2, [r3, #128] @ 0x80
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8005e62: 687b ldr r3, [r7, #4]
|
|
8005e64: 2200 movs r2, #0
|
|
8005e66: 661a str r2, [r3, #96] @ 0x60
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
8005e68: 687b ldr r3, [r7, #4]
|
|
8005e6a: 2200 movs r2, #0
|
|
8005e6c: 665a str r2, [r3, #100] @ 0x64
|
|
|
|
__HAL_UNLOCK(huart);
|
|
8005e6e: 687b ldr r3, [r7, #4]
|
|
8005e70: 2200 movs r2, #0
|
|
8005e72: f883 2078 strb.w r2, [r3, #120] @ 0x78
|
|
|
|
return HAL_OK;
|
|
8005e76: 2300 movs r3, #0
|
|
}
|
|
8005e78: 4618 mov r0, r3
|
|
8005e7a: 3758 adds r7, #88 @ 0x58
|
|
8005e7c: 46bd mov sp, r7
|
|
8005e7e: bd80 pop {r7, pc}
|
|
|
|
08005e80 <UART_WaitOnFlagUntilTimeout>:
|
|
* @param Timeout Timeout duration
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
|
|
uint32_t Tickstart, uint32_t Timeout)
|
|
{
|
|
8005e80: b580 push {r7, lr}
|
|
8005e82: b084 sub sp, #16
|
|
8005e84: af00 add r7, sp, #0
|
|
8005e86: 60f8 str r0, [r7, #12]
|
|
8005e88: 60b9 str r1, [r7, #8]
|
|
8005e8a: 603b str r3, [r7, #0]
|
|
8005e8c: 4613 mov r3, r2
|
|
8005e8e: 71fb strb r3, [r7, #7]
|
|
/* Wait until flag is set */
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
8005e90: e04f b.n 8005f32 <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
/* Check for the Timeout */
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
8005e92: 69bb ldr r3, [r7, #24]
|
|
8005e94: f1b3 3fff cmp.w r3, #4294967295 @ 0xffffffff
|
|
8005e98: d04b beq.n 8005f32 <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
8005e9a: f7fc fadf bl 800245c <HAL_GetTick>
|
|
8005e9e: 4602 mov r2, r0
|
|
8005ea0: 683b ldr r3, [r7, #0]
|
|
8005ea2: 1ad3 subs r3, r2, r3
|
|
8005ea4: 69ba ldr r2, [r7, #24]
|
|
8005ea6: 429a cmp r2, r3
|
|
8005ea8: d302 bcc.n 8005eb0 <UART_WaitOnFlagUntilTimeout+0x30>
|
|
8005eaa: 69bb ldr r3, [r7, #24]
|
|
8005eac: 2b00 cmp r3, #0
|
|
8005eae: d101 bne.n 8005eb4 <UART_WaitOnFlagUntilTimeout+0x34>
|
|
{
|
|
|
|
return HAL_TIMEOUT;
|
|
8005eb0: 2303 movs r3, #3
|
|
8005eb2: e04e b.n 8005f52 <UART_WaitOnFlagUntilTimeout+0xd2>
|
|
}
|
|
|
|
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
|
|
8005eb4: 68fb ldr r3, [r7, #12]
|
|
8005eb6: 681b ldr r3, [r3, #0]
|
|
8005eb8: 681b ldr r3, [r3, #0]
|
|
8005eba: f003 0304 and.w r3, r3, #4
|
|
8005ebe: 2b00 cmp r3, #0
|
|
8005ec0: d037 beq.n 8005f32 <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
8005ec2: 68bb ldr r3, [r7, #8]
|
|
8005ec4: 2b80 cmp r3, #128 @ 0x80
|
|
8005ec6: d034 beq.n 8005f32 <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
8005ec8: 68bb ldr r3, [r7, #8]
|
|
8005eca: 2b40 cmp r3, #64 @ 0x40
|
|
8005ecc: d031 beq.n 8005f32 <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
|
|
8005ece: 68fb ldr r3, [r7, #12]
|
|
8005ed0: 681b ldr r3, [r3, #0]
|
|
8005ed2: 69db ldr r3, [r3, #28]
|
|
8005ed4: f003 0308 and.w r3, r3, #8
|
|
8005ed8: 2b08 cmp r3, #8
|
|
8005eda: d110 bne.n 8005efe <UART_WaitOnFlagUntilTimeout+0x7e>
|
|
{
|
|
/* Clear Overrun Error flag*/
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
|
|
8005edc: 68fb ldr r3, [r7, #12]
|
|
8005ede: 681b ldr r3, [r3, #0]
|
|
8005ee0: 2208 movs r2, #8
|
|
8005ee2: 621a str r2, [r3, #32]
|
|
|
|
/* Blocking error : transfer is aborted
|
|
Set the UART state ready to be able to start again the process,
|
|
Disable Rx Interrupts if ongoing */
|
|
UART_EndRxTransfer(huart);
|
|
8005ee4: 68f8 ldr r0, [r7, #12]
|
|
8005ee6: f000 f8ff bl 80060e8 <UART_EndRxTransfer>
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_ORE;
|
|
8005eea: 68fb ldr r3, [r7, #12]
|
|
8005eec: 2208 movs r2, #8
|
|
8005eee: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
8005ef2: 68fb ldr r3, [r7, #12]
|
|
8005ef4: 2200 movs r2, #0
|
|
8005ef6: f883 2078 strb.w r2, [r3, #120] @ 0x78
|
|
|
|
return HAL_ERROR;
|
|
8005efa: 2301 movs r3, #1
|
|
8005efc: e029 b.n 8005f52 <UART_WaitOnFlagUntilTimeout+0xd2>
|
|
}
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
|
|
8005efe: 68fb ldr r3, [r7, #12]
|
|
8005f00: 681b ldr r3, [r3, #0]
|
|
8005f02: 69db ldr r3, [r3, #28]
|
|
8005f04: f403 6300 and.w r3, r3, #2048 @ 0x800
|
|
8005f08: f5b3 6f00 cmp.w r3, #2048 @ 0x800
|
|
8005f0c: d111 bne.n 8005f32 <UART_WaitOnFlagUntilTimeout+0xb2>
|
|
{
|
|
/* Clear Receiver Timeout flag*/
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
|
|
8005f0e: 68fb ldr r3, [r7, #12]
|
|
8005f10: 681b ldr r3, [r3, #0]
|
|
8005f12: f44f 6200 mov.w r2, #2048 @ 0x800
|
|
8005f16: 621a str r2, [r3, #32]
|
|
|
|
/* Blocking error : transfer is aborted
|
|
Set the UART state ready to be able to start again the process,
|
|
Disable Rx Interrupts if ongoing */
|
|
UART_EndRxTransfer(huart);
|
|
8005f18: 68f8 ldr r0, [r7, #12]
|
|
8005f1a: f000 f8e5 bl 80060e8 <UART_EndRxTransfer>
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_RTO;
|
|
8005f1e: 68fb ldr r3, [r7, #12]
|
|
8005f20: 2220 movs r2, #32
|
|
8005f22: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
|
|
/* Process Unlocked */
|
|
__HAL_UNLOCK(huart);
|
|
8005f26: 68fb ldr r3, [r7, #12]
|
|
8005f28: 2200 movs r2, #0
|
|
8005f2a: f883 2078 strb.w r2, [r3, #120] @ 0x78
|
|
|
|
return HAL_TIMEOUT;
|
|
8005f2e: 2303 movs r3, #3
|
|
8005f30: e00f b.n 8005f52 <UART_WaitOnFlagUntilTimeout+0xd2>
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
8005f32: 68fb ldr r3, [r7, #12]
|
|
8005f34: 681b ldr r3, [r3, #0]
|
|
8005f36: 69da ldr r2, [r3, #28]
|
|
8005f38: 68bb ldr r3, [r7, #8]
|
|
8005f3a: 4013 ands r3, r2
|
|
8005f3c: 68ba ldr r2, [r7, #8]
|
|
8005f3e: 429a cmp r2, r3
|
|
8005f40: bf0c ite eq
|
|
8005f42: 2301 moveq r3, #1
|
|
8005f44: 2300 movne r3, #0
|
|
8005f46: b2db uxtb r3, r3
|
|
8005f48: 461a mov r2, r3
|
|
8005f4a: 79fb ldrb r3, [r7, #7]
|
|
8005f4c: 429a cmp r2, r3
|
|
8005f4e: d0a0 beq.n 8005e92 <UART_WaitOnFlagUntilTimeout+0x12>
|
|
}
|
|
}
|
|
}
|
|
}
|
|
return HAL_OK;
|
|
8005f50: 2300 movs r3, #0
|
|
}
|
|
8005f52: 4618 mov r0, r3
|
|
8005f54: 3710 adds r7, #16
|
|
8005f56: 46bd mov sp, r7
|
|
8005f58: bd80 pop {r7, pc}
|
|
...
|
|
|
|
08005f5c <UART_Start_Receive_IT>:
|
|
* @param pData Pointer to data buffer (u8 or u16 data elements).
|
|
* @param Size Amount of data elements (u8 or u16) to be received.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
|
|
{
|
|
8005f5c: b480 push {r7}
|
|
8005f5e: b097 sub sp, #92 @ 0x5c
|
|
8005f60: af00 add r7, sp, #0
|
|
8005f62: 60f8 str r0, [r7, #12]
|
|
8005f64: 60b9 str r1, [r7, #8]
|
|
8005f66: 4613 mov r3, r2
|
|
8005f68: 80fb strh r3, [r7, #6]
|
|
huart->pRxBuffPtr = pData;
|
|
8005f6a: 68fb ldr r3, [r7, #12]
|
|
8005f6c: 68ba ldr r2, [r7, #8]
|
|
8005f6e: 655a str r2, [r3, #84] @ 0x54
|
|
huart->RxXferSize = Size;
|
|
8005f70: 68fb ldr r3, [r7, #12]
|
|
8005f72: 88fa ldrh r2, [r7, #6]
|
|
8005f74: f8a3 2058 strh.w r2, [r3, #88] @ 0x58
|
|
huart->RxXferCount = Size;
|
|
8005f78: 68fb ldr r3, [r7, #12]
|
|
8005f7a: 88fa ldrh r2, [r7, #6]
|
|
8005f7c: f8a3 205a strh.w r2, [r3, #90] @ 0x5a
|
|
huart->RxISR = NULL;
|
|
8005f80: 68fb ldr r3, [r7, #12]
|
|
8005f82: 2200 movs r2, #0
|
|
8005f84: 669a str r2, [r3, #104] @ 0x68
|
|
|
|
/* Computation of UART mask to apply to RDR register */
|
|
UART_MASK_COMPUTATION(huart);
|
|
8005f86: 68fb ldr r3, [r7, #12]
|
|
8005f88: 689b ldr r3, [r3, #8]
|
|
8005f8a: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
8005f8e: d10e bne.n 8005fae <UART_Start_Receive_IT+0x52>
|
|
8005f90: 68fb ldr r3, [r7, #12]
|
|
8005f92: 691b ldr r3, [r3, #16]
|
|
8005f94: 2b00 cmp r3, #0
|
|
8005f96: d105 bne.n 8005fa4 <UART_Start_Receive_IT+0x48>
|
|
8005f98: 68fb ldr r3, [r7, #12]
|
|
8005f9a: f240 12ff movw r2, #511 @ 0x1ff
|
|
8005f9e: f8a3 205c strh.w r2, [r3, #92] @ 0x5c
|
|
8005fa2: e02d b.n 8006000 <UART_Start_Receive_IT+0xa4>
|
|
8005fa4: 68fb ldr r3, [r7, #12]
|
|
8005fa6: 22ff movs r2, #255 @ 0xff
|
|
8005fa8: f8a3 205c strh.w r2, [r3, #92] @ 0x5c
|
|
8005fac: e028 b.n 8006000 <UART_Start_Receive_IT+0xa4>
|
|
8005fae: 68fb ldr r3, [r7, #12]
|
|
8005fb0: 689b ldr r3, [r3, #8]
|
|
8005fb2: 2b00 cmp r3, #0
|
|
8005fb4: d10d bne.n 8005fd2 <UART_Start_Receive_IT+0x76>
|
|
8005fb6: 68fb ldr r3, [r7, #12]
|
|
8005fb8: 691b ldr r3, [r3, #16]
|
|
8005fba: 2b00 cmp r3, #0
|
|
8005fbc: d104 bne.n 8005fc8 <UART_Start_Receive_IT+0x6c>
|
|
8005fbe: 68fb ldr r3, [r7, #12]
|
|
8005fc0: 22ff movs r2, #255 @ 0xff
|
|
8005fc2: f8a3 205c strh.w r2, [r3, #92] @ 0x5c
|
|
8005fc6: e01b b.n 8006000 <UART_Start_Receive_IT+0xa4>
|
|
8005fc8: 68fb ldr r3, [r7, #12]
|
|
8005fca: 227f movs r2, #127 @ 0x7f
|
|
8005fcc: f8a3 205c strh.w r2, [r3, #92] @ 0x5c
|
|
8005fd0: e016 b.n 8006000 <UART_Start_Receive_IT+0xa4>
|
|
8005fd2: 68fb ldr r3, [r7, #12]
|
|
8005fd4: 689b ldr r3, [r3, #8]
|
|
8005fd6: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
|
|
8005fda: d10d bne.n 8005ff8 <UART_Start_Receive_IT+0x9c>
|
|
8005fdc: 68fb ldr r3, [r7, #12]
|
|
8005fde: 691b ldr r3, [r3, #16]
|
|
8005fe0: 2b00 cmp r3, #0
|
|
8005fe2: d104 bne.n 8005fee <UART_Start_Receive_IT+0x92>
|
|
8005fe4: 68fb ldr r3, [r7, #12]
|
|
8005fe6: 227f movs r2, #127 @ 0x7f
|
|
8005fe8: f8a3 205c strh.w r2, [r3, #92] @ 0x5c
|
|
8005fec: e008 b.n 8006000 <UART_Start_Receive_IT+0xa4>
|
|
8005fee: 68fb ldr r3, [r7, #12]
|
|
8005ff0: 223f movs r2, #63 @ 0x3f
|
|
8005ff2: f8a3 205c strh.w r2, [r3, #92] @ 0x5c
|
|
8005ff6: e003 b.n 8006000 <UART_Start_Receive_IT+0xa4>
|
|
8005ff8: 68fb ldr r3, [r7, #12]
|
|
8005ffa: 2200 movs r2, #0
|
|
8005ffc: f8a3 205c strh.w r2, [r3, #92] @ 0x5c
|
|
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8006000: 68fb ldr r3, [r7, #12]
|
|
8006002: 2200 movs r2, #0
|
|
8006004: f8c3 2084 str.w r2, [r3, #132] @ 0x84
|
|
huart->RxState = HAL_UART_STATE_BUSY_RX;
|
|
8006008: 68fb ldr r3, [r7, #12]
|
|
800600a: 2222 movs r2, #34 @ 0x22
|
|
800600c: f8c3 2080 str.w r2, [r3, #128] @ 0x80
|
|
|
|
/* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
|
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8006010: 68fb ldr r3, [r7, #12]
|
|
8006012: 681b ldr r3, [r3, #0]
|
|
8006014: 3308 adds r3, #8
|
|
8006016: 63fb str r3, [r7, #60] @ 0x3c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006018: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
800601a: e853 3f00 ldrex r3, [r3]
|
|
800601e: 63bb str r3, [r7, #56] @ 0x38
|
|
return(result);
|
|
8006020: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
8006022: f043 0301 orr.w r3, r3, #1
|
|
8006026: 657b str r3, [r7, #84] @ 0x54
|
|
8006028: 68fb ldr r3, [r7, #12]
|
|
800602a: 681b ldr r3, [r3, #0]
|
|
800602c: 3308 adds r3, #8
|
|
800602e: 6d7a ldr r2, [r7, #84] @ 0x54
|
|
8006030: 64ba str r2, [r7, #72] @ 0x48
|
|
8006032: 647b str r3, [r7, #68] @ 0x44
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006034: 6c79 ldr r1, [r7, #68] @ 0x44
|
|
8006036: 6cba ldr r2, [r7, #72] @ 0x48
|
|
8006038: e841 2300 strex r3, r2, [r1]
|
|
800603c: 643b str r3, [r7, #64] @ 0x40
|
|
return(result);
|
|
800603e: 6c3b ldr r3, [r7, #64] @ 0x40
|
|
8006040: 2b00 cmp r3, #0
|
|
8006042: d1e5 bne.n 8006010 <UART_Start_Receive_IT+0xb4>
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
|
|
}
|
|
}
|
|
#else
|
|
/* Set the Rx ISR function pointer according to the data word length */
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
8006044: 68fb ldr r3, [r7, #12]
|
|
8006046: 689b ldr r3, [r3, #8]
|
|
8006048: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
|
|
800604c: d107 bne.n 800605e <UART_Start_Receive_IT+0x102>
|
|
800604e: 68fb ldr r3, [r7, #12]
|
|
8006050: 691b ldr r3, [r3, #16]
|
|
8006052: 2b00 cmp r3, #0
|
|
8006054: d103 bne.n 800605e <UART_Start_Receive_IT+0x102>
|
|
{
|
|
huart->RxISR = UART_RxISR_16BIT;
|
|
8006056: 68fb ldr r3, [r7, #12]
|
|
8006058: 4a21 ldr r2, [pc, #132] @ (80060e0 <UART_Start_Receive_IT+0x184>)
|
|
800605a: 669a str r2, [r3, #104] @ 0x68
|
|
800605c: e002 b.n 8006064 <UART_Start_Receive_IT+0x108>
|
|
}
|
|
else
|
|
{
|
|
huart->RxISR = UART_RxISR_8BIT;
|
|
800605e: 68fb ldr r3, [r7, #12]
|
|
8006060: 4a20 ldr r2, [pc, #128] @ (80060e4 <UART_Start_Receive_IT+0x188>)
|
|
8006062: 669a str r2, [r3, #104] @ 0x68
|
|
}
|
|
|
|
/* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
|
|
if (huart->Init.Parity != UART_PARITY_NONE)
|
|
8006064: 68fb ldr r3, [r7, #12]
|
|
8006066: 691b ldr r3, [r3, #16]
|
|
8006068: 2b00 cmp r3, #0
|
|
800606a: d019 beq.n 80060a0 <UART_Start_Receive_IT+0x144>
|
|
{
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE);
|
|
800606c: 68fb ldr r3, [r7, #12]
|
|
800606e: 681b ldr r3, [r3, #0]
|
|
8006070: 62bb str r3, [r7, #40] @ 0x28
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006072: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8006074: e853 3f00 ldrex r3, [r3]
|
|
8006078: 627b str r3, [r7, #36] @ 0x24
|
|
return(result);
|
|
800607a: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
800607c: f443 7390 orr.w r3, r3, #288 @ 0x120
|
|
8006080: 64fb str r3, [r7, #76] @ 0x4c
|
|
8006082: 68fb ldr r3, [r7, #12]
|
|
8006084: 681b ldr r3, [r3, #0]
|
|
8006086: 461a mov r2, r3
|
|
8006088: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
800608a: 637b str r3, [r7, #52] @ 0x34
|
|
800608c: 633a str r2, [r7, #48] @ 0x30
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800608e: 6b39 ldr r1, [r7, #48] @ 0x30
|
|
8006090: 6b7a ldr r2, [r7, #52] @ 0x34
|
|
8006092: e841 2300 strex r3, r2, [r1]
|
|
8006096: 62fb str r3, [r7, #44] @ 0x2c
|
|
return(result);
|
|
8006098: 6afb ldr r3, [r7, #44] @ 0x2c
|
|
800609a: 2b00 cmp r3, #0
|
|
800609c: d1e6 bne.n 800606c <UART_Start_Receive_IT+0x110>
|
|
800609e: e018 b.n 80060d2 <UART_Start_Receive_IT+0x176>
|
|
}
|
|
else
|
|
{
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE);
|
|
80060a0: 68fb ldr r3, [r7, #12]
|
|
80060a2: 681b ldr r3, [r3, #0]
|
|
80060a4: 617b str r3, [r7, #20]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80060a6: 697b ldr r3, [r7, #20]
|
|
80060a8: e853 3f00 ldrex r3, [r3]
|
|
80060ac: 613b str r3, [r7, #16]
|
|
return(result);
|
|
80060ae: 693b ldr r3, [r7, #16]
|
|
80060b0: f043 0320 orr.w r3, r3, #32
|
|
80060b4: 653b str r3, [r7, #80] @ 0x50
|
|
80060b6: 68fb ldr r3, [r7, #12]
|
|
80060b8: 681b ldr r3, [r3, #0]
|
|
80060ba: 461a mov r2, r3
|
|
80060bc: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
80060be: 623b str r3, [r7, #32]
|
|
80060c0: 61fa str r2, [r7, #28]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80060c2: 69f9 ldr r1, [r7, #28]
|
|
80060c4: 6a3a ldr r2, [r7, #32]
|
|
80060c6: e841 2300 strex r3, r2, [r1]
|
|
80060ca: 61bb str r3, [r7, #24]
|
|
return(result);
|
|
80060cc: 69bb ldr r3, [r7, #24]
|
|
80060ce: 2b00 cmp r3, #0
|
|
80060d0: d1e6 bne.n 80060a0 <UART_Start_Receive_IT+0x144>
|
|
}
|
|
#endif /* USART_CR1_FIFOEN */
|
|
return HAL_OK;
|
|
80060d2: 2300 movs r3, #0
|
|
}
|
|
80060d4: 4618 mov r0, r3
|
|
80060d6: 375c adds r7, #92 @ 0x5c
|
|
80060d8: 46bd mov sp, r7
|
|
80060da: f85d 7b04 ldr.w r7, [sp], #4
|
|
80060de: 4770 bx lr
|
|
80060e0: 080063ed .word 0x080063ed
|
|
80060e4: 08006231 .word 0x08006231
|
|
|
|
080060e8 <UART_EndRxTransfer>:
|
|
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
|
|
{
|
|
80060e8: b480 push {r7}
|
|
80060ea: b095 sub sp, #84 @ 0x54
|
|
80060ec: af00 add r7, sp, #0
|
|
80060ee: 6078 str r0, [r7, #4]
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|
#if defined(USART_CR1_FIFOEN)
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
|
#else
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|
80060f0: 687b ldr r3, [r7, #4]
|
|
80060f2: 681b ldr r3, [r3, #0]
|
|
80060f4: 637b str r3, [r7, #52] @ 0x34
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80060f6: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
80060f8: e853 3f00 ldrex r3, [r3]
|
|
80060fc: 633b str r3, [r7, #48] @ 0x30
|
|
return(result);
|
|
80060fe: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8006100: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
8006104: 64fb str r3, [r7, #76] @ 0x4c
|
|
8006106: 687b ldr r3, [r7, #4]
|
|
8006108: 681b ldr r3, [r3, #0]
|
|
800610a: 461a mov r2, r3
|
|
800610c: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
800610e: 643b str r3, [r7, #64] @ 0x40
|
|
8006110: 63fa str r2, [r7, #60] @ 0x3c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006112: 6bf9 ldr r1, [r7, #60] @ 0x3c
|
|
8006114: 6c3a ldr r2, [r7, #64] @ 0x40
|
|
8006116: e841 2300 strex r3, r2, [r1]
|
|
800611a: 63bb str r3, [r7, #56] @ 0x38
|
|
return(result);
|
|
800611c: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
800611e: 2b00 cmp r3, #0
|
|
8006120: d1e6 bne.n 80060f0 <UART_EndRxTransfer+0x8>
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8006122: 687b ldr r3, [r7, #4]
|
|
8006124: 681b ldr r3, [r3, #0]
|
|
8006126: 3308 adds r3, #8
|
|
8006128: 623b str r3, [r7, #32]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800612a: 6a3b ldr r3, [r7, #32]
|
|
800612c: e853 3f00 ldrex r3, [r3]
|
|
8006130: 61fb str r3, [r7, #28]
|
|
return(result);
|
|
8006132: 69fb ldr r3, [r7, #28]
|
|
8006134: f023 0301 bic.w r3, r3, #1
|
|
8006138: 64bb str r3, [r7, #72] @ 0x48
|
|
800613a: 687b ldr r3, [r7, #4]
|
|
800613c: 681b ldr r3, [r3, #0]
|
|
800613e: 3308 adds r3, #8
|
|
8006140: 6cba ldr r2, [r7, #72] @ 0x48
|
|
8006142: 62fa str r2, [r7, #44] @ 0x2c
|
|
8006144: 62bb str r3, [r7, #40] @ 0x28
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006146: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
8006148: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
800614a: e841 2300 strex r3, r2, [r1]
|
|
800614e: 627b str r3, [r7, #36] @ 0x24
|
|
return(result);
|
|
8006150: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006152: 2b00 cmp r3, #0
|
|
8006154: d1e5 bne.n 8006122 <UART_EndRxTransfer+0x3a>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
|
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8006156: 687b ldr r3, [r7, #4]
|
|
8006158: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800615a: 2b01 cmp r3, #1
|
|
800615c: d118 bne.n 8006190 <UART_EndRxTransfer+0xa8>
|
|
{
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
800615e: 687b ldr r3, [r7, #4]
|
|
8006160: 681b ldr r3, [r3, #0]
|
|
8006162: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006164: 68fb ldr r3, [r7, #12]
|
|
8006166: e853 3f00 ldrex r3, [r3]
|
|
800616a: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
800616c: 68bb ldr r3, [r7, #8]
|
|
800616e: f023 0310 bic.w r3, r3, #16
|
|
8006172: 647b str r3, [r7, #68] @ 0x44
|
|
8006174: 687b ldr r3, [r7, #4]
|
|
8006176: 681b ldr r3, [r3, #0]
|
|
8006178: 461a mov r2, r3
|
|
800617a: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
800617c: 61bb str r3, [r7, #24]
|
|
800617e: 617a str r2, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006180: 6979 ldr r1, [r7, #20]
|
|
8006182: 69ba ldr r2, [r7, #24]
|
|
8006184: e841 2300 strex r3, r2, [r1]
|
|
8006188: 613b str r3, [r7, #16]
|
|
return(result);
|
|
800618a: 693b ldr r3, [r7, #16]
|
|
800618c: 2b00 cmp r3, #0
|
|
800618e: d1e6 bne.n 800615e <UART_EndRxTransfer+0x76>
|
|
}
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8006190: 687b ldr r3, [r7, #4]
|
|
8006192: 2220 movs r2, #32
|
|
8006194: f8c3 2080 str.w r2, [r3, #128] @ 0x80
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8006198: 687b ldr r3, [r7, #4]
|
|
800619a: 2200 movs r2, #0
|
|
800619c: 661a str r2, [r3, #96] @ 0x60
|
|
|
|
/* Reset RxIsr function pointer */
|
|
huart->RxISR = NULL;
|
|
800619e: 687b ldr r3, [r7, #4]
|
|
80061a0: 2200 movs r2, #0
|
|
80061a2: 669a str r2, [r3, #104] @ 0x68
|
|
}
|
|
80061a4: bf00 nop
|
|
80061a6: 3754 adds r7, #84 @ 0x54
|
|
80061a8: 46bd mov sp, r7
|
|
80061aa: f85d 7b04 ldr.w r7, [sp], #4
|
|
80061ae: 4770 bx lr
|
|
|
|
080061b0 <UART_DMAAbortOnError>:
|
|
* (To be called at end of DMA Abort procedure following error occurrence).
|
|
* @param hdma DMA handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
|
|
{
|
|
80061b0: b580 push {r7, lr}
|
|
80061b2: b084 sub sp, #16
|
|
80061b4: af00 add r7, sp, #0
|
|
80061b6: 6078 str r0, [r7, #4]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
|
|
80061b8: 687b ldr r3, [r7, #4]
|
|
80061ba: 6a9b ldr r3, [r3, #40] @ 0x28
|
|
80061bc: 60fb str r3, [r7, #12]
|
|
huart->RxXferCount = 0U;
|
|
80061be: 68fb ldr r3, [r7, #12]
|
|
80061c0: 2200 movs r2, #0
|
|
80061c2: f8a3 205a strh.w r2, [r3, #90] @ 0x5a
|
|
huart->TxXferCount = 0U;
|
|
80061c6: 68fb ldr r3, [r7, #12]
|
|
80061c8: 2200 movs r2, #0
|
|
80061ca: f8a3 2052 strh.w r2, [r3, #82] @ 0x52
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
80061ce: 68f8 ldr r0, [r7, #12]
|
|
80061d0: f7ff fa3e bl 8005650 <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
80061d4: bf00 nop
|
|
80061d6: 3710 adds r7, #16
|
|
80061d8: 46bd mov sp, r7
|
|
80061da: bd80 pop {r7, pc}
|
|
|
|
080061dc <UART_EndTransmit_IT>:
|
|
* @param huart pointer to a UART_HandleTypeDef structure that contains
|
|
* the configuration information for the specified UART module.
|
|
* @retval None
|
|
*/
|
|
static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
|
|
{
|
|
80061dc: b580 push {r7, lr}
|
|
80061de: b088 sub sp, #32
|
|
80061e0: af00 add r7, sp, #0
|
|
80061e2: 6078 str r0, [r7, #4]
|
|
/* Disable the UART Transmit Complete Interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
|
80061e4: 687b ldr r3, [r7, #4]
|
|
80061e6: 681b ldr r3, [r3, #0]
|
|
80061e8: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80061ea: 68fb ldr r3, [r7, #12]
|
|
80061ec: e853 3f00 ldrex r3, [r3]
|
|
80061f0: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
80061f2: 68bb ldr r3, [r7, #8]
|
|
80061f4: f023 0340 bic.w r3, r3, #64 @ 0x40
|
|
80061f8: 61fb str r3, [r7, #28]
|
|
80061fa: 687b ldr r3, [r7, #4]
|
|
80061fc: 681b ldr r3, [r3, #0]
|
|
80061fe: 461a mov r2, r3
|
|
8006200: 69fb ldr r3, [r7, #28]
|
|
8006202: 61bb str r3, [r7, #24]
|
|
8006204: 617a str r2, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006206: 6979 ldr r1, [r7, #20]
|
|
8006208: 69ba ldr r2, [r7, #24]
|
|
800620a: e841 2300 strex r3, r2, [r1]
|
|
800620e: 613b str r3, [r7, #16]
|
|
return(result);
|
|
8006210: 693b ldr r3, [r7, #16]
|
|
8006212: 2b00 cmp r3, #0
|
|
8006214: d1e6 bne.n 80061e4 <UART_EndTransmit_IT+0x8>
|
|
|
|
/* Tx process is ended, restore huart->gState to Ready */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8006216: 687b ldr r3, [r7, #4]
|
|
8006218: 2220 movs r2, #32
|
|
800621a: 67da str r2, [r3, #124] @ 0x7c
|
|
|
|
/* Cleat TxISR function pointer */
|
|
huart->TxISR = NULL;
|
|
800621c: 687b ldr r3, [r7, #4]
|
|
800621e: 2200 movs r2, #0
|
|
8006220: 66da str r2, [r3, #108] @ 0x6c
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Tx complete callback*/
|
|
huart->TxCpltCallback(huart);
|
|
#else
|
|
/*Call legacy weak Tx complete callback*/
|
|
HAL_UART_TxCpltCallback(huart);
|
|
8006222: 6878 ldr r0, [r7, #4]
|
|
8006224: f7ff fa0a bl 800563c <HAL_UART_TxCpltCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
8006228: bf00 nop
|
|
800622a: 3720 adds r7, #32
|
|
800622c: 46bd mov sp, r7
|
|
800622e: bd80 pop {r7, pc}
|
|
|
|
08006230 <UART_RxISR_8BIT>:
|
|
* @brief RX interrupt handler for 7 or 8 bits data word length .
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
|
|
{
|
|
8006230: b580 push {r7, lr}
|
|
8006232: b09c sub sp, #112 @ 0x70
|
|
8006234: af00 add r7, sp, #0
|
|
8006236: 6078 str r0, [r7, #4]
|
|
uint16_t uhMask = huart->Mask;
|
|
8006238: 687b ldr r3, [r7, #4]
|
|
800623a: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
|
|
800623e: f8a7 306e strh.w r3, [r7, #110] @ 0x6e
|
|
uint16_t uhdata;
|
|
|
|
/* Check that a Rx process is ongoing */
|
|
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
|
|
8006242: 687b ldr r3, [r7, #4]
|
|
8006244: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
8006248: 2b22 cmp r3, #34 @ 0x22
|
|
800624a: f040 80be bne.w 80063ca <UART_RxISR_8BIT+0x19a>
|
|
{
|
|
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
|
|
800624e: 687b ldr r3, [r7, #4]
|
|
8006250: 681b ldr r3, [r3, #0]
|
|
8006252: 8c9b ldrh r3, [r3, #36] @ 0x24
|
|
8006254: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
|
|
*huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
|
|
8006258: f8b7 306c ldrh.w r3, [r7, #108] @ 0x6c
|
|
800625c: b2d9 uxtb r1, r3
|
|
800625e: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e
|
|
8006262: b2da uxtb r2, r3
|
|
8006264: 687b ldr r3, [r7, #4]
|
|
8006266: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8006268: 400a ands r2, r1
|
|
800626a: b2d2 uxtb r2, r2
|
|
800626c: 701a strb r2, [r3, #0]
|
|
huart->pRxBuffPtr++;
|
|
800626e: 687b ldr r3, [r7, #4]
|
|
8006270: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8006272: 1c5a adds r2, r3, #1
|
|
8006274: 687b ldr r3, [r7, #4]
|
|
8006276: 655a str r2, [r3, #84] @ 0x54
|
|
huart->RxXferCount--;
|
|
8006278: 687b ldr r3, [r7, #4]
|
|
800627a: f8b3 305a ldrh.w r3, [r3, #90] @ 0x5a
|
|
800627e: b29b uxth r3, r3
|
|
8006280: 3b01 subs r3, #1
|
|
8006282: b29a uxth r2, r3
|
|
8006284: 687b ldr r3, [r7, #4]
|
|
8006286: f8a3 205a strh.w r2, [r3, #90] @ 0x5a
|
|
|
|
if (huart->RxXferCount == 0U)
|
|
800628a: 687b ldr r3, [r7, #4]
|
|
800628c: f8b3 305a ldrh.w r3, [r3, #90] @ 0x5a
|
|
8006290: b29b uxth r3, r3
|
|
8006292: 2b00 cmp r3, #0
|
|
8006294: f040 80a3 bne.w 80063de <UART_RxISR_8BIT+0x1ae>
|
|
{
|
|
/* Disable the UART Parity Error Interrupt and RXNE interrupts */
|
|
#if defined(USART_CR1_FIFOEN)
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
#else
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|
8006298: 687b ldr r3, [r7, #4]
|
|
800629a: 681b ldr r3, [r3, #0]
|
|
800629c: 64fb str r3, [r7, #76] @ 0x4c
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800629e: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
80062a0: e853 3f00 ldrex r3, [r3]
|
|
80062a4: 64bb str r3, [r7, #72] @ 0x48
|
|
return(result);
|
|
80062a6: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
80062a8: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
80062ac: 66bb str r3, [r7, #104] @ 0x68
|
|
80062ae: 687b ldr r3, [r7, #4]
|
|
80062b0: 681b ldr r3, [r3, #0]
|
|
80062b2: 461a mov r2, r3
|
|
80062b4: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
80062b6: 65bb str r3, [r7, #88] @ 0x58
|
|
80062b8: 657a str r2, [r7, #84] @ 0x54
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80062ba: 6d79 ldr r1, [r7, #84] @ 0x54
|
|
80062bc: 6dba ldr r2, [r7, #88] @ 0x58
|
|
80062be: e841 2300 strex r3, r2, [r1]
|
|
80062c2: 653b str r3, [r7, #80] @ 0x50
|
|
return(result);
|
|
80062c4: 6d3b ldr r3, [r7, #80] @ 0x50
|
|
80062c6: 2b00 cmp r3, #0
|
|
80062c8: d1e6 bne.n 8006298 <UART_RxISR_8BIT+0x68>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
|
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
80062ca: 687b ldr r3, [r7, #4]
|
|
80062cc: 681b ldr r3, [r3, #0]
|
|
80062ce: 3308 adds r3, #8
|
|
80062d0: 63bb str r3, [r7, #56] @ 0x38
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80062d2: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
80062d4: e853 3f00 ldrex r3, [r3]
|
|
80062d8: 637b str r3, [r7, #52] @ 0x34
|
|
return(result);
|
|
80062da: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
80062dc: f023 0301 bic.w r3, r3, #1
|
|
80062e0: 667b str r3, [r7, #100] @ 0x64
|
|
80062e2: 687b ldr r3, [r7, #4]
|
|
80062e4: 681b ldr r3, [r3, #0]
|
|
80062e6: 3308 adds r3, #8
|
|
80062e8: 6e7a ldr r2, [r7, #100] @ 0x64
|
|
80062ea: 647a str r2, [r7, #68] @ 0x44
|
|
80062ec: 643b str r3, [r7, #64] @ 0x40
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80062ee: 6c39 ldr r1, [r7, #64] @ 0x40
|
|
80062f0: 6c7a ldr r2, [r7, #68] @ 0x44
|
|
80062f2: e841 2300 strex r3, r2, [r1]
|
|
80062f6: 63fb str r3, [r7, #60] @ 0x3c
|
|
return(result);
|
|
80062f8: 6bfb ldr r3, [r7, #60] @ 0x3c
|
|
80062fa: 2b00 cmp r3, #0
|
|
80062fc: d1e5 bne.n 80062ca <UART_RxISR_8BIT+0x9a>
|
|
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
80062fe: 687b ldr r3, [r7, #4]
|
|
8006300: 2220 movs r2, #32
|
|
8006302: f8c3 2080 str.w r2, [r3, #128] @ 0x80
|
|
|
|
/* Clear RxISR function pointer */
|
|
huart->RxISR = NULL;
|
|
8006306: 687b ldr r3, [r7, #4]
|
|
8006308: 2200 movs r2, #0
|
|
800630a: 669a str r2, [r3, #104] @ 0x68
|
|
|
|
/* Initialize type of RxEvent to Transfer Complete */
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
800630c: 687b ldr r3, [r7, #4]
|
|
800630e: 2200 movs r2, #0
|
|
8006310: 665a str r2, [r3, #100] @ 0x64
|
|
|
|
if (!(IS_LPUART_INSTANCE(huart->Instance)))
|
|
8006312: 687b ldr r3, [r7, #4]
|
|
8006314: 681b ldr r3, [r3, #0]
|
|
8006316: 4a34 ldr r2, [pc, #208] @ (80063e8 <UART_RxISR_8BIT+0x1b8>)
|
|
8006318: 4293 cmp r3, r2
|
|
800631a: d01f beq.n 800635c <UART_RxISR_8BIT+0x12c>
|
|
{
|
|
/* Check that USART RTOEN bit is set */
|
|
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
|
|
800631c: 687b ldr r3, [r7, #4]
|
|
800631e: 681b ldr r3, [r3, #0]
|
|
8006320: 685b ldr r3, [r3, #4]
|
|
8006322: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
8006326: 2b00 cmp r3, #0
|
|
8006328: d018 beq.n 800635c <UART_RxISR_8BIT+0x12c>
|
|
{
|
|
/* Enable the UART Receiver Timeout Interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
|
|
800632a: 687b ldr r3, [r7, #4]
|
|
800632c: 681b ldr r3, [r3, #0]
|
|
800632e: 627b str r3, [r7, #36] @ 0x24
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006330: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006332: e853 3f00 ldrex r3, [r3]
|
|
8006336: 623b str r3, [r7, #32]
|
|
return(result);
|
|
8006338: 6a3b ldr r3, [r7, #32]
|
|
800633a: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
|
|
800633e: 663b str r3, [r7, #96] @ 0x60
|
|
8006340: 687b ldr r3, [r7, #4]
|
|
8006342: 681b ldr r3, [r3, #0]
|
|
8006344: 461a mov r2, r3
|
|
8006346: 6e3b ldr r3, [r7, #96] @ 0x60
|
|
8006348: 633b str r3, [r7, #48] @ 0x30
|
|
800634a: 62fa str r2, [r7, #44] @ 0x2c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800634c: 6af9 ldr r1, [r7, #44] @ 0x2c
|
|
800634e: 6b3a ldr r2, [r7, #48] @ 0x30
|
|
8006350: e841 2300 strex r3, r2, [r1]
|
|
8006354: 62bb str r3, [r7, #40] @ 0x28
|
|
return(result);
|
|
8006356: 6abb ldr r3, [r7, #40] @ 0x28
|
|
8006358: 2b00 cmp r3, #0
|
|
800635a: d1e6 bne.n 800632a <UART_RxISR_8BIT+0xfa>
|
|
}
|
|
}
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
800635c: 687b ldr r3, [r7, #4]
|
|
800635e: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
8006360: 2b01 cmp r3, #1
|
|
8006362: d12e bne.n 80063c2 <UART_RxISR_8BIT+0x192>
|
|
{
|
|
/* Set reception type to Standard */
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8006364: 687b ldr r3, [r7, #4]
|
|
8006366: 2200 movs r2, #0
|
|
8006368: 661a str r2, [r3, #96] @ 0x60
|
|
|
|
/* Disable IDLE interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
800636a: 687b ldr r3, [r7, #4]
|
|
800636c: 681b ldr r3, [r3, #0]
|
|
800636e: 613b str r3, [r7, #16]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
8006370: 693b ldr r3, [r7, #16]
|
|
8006372: e853 3f00 ldrex r3, [r3]
|
|
8006376: 60fb str r3, [r7, #12]
|
|
return(result);
|
|
8006378: 68fb ldr r3, [r7, #12]
|
|
800637a: f023 0310 bic.w r3, r3, #16
|
|
800637e: 65fb str r3, [r7, #92] @ 0x5c
|
|
8006380: 687b ldr r3, [r7, #4]
|
|
8006382: 681b ldr r3, [r3, #0]
|
|
8006384: 461a mov r2, r3
|
|
8006386: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
8006388: 61fb str r3, [r7, #28]
|
|
800638a: 61ba str r2, [r7, #24]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
800638c: 69b9 ldr r1, [r7, #24]
|
|
800638e: 69fa ldr r2, [r7, #28]
|
|
8006390: e841 2300 strex r3, r2, [r1]
|
|
8006394: 617b str r3, [r7, #20]
|
|
return(result);
|
|
8006396: 697b ldr r3, [r7, #20]
|
|
8006398: 2b00 cmp r3, #0
|
|
800639a: d1e6 bne.n 800636a <UART_RxISR_8BIT+0x13a>
|
|
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
|
|
800639c: 687b ldr r3, [r7, #4]
|
|
800639e: 681b ldr r3, [r3, #0]
|
|
80063a0: 69db ldr r3, [r3, #28]
|
|
80063a2: f003 0310 and.w r3, r3, #16
|
|
80063a6: 2b10 cmp r3, #16
|
|
80063a8: d103 bne.n 80063b2 <UART_RxISR_8BIT+0x182>
|
|
{
|
|
/* Clear IDLE Flag */
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
|
80063aa: 687b ldr r3, [r7, #4]
|
|
80063ac: 681b ldr r3, [r3, #0]
|
|
80063ae: 2210 movs r2, #16
|
|
80063b0: 621a str r2, [r3, #32]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, huart->RxXferSize);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
80063b2: 687b ldr r3, [r7, #4]
|
|
80063b4: f8b3 3058 ldrh.w r3, [r3, #88] @ 0x58
|
|
80063b8: 4619 mov r1, r3
|
|
80063ba: 6878 ldr r0, [r7, #4]
|
|
80063bc: f7ff f952 bl 8005664 <HAL_UARTEx_RxEventCallback>
|
|
else
|
|
{
|
|
/* Clear RXNE interrupt flag */
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
}
|
|
}
|
|
80063c0: e00d b.n 80063de <UART_RxISR_8BIT+0x1ae>
|
|
HAL_UART_RxCpltCallback(huart);
|
|
80063c2: 6878 ldr r0, [r7, #4]
|
|
80063c4: f7fb fa66 bl 8001894 <HAL_UART_RxCpltCallback>
|
|
}
|
|
80063c8: e009 b.n 80063de <UART_RxISR_8BIT+0x1ae>
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
80063ca: 687b ldr r3, [r7, #4]
|
|
80063cc: 681b ldr r3, [r3, #0]
|
|
80063ce: 8b1b ldrh r3, [r3, #24]
|
|
80063d0: b29a uxth r2, r3
|
|
80063d2: 687b ldr r3, [r7, #4]
|
|
80063d4: 681b ldr r3, [r3, #0]
|
|
80063d6: f042 0208 orr.w r2, r2, #8
|
|
80063da: b292 uxth r2, r2
|
|
80063dc: 831a strh r2, [r3, #24]
|
|
}
|
|
80063de: bf00 nop
|
|
80063e0: 3770 adds r7, #112 @ 0x70
|
|
80063e2: 46bd mov sp, r7
|
|
80063e4: bd80 pop {r7, pc}
|
|
80063e6: bf00 nop
|
|
80063e8: 40008000 .word 0x40008000
|
|
|
|
080063ec <UART_RxISR_16BIT>:
|
|
* interruptions have been enabled by HAL_UART_Receive_IT()
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
|
|
{
|
|
80063ec: b580 push {r7, lr}
|
|
80063ee: b09c sub sp, #112 @ 0x70
|
|
80063f0: af00 add r7, sp, #0
|
|
80063f2: 6078 str r0, [r7, #4]
|
|
uint16_t *tmp;
|
|
uint16_t uhMask = huart->Mask;
|
|
80063f4: 687b ldr r3, [r7, #4]
|
|
80063f6: f8b3 305c ldrh.w r3, [r3, #92] @ 0x5c
|
|
80063fa: f8a7 306e strh.w r3, [r7, #110] @ 0x6e
|
|
uint16_t uhdata;
|
|
|
|
/* Check that a Rx process is ongoing */
|
|
if (huart->RxState == HAL_UART_STATE_BUSY_RX)
|
|
80063fe: 687b ldr r3, [r7, #4]
|
|
8006400: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
|
|
8006404: 2b22 cmp r3, #34 @ 0x22
|
|
8006406: f040 80be bne.w 8006586 <UART_RxISR_16BIT+0x19a>
|
|
{
|
|
uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
|
|
800640a: 687b ldr r3, [r7, #4]
|
|
800640c: 681b ldr r3, [r3, #0]
|
|
800640e: 8c9b ldrh r3, [r3, #36] @ 0x24
|
|
8006410: f8a7 306c strh.w r3, [r7, #108] @ 0x6c
|
|
tmp = (uint16_t *) huart->pRxBuffPtr ;
|
|
8006414: 687b ldr r3, [r7, #4]
|
|
8006416: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8006418: 66bb str r3, [r7, #104] @ 0x68
|
|
*tmp = (uint16_t)(uhdata & uhMask);
|
|
800641a: f8b7 206c ldrh.w r2, [r7, #108] @ 0x6c
|
|
800641e: f8b7 306e ldrh.w r3, [r7, #110] @ 0x6e
|
|
8006422: 4013 ands r3, r2
|
|
8006424: b29a uxth r2, r3
|
|
8006426: 6ebb ldr r3, [r7, #104] @ 0x68
|
|
8006428: 801a strh r2, [r3, #0]
|
|
huart->pRxBuffPtr += 2U;
|
|
800642a: 687b ldr r3, [r7, #4]
|
|
800642c: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
800642e: 1c9a adds r2, r3, #2
|
|
8006430: 687b ldr r3, [r7, #4]
|
|
8006432: 655a str r2, [r3, #84] @ 0x54
|
|
huart->RxXferCount--;
|
|
8006434: 687b ldr r3, [r7, #4]
|
|
8006436: f8b3 305a ldrh.w r3, [r3, #90] @ 0x5a
|
|
800643a: b29b uxth r3, r3
|
|
800643c: 3b01 subs r3, #1
|
|
800643e: b29a uxth r2, r3
|
|
8006440: 687b ldr r3, [r7, #4]
|
|
8006442: f8a3 205a strh.w r2, [r3, #90] @ 0x5a
|
|
|
|
if (huart->RxXferCount == 0U)
|
|
8006446: 687b ldr r3, [r7, #4]
|
|
8006448: f8b3 305a ldrh.w r3, [r3, #90] @ 0x5a
|
|
800644c: b29b uxth r3, r3
|
|
800644e: 2b00 cmp r3, #0
|
|
8006450: f040 80a3 bne.w 800659a <UART_RxISR_16BIT+0x1ae>
|
|
{
|
|
/* Disable the UART Parity Error Interrupt and RXNE interrupt*/
|
|
#if defined(USART_CR1_FIFOEN)
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
#else
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE | USART_CR1_PEIE));
|
|
8006454: 687b ldr r3, [r7, #4]
|
|
8006456: 681b ldr r3, [r3, #0]
|
|
8006458: 64bb str r3, [r7, #72] @ 0x48
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800645a: 6cbb ldr r3, [r7, #72] @ 0x48
|
|
800645c: e853 3f00 ldrex r3, [r3]
|
|
8006460: 647b str r3, [r7, #68] @ 0x44
|
|
return(result);
|
|
8006462: 6c7b ldr r3, [r7, #68] @ 0x44
|
|
8006464: f423 7390 bic.w r3, r3, #288 @ 0x120
|
|
8006468: 667b str r3, [r7, #100] @ 0x64
|
|
800646a: 687b ldr r3, [r7, #4]
|
|
800646c: 681b ldr r3, [r3, #0]
|
|
800646e: 461a mov r2, r3
|
|
8006470: 6e7b ldr r3, [r7, #100] @ 0x64
|
|
8006472: 657b str r3, [r7, #84] @ 0x54
|
|
8006474: 653a str r2, [r7, #80] @ 0x50
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006476: 6d39 ldr r1, [r7, #80] @ 0x50
|
|
8006478: 6d7a ldr r2, [r7, #84] @ 0x54
|
|
800647a: e841 2300 strex r3, r2, [r1]
|
|
800647e: 64fb str r3, [r7, #76] @ 0x4c
|
|
return(result);
|
|
8006480: 6cfb ldr r3, [r7, #76] @ 0x4c
|
|
8006482: 2b00 cmp r3, #0
|
|
8006484: d1e6 bne.n 8006454 <UART_RxISR_16BIT+0x68>
|
|
#endif /* USART_CR1_FIFOEN */
|
|
|
|
/* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8006486: 687b ldr r3, [r7, #4]
|
|
8006488: 681b ldr r3, [r3, #0]
|
|
800648a: 3308 adds r3, #8
|
|
800648c: 637b str r3, [r7, #52] @ 0x34
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800648e: 6b7b ldr r3, [r7, #52] @ 0x34
|
|
8006490: e853 3f00 ldrex r3, [r3]
|
|
8006494: 633b str r3, [r7, #48] @ 0x30
|
|
return(result);
|
|
8006496: 6b3b ldr r3, [r7, #48] @ 0x30
|
|
8006498: f023 0301 bic.w r3, r3, #1
|
|
800649c: 663b str r3, [r7, #96] @ 0x60
|
|
800649e: 687b ldr r3, [r7, #4]
|
|
80064a0: 681b ldr r3, [r3, #0]
|
|
80064a2: 3308 adds r3, #8
|
|
80064a4: 6e3a ldr r2, [r7, #96] @ 0x60
|
|
80064a6: 643a str r2, [r7, #64] @ 0x40
|
|
80064a8: 63fb str r3, [r7, #60] @ 0x3c
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
80064aa: 6bf9 ldr r1, [r7, #60] @ 0x3c
|
|
80064ac: 6c3a ldr r2, [r7, #64] @ 0x40
|
|
80064ae: e841 2300 strex r3, r2, [r1]
|
|
80064b2: 63bb str r3, [r7, #56] @ 0x38
|
|
return(result);
|
|
80064b4: 6bbb ldr r3, [r7, #56] @ 0x38
|
|
80064b6: 2b00 cmp r3, #0
|
|
80064b8: d1e5 bne.n 8006486 <UART_RxISR_16BIT+0x9a>
|
|
|
|
/* Rx process is completed, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
80064ba: 687b ldr r3, [r7, #4]
|
|
80064bc: 2220 movs r2, #32
|
|
80064be: f8c3 2080 str.w r2, [r3, #128] @ 0x80
|
|
|
|
/* Clear RxISR function pointer */
|
|
huart->RxISR = NULL;
|
|
80064c2: 687b ldr r3, [r7, #4]
|
|
80064c4: 2200 movs r2, #0
|
|
80064c6: 669a str r2, [r3, #104] @ 0x68
|
|
|
|
/* Initialize type of RxEvent to Transfer Complete */
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
80064c8: 687b ldr r3, [r7, #4]
|
|
80064ca: 2200 movs r2, #0
|
|
80064cc: 665a str r2, [r3, #100] @ 0x64
|
|
|
|
if (!(IS_LPUART_INSTANCE(huart->Instance)))
|
|
80064ce: 687b ldr r3, [r7, #4]
|
|
80064d0: 681b ldr r3, [r3, #0]
|
|
80064d2: 4a34 ldr r2, [pc, #208] @ (80065a4 <UART_RxISR_16BIT+0x1b8>)
|
|
80064d4: 4293 cmp r3, r2
|
|
80064d6: d01f beq.n 8006518 <UART_RxISR_16BIT+0x12c>
|
|
{
|
|
/* Check that USART RTOEN bit is set */
|
|
if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
|
|
80064d8: 687b ldr r3, [r7, #4]
|
|
80064da: 681b ldr r3, [r3, #0]
|
|
80064dc: 685b ldr r3, [r3, #4]
|
|
80064de: f403 0300 and.w r3, r3, #8388608 @ 0x800000
|
|
80064e2: 2b00 cmp r3, #0
|
|
80064e4: d018 beq.n 8006518 <UART_RxISR_16BIT+0x12c>
|
|
{
|
|
/* Enable the UART Receiver Timeout Interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
|
|
80064e6: 687b ldr r3, [r7, #4]
|
|
80064e8: 681b ldr r3, [r3, #0]
|
|
80064ea: 623b str r3, [r7, #32]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
80064ec: 6a3b ldr r3, [r7, #32]
|
|
80064ee: e853 3f00 ldrex r3, [r3]
|
|
80064f2: 61fb str r3, [r7, #28]
|
|
return(result);
|
|
80064f4: 69fb ldr r3, [r7, #28]
|
|
80064f6: f023 6380 bic.w r3, r3, #67108864 @ 0x4000000
|
|
80064fa: 65fb str r3, [r7, #92] @ 0x5c
|
|
80064fc: 687b ldr r3, [r7, #4]
|
|
80064fe: 681b ldr r3, [r3, #0]
|
|
8006500: 461a mov r2, r3
|
|
8006502: 6dfb ldr r3, [r7, #92] @ 0x5c
|
|
8006504: 62fb str r3, [r7, #44] @ 0x2c
|
|
8006506: 62ba str r2, [r7, #40] @ 0x28
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006508: 6ab9 ldr r1, [r7, #40] @ 0x28
|
|
800650a: 6afa ldr r2, [r7, #44] @ 0x2c
|
|
800650c: e841 2300 strex r3, r2, [r1]
|
|
8006510: 627b str r3, [r7, #36] @ 0x24
|
|
return(result);
|
|
8006512: 6a7b ldr r3, [r7, #36] @ 0x24
|
|
8006514: 2b00 cmp r3, #0
|
|
8006516: d1e6 bne.n 80064e6 <UART_RxISR_16BIT+0xfa>
|
|
}
|
|
}
|
|
|
|
/* Check current reception Mode :
|
|
If Reception till IDLE event has been selected : */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8006518: 687b ldr r3, [r7, #4]
|
|
800651a: 6e1b ldr r3, [r3, #96] @ 0x60
|
|
800651c: 2b01 cmp r3, #1
|
|
800651e: d12e bne.n 800657e <UART_RxISR_16BIT+0x192>
|
|
{
|
|
/* Set reception type to Standard */
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8006520: 687b ldr r3, [r7, #4]
|
|
8006522: 2200 movs r2, #0
|
|
8006524: 661a str r2, [r3, #96] @ 0x60
|
|
|
|
/* Disable IDLE interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8006526: 687b ldr r3, [r7, #4]
|
|
8006528: 681b ldr r3, [r3, #0]
|
|
800652a: 60fb str r3, [r7, #12]
|
|
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
|
|
800652c: 68fb ldr r3, [r7, #12]
|
|
800652e: e853 3f00 ldrex r3, [r3]
|
|
8006532: 60bb str r3, [r7, #8]
|
|
return(result);
|
|
8006534: 68bb ldr r3, [r7, #8]
|
|
8006536: f023 0310 bic.w r3, r3, #16
|
|
800653a: 65bb str r3, [r7, #88] @ 0x58
|
|
800653c: 687b ldr r3, [r7, #4]
|
|
800653e: 681b ldr r3, [r3, #0]
|
|
8006540: 461a mov r2, r3
|
|
8006542: 6dbb ldr r3, [r7, #88] @ 0x58
|
|
8006544: 61bb str r3, [r7, #24]
|
|
8006546: 617a str r2, [r7, #20]
|
|
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
|
|
8006548: 6979 ldr r1, [r7, #20]
|
|
800654a: 69ba ldr r2, [r7, #24]
|
|
800654c: e841 2300 strex r3, r2, [r1]
|
|
8006550: 613b str r3, [r7, #16]
|
|
return(result);
|
|
8006552: 693b ldr r3, [r7, #16]
|
|
8006554: 2b00 cmp r3, #0
|
|
8006556: d1e6 bne.n 8006526 <UART_RxISR_16BIT+0x13a>
|
|
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
|
|
8006558: 687b ldr r3, [r7, #4]
|
|
800655a: 681b ldr r3, [r3, #0]
|
|
800655c: 69db ldr r3, [r3, #28]
|
|
800655e: f003 0310 and.w r3, r3, #16
|
|
8006562: 2b10 cmp r3, #16
|
|
8006564: d103 bne.n 800656e <UART_RxISR_16BIT+0x182>
|
|
{
|
|
/* Clear IDLE Flag */
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
|
8006566: 687b ldr r3, [r7, #4]
|
|
8006568: 681b ldr r3, [r3, #0]
|
|
800656a: 2210 movs r2, #16
|
|
800656c: 621a str r2, [r3, #32]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Rx Event callback*/
|
|
huart->RxEventCallback(huart, huart->RxXferSize);
|
|
#else
|
|
/*Call legacy weak Rx Event callback*/
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
800656e: 687b ldr r3, [r7, #4]
|
|
8006570: f8b3 3058 ldrh.w r3, [r3, #88] @ 0x58
|
|
8006574: 4619 mov r1, r3
|
|
8006576: 6878 ldr r0, [r7, #4]
|
|
8006578: f7ff f874 bl 8005664 <HAL_UARTEx_RxEventCallback>
|
|
else
|
|
{
|
|
/* Clear RXNE interrupt flag */
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
}
|
|
}
|
|
800657c: e00d b.n 800659a <UART_RxISR_16BIT+0x1ae>
|
|
HAL_UART_RxCpltCallback(huart);
|
|
800657e: 6878 ldr r0, [r7, #4]
|
|
8006580: f7fb f988 bl 8001894 <HAL_UART_RxCpltCallback>
|
|
}
|
|
8006584: e009 b.n 800659a <UART_RxISR_16BIT+0x1ae>
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
8006586: 687b ldr r3, [r7, #4]
|
|
8006588: 681b ldr r3, [r3, #0]
|
|
800658a: 8b1b ldrh r3, [r3, #24]
|
|
800658c: b29a uxth r2, r3
|
|
800658e: 687b ldr r3, [r7, #4]
|
|
8006590: 681b ldr r3, [r3, #0]
|
|
8006592: f042 0208 orr.w r2, r2, #8
|
|
8006596: b292 uxth r2, r2
|
|
8006598: 831a strh r2, [r3, #24]
|
|
}
|
|
800659a: bf00 nop
|
|
800659c: 3770 adds r7, #112 @ 0x70
|
|
800659e: 46bd mov sp, r7
|
|
80065a0: bd80 pop {r7, pc}
|
|
80065a2: bf00 nop
|
|
80065a4: 40008000 .word 0x40008000
|
|
|
|
080065a8 <HAL_UARTEx_WakeupCallback>:
|
|
* @brief UART wakeup from Stop mode callback.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
|
|
{
|
|
80065a8: b480 push {r7}
|
|
80065aa: b083 sub sp, #12
|
|
80065ac: af00 add r7, sp, #0
|
|
80065ae: 6078 str r0, [r7, #4]
|
|
UNUSED(huart);
|
|
|
|
/* NOTE : This function should not be modified, when the callback is needed,
|
|
the HAL_UARTEx_WakeupCallback can be implemented in the user file.
|
|
*/
|
|
}
|
|
80065b0: bf00 nop
|
|
80065b2: 370c adds r7, #12
|
|
80065b4: 46bd mov sp, r7
|
|
80065b6: f85d 7b04 ldr.w r7, [sp], #4
|
|
80065ba: 4770 bx lr
|
|
|
|
080065bc <__cvt>:
|
|
80065bc: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
|
|
80065c0: ec57 6b10 vmov r6, r7, d0
|
|
80065c4: 2f00 cmp r7, #0
|
|
80065c6: 460c mov r4, r1
|
|
80065c8: 4619 mov r1, r3
|
|
80065ca: 463b mov r3, r7
|
|
80065cc: bfbb ittet lt
|
|
80065ce: f107 4300 addlt.w r3, r7, #2147483648 @ 0x80000000
|
|
80065d2: 461f movlt r7, r3
|
|
80065d4: 2300 movge r3, #0
|
|
80065d6: 232d movlt r3, #45 @ 0x2d
|
|
80065d8: 700b strb r3, [r1, #0]
|
|
80065da: 9b0d ldr r3, [sp, #52] @ 0x34
|
|
80065dc: f8dd a030 ldr.w sl, [sp, #48] @ 0x30
|
|
80065e0: 4691 mov r9, r2
|
|
80065e2: f023 0820 bic.w r8, r3, #32
|
|
80065e6: bfbc itt lt
|
|
80065e8: 4632 movlt r2, r6
|
|
80065ea: 4616 movlt r6, r2
|
|
80065ec: f1b8 0f46 cmp.w r8, #70 @ 0x46
|
|
80065f0: d005 beq.n 80065fe <__cvt+0x42>
|
|
80065f2: f1b8 0f45 cmp.w r8, #69 @ 0x45
|
|
80065f6: d100 bne.n 80065fa <__cvt+0x3e>
|
|
80065f8: 3401 adds r4, #1
|
|
80065fa: 2102 movs r1, #2
|
|
80065fc: e000 b.n 8006600 <__cvt+0x44>
|
|
80065fe: 2103 movs r1, #3
|
|
8006600: ab03 add r3, sp, #12
|
|
8006602: 9301 str r3, [sp, #4]
|
|
8006604: ab02 add r3, sp, #8
|
|
8006606: 9300 str r3, [sp, #0]
|
|
8006608: ec47 6b10 vmov d0, r6, r7
|
|
800660c: 4653 mov r3, sl
|
|
800660e: 4622 mov r2, r4
|
|
8006610: f000 fe6e bl 80072f0 <_dtoa_r>
|
|
8006614: f1b8 0f47 cmp.w r8, #71 @ 0x47
|
|
8006618: 4605 mov r5, r0
|
|
800661a: d119 bne.n 8006650 <__cvt+0x94>
|
|
800661c: f019 0f01 tst.w r9, #1
|
|
8006620: d00e beq.n 8006640 <__cvt+0x84>
|
|
8006622: eb00 0904 add.w r9, r0, r4
|
|
8006626: 2200 movs r2, #0
|
|
8006628: 2300 movs r3, #0
|
|
800662a: 4630 mov r0, r6
|
|
800662c: 4639 mov r1, r7
|
|
800662e: f7fa fa4b bl 8000ac8 <__aeabi_dcmpeq>
|
|
8006632: b108 cbz r0, 8006638 <__cvt+0x7c>
|
|
8006634: f8cd 900c str.w r9, [sp, #12]
|
|
8006638: 2230 movs r2, #48 @ 0x30
|
|
800663a: 9b03 ldr r3, [sp, #12]
|
|
800663c: 454b cmp r3, r9
|
|
800663e: d31e bcc.n 800667e <__cvt+0xc2>
|
|
8006640: 9b03 ldr r3, [sp, #12]
|
|
8006642: 9a0e ldr r2, [sp, #56] @ 0x38
|
|
8006644: 1b5b subs r3, r3, r5
|
|
8006646: 4628 mov r0, r5
|
|
8006648: 6013 str r3, [r2, #0]
|
|
800664a: b004 add sp, #16
|
|
800664c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
8006650: f1b8 0f46 cmp.w r8, #70 @ 0x46
|
|
8006654: eb00 0904 add.w r9, r0, r4
|
|
8006658: d1e5 bne.n 8006626 <__cvt+0x6a>
|
|
800665a: 7803 ldrb r3, [r0, #0]
|
|
800665c: 2b30 cmp r3, #48 @ 0x30
|
|
800665e: d10a bne.n 8006676 <__cvt+0xba>
|
|
8006660: 2200 movs r2, #0
|
|
8006662: 2300 movs r3, #0
|
|
8006664: 4630 mov r0, r6
|
|
8006666: 4639 mov r1, r7
|
|
8006668: f7fa fa2e bl 8000ac8 <__aeabi_dcmpeq>
|
|
800666c: b918 cbnz r0, 8006676 <__cvt+0xba>
|
|
800666e: f1c4 0401 rsb r4, r4, #1
|
|
8006672: f8ca 4000 str.w r4, [sl]
|
|
8006676: f8da 3000 ldr.w r3, [sl]
|
|
800667a: 4499 add r9, r3
|
|
800667c: e7d3 b.n 8006626 <__cvt+0x6a>
|
|
800667e: 1c59 adds r1, r3, #1
|
|
8006680: 9103 str r1, [sp, #12]
|
|
8006682: 701a strb r2, [r3, #0]
|
|
8006684: e7d9 b.n 800663a <__cvt+0x7e>
|
|
|
|
08006686 <__exponent>:
|
|
8006686: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
|
|
8006688: 2900 cmp r1, #0
|
|
800668a: bfba itte lt
|
|
800668c: 4249 neglt r1, r1
|
|
800668e: 232d movlt r3, #45 @ 0x2d
|
|
8006690: 232b movge r3, #43 @ 0x2b
|
|
8006692: 2909 cmp r1, #9
|
|
8006694: 7002 strb r2, [r0, #0]
|
|
8006696: 7043 strb r3, [r0, #1]
|
|
8006698: dd29 ble.n 80066ee <__exponent+0x68>
|
|
800669a: f10d 0307 add.w r3, sp, #7
|
|
800669e: 461d mov r5, r3
|
|
80066a0: 270a movs r7, #10
|
|
80066a2: 461a mov r2, r3
|
|
80066a4: fbb1 f6f7 udiv r6, r1, r7
|
|
80066a8: fb07 1416 mls r4, r7, r6, r1
|
|
80066ac: 3430 adds r4, #48 @ 0x30
|
|
80066ae: f802 4c01 strb.w r4, [r2, #-1]
|
|
80066b2: 460c mov r4, r1
|
|
80066b4: 2c63 cmp r4, #99 @ 0x63
|
|
80066b6: f103 33ff add.w r3, r3, #4294967295 @ 0xffffffff
|
|
80066ba: 4631 mov r1, r6
|
|
80066bc: dcf1 bgt.n 80066a2 <__exponent+0x1c>
|
|
80066be: 3130 adds r1, #48 @ 0x30
|
|
80066c0: 1e94 subs r4, r2, #2
|
|
80066c2: f803 1c01 strb.w r1, [r3, #-1]
|
|
80066c6: 1c41 adds r1, r0, #1
|
|
80066c8: 4623 mov r3, r4
|
|
80066ca: 42ab cmp r3, r5
|
|
80066cc: d30a bcc.n 80066e4 <__exponent+0x5e>
|
|
80066ce: f10d 0309 add.w r3, sp, #9
|
|
80066d2: 1a9b subs r3, r3, r2
|
|
80066d4: 42ac cmp r4, r5
|
|
80066d6: bf88 it hi
|
|
80066d8: 2300 movhi r3, #0
|
|
80066da: 3302 adds r3, #2
|
|
80066dc: 4403 add r3, r0
|
|
80066de: 1a18 subs r0, r3, r0
|
|
80066e0: b003 add sp, #12
|
|
80066e2: bdf0 pop {r4, r5, r6, r7, pc}
|
|
80066e4: f813 6b01 ldrb.w r6, [r3], #1
|
|
80066e8: f801 6f01 strb.w r6, [r1, #1]!
|
|
80066ec: e7ed b.n 80066ca <__exponent+0x44>
|
|
80066ee: 2330 movs r3, #48 @ 0x30
|
|
80066f0: 3130 adds r1, #48 @ 0x30
|
|
80066f2: 7083 strb r3, [r0, #2]
|
|
80066f4: 70c1 strb r1, [r0, #3]
|
|
80066f6: 1d03 adds r3, r0, #4
|
|
80066f8: e7f1 b.n 80066de <__exponent+0x58>
|
|
...
|
|
|
|
080066fc <_printf_float>:
|
|
80066fc: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
8006700: b08d sub sp, #52 @ 0x34
|
|
8006702: 460c mov r4, r1
|
|
8006704: f8dd 8058 ldr.w r8, [sp, #88] @ 0x58
|
|
8006708: 4616 mov r6, r2
|
|
800670a: 461f mov r7, r3
|
|
800670c: 4605 mov r5, r0
|
|
800670e: f000 fced bl 80070ec <_localeconv_r>
|
|
8006712: 6803 ldr r3, [r0, #0]
|
|
8006714: 9304 str r3, [sp, #16]
|
|
8006716: 4618 mov r0, r3
|
|
8006718: f7f9 fdaa bl 8000270 <strlen>
|
|
800671c: 2300 movs r3, #0
|
|
800671e: 930a str r3, [sp, #40] @ 0x28
|
|
8006720: f8d8 3000 ldr.w r3, [r8]
|
|
8006724: 9005 str r0, [sp, #20]
|
|
8006726: 3307 adds r3, #7
|
|
8006728: f023 0307 bic.w r3, r3, #7
|
|
800672c: f103 0208 add.w r2, r3, #8
|
|
8006730: f894 a018 ldrb.w sl, [r4, #24]
|
|
8006734: f8d4 b000 ldr.w fp, [r4]
|
|
8006738: f8c8 2000 str.w r2, [r8]
|
|
800673c: e9d3 8900 ldrd r8, r9, [r3]
|
|
8006740: f029 4300 bic.w r3, r9, #2147483648 @ 0x80000000
|
|
8006744: 9307 str r3, [sp, #28]
|
|
8006746: f8cd 8018 str.w r8, [sp, #24]
|
|
800674a: e9c4 8912 strd r8, r9, [r4, #72] @ 0x48
|
|
800674e: e9dd 0106 ldrd r0, r1, [sp, #24]
|
|
8006752: 4b9c ldr r3, [pc, #624] @ (80069c4 <_printf_float+0x2c8>)
|
|
8006754: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8006758: f7fa f9e8 bl 8000b2c <__aeabi_dcmpun>
|
|
800675c: bb70 cbnz r0, 80067bc <_printf_float+0xc0>
|
|
800675e: e9dd 0106 ldrd r0, r1, [sp, #24]
|
|
8006762: 4b98 ldr r3, [pc, #608] @ (80069c4 <_printf_float+0x2c8>)
|
|
8006764: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8006768: f7fa f9c2 bl 8000af0 <__aeabi_dcmple>
|
|
800676c: bb30 cbnz r0, 80067bc <_printf_float+0xc0>
|
|
800676e: 2200 movs r2, #0
|
|
8006770: 2300 movs r3, #0
|
|
8006772: 4640 mov r0, r8
|
|
8006774: 4649 mov r1, r9
|
|
8006776: f7fa f9b1 bl 8000adc <__aeabi_dcmplt>
|
|
800677a: b110 cbz r0, 8006782 <_printf_float+0x86>
|
|
800677c: 232d movs r3, #45 @ 0x2d
|
|
800677e: f884 3043 strb.w r3, [r4, #67] @ 0x43
|
|
8006782: 4a91 ldr r2, [pc, #580] @ (80069c8 <_printf_float+0x2cc>)
|
|
8006784: 4b91 ldr r3, [pc, #580] @ (80069cc <_printf_float+0x2d0>)
|
|
8006786: f1ba 0f47 cmp.w sl, #71 @ 0x47
|
|
800678a: bf8c ite hi
|
|
800678c: 4690 movhi r8, r2
|
|
800678e: 4698 movls r8, r3
|
|
8006790: 2303 movs r3, #3
|
|
8006792: 6123 str r3, [r4, #16]
|
|
8006794: f02b 0304 bic.w r3, fp, #4
|
|
8006798: 6023 str r3, [r4, #0]
|
|
800679a: f04f 0900 mov.w r9, #0
|
|
800679e: 9700 str r7, [sp, #0]
|
|
80067a0: 4633 mov r3, r6
|
|
80067a2: aa0b add r2, sp, #44 @ 0x2c
|
|
80067a4: 4621 mov r1, r4
|
|
80067a6: 4628 mov r0, r5
|
|
80067a8: f000 f9d2 bl 8006b50 <_printf_common>
|
|
80067ac: 3001 adds r0, #1
|
|
80067ae: f040 808d bne.w 80068cc <_printf_float+0x1d0>
|
|
80067b2: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
80067b6: b00d add sp, #52 @ 0x34
|
|
80067b8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
80067bc: 4642 mov r2, r8
|
|
80067be: 464b mov r3, r9
|
|
80067c0: 4640 mov r0, r8
|
|
80067c2: 4649 mov r1, r9
|
|
80067c4: f7fa f9b2 bl 8000b2c <__aeabi_dcmpun>
|
|
80067c8: b140 cbz r0, 80067dc <_printf_float+0xe0>
|
|
80067ca: 464b mov r3, r9
|
|
80067cc: 2b00 cmp r3, #0
|
|
80067ce: bfbc itt lt
|
|
80067d0: 232d movlt r3, #45 @ 0x2d
|
|
80067d2: f884 3043 strblt.w r3, [r4, #67] @ 0x43
|
|
80067d6: 4a7e ldr r2, [pc, #504] @ (80069d0 <_printf_float+0x2d4>)
|
|
80067d8: 4b7e ldr r3, [pc, #504] @ (80069d4 <_printf_float+0x2d8>)
|
|
80067da: e7d4 b.n 8006786 <_printf_float+0x8a>
|
|
80067dc: 6863 ldr r3, [r4, #4]
|
|
80067de: f00a 02df and.w r2, sl, #223 @ 0xdf
|
|
80067e2: 9206 str r2, [sp, #24]
|
|
80067e4: 1c5a adds r2, r3, #1
|
|
80067e6: d13b bne.n 8006860 <_printf_float+0x164>
|
|
80067e8: 2306 movs r3, #6
|
|
80067ea: 6063 str r3, [r4, #4]
|
|
80067ec: f44b 6280 orr.w r2, fp, #1024 @ 0x400
|
|
80067f0: 2300 movs r3, #0
|
|
80067f2: 6022 str r2, [r4, #0]
|
|
80067f4: 9303 str r3, [sp, #12]
|
|
80067f6: ab0a add r3, sp, #40 @ 0x28
|
|
80067f8: e9cd a301 strd sl, r3, [sp, #4]
|
|
80067fc: ab09 add r3, sp, #36 @ 0x24
|
|
80067fe: 9300 str r3, [sp, #0]
|
|
8006800: 6861 ldr r1, [r4, #4]
|
|
8006802: ec49 8b10 vmov d0, r8, r9
|
|
8006806: f10d 0323 add.w r3, sp, #35 @ 0x23
|
|
800680a: 4628 mov r0, r5
|
|
800680c: f7ff fed6 bl 80065bc <__cvt>
|
|
8006810: 9b06 ldr r3, [sp, #24]
|
|
8006812: 9909 ldr r1, [sp, #36] @ 0x24
|
|
8006814: 2b47 cmp r3, #71 @ 0x47
|
|
8006816: 4680 mov r8, r0
|
|
8006818: d129 bne.n 800686e <_printf_float+0x172>
|
|
800681a: 1cc8 adds r0, r1, #3
|
|
800681c: db02 blt.n 8006824 <_printf_float+0x128>
|
|
800681e: 6863 ldr r3, [r4, #4]
|
|
8006820: 4299 cmp r1, r3
|
|
8006822: dd41 ble.n 80068a8 <_printf_float+0x1ac>
|
|
8006824: f1aa 0a02 sub.w sl, sl, #2
|
|
8006828: fa5f fa8a uxtb.w sl, sl
|
|
800682c: 3901 subs r1, #1
|
|
800682e: 4652 mov r2, sl
|
|
8006830: f104 0050 add.w r0, r4, #80 @ 0x50
|
|
8006834: 9109 str r1, [sp, #36] @ 0x24
|
|
8006836: f7ff ff26 bl 8006686 <__exponent>
|
|
800683a: 9a0a ldr r2, [sp, #40] @ 0x28
|
|
800683c: 1813 adds r3, r2, r0
|
|
800683e: 2a01 cmp r2, #1
|
|
8006840: 4681 mov r9, r0
|
|
8006842: 6123 str r3, [r4, #16]
|
|
8006844: dc02 bgt.n 800684c <_printf_float+0x150>
|
|
8006846: 6822 ldr r2, [r4, #0]
|
|
8006848: 07d2 lsls r2, r2, #31
|
|
800684a: d501 bpl.n 8006850 <_printf_float+0x154>
|
|
800684c: 3301 adds r3, #1
|
|
800684e: 6123 str r3, [r4, #16]
|
|
8006850: f89d 3023 ldrb.w r3, [sp, #35] @ 0x23
|
|
8006854: 2b00 cmp r3, #0
|
|
8006856: d0a2 beq.n 800679e <_printf_float+0xa2>
|
|
8006858: 232d movs r3, #45 @ 0x2d
|
|
800685a: f884 3043 strb.w r3, [r4, #67] @ 0x43
|
|
800685e: e79e b.n 800679e <_printf_float+0xa2>
|
|
8006860: 9a06 ldr r2, [sp, #24]
|
|
8006862: 2a47 cmp r2, #71 @ 0x47
|
|
8006864: d1c2 bne.n 80067ec <_printf_float+0xf0>
|
|
8006866: 2b00 cmp r3, #0
|
|
8006868: d1c0 bne.n 80067ec <_printf_float+0xf0>
|
|
800686a: 2301 movs r3, #1
|
|
800686c: e7bd b.n 80067ea <_printf_float+0xee>
|
|
800686e: f1ba 0f65 cmp.w sl, #101 @ 0x65
|
|
8006872: d9db bls.n 800682c <_printf_float+0x130>
|
|
8006874: f1ba 0f66 cmp.w sl, #102 @ 0x66
|
|
8006878: d118 bne.n 80068ac <_printf_float+0x1b0>
|
|
800687a: 2900 cmp r1, #0
|
|
800687c: 6863 ldr r3, [r4, #4]
|
|
800687e: dd0b ble.n 8006898 <_printf_float+0x19c>
|
|
8006880: 6121 str r1, [r4, #16]
|
|
8006882: b913 cbnz r3, 800688a <_printf_float+0x18e>
|
|
8006884: 6822 ldr r2, [r4, #0]
|
|
8006886: 07d0 lsls r0, r2, #31
|
|
8006888: d502 bpl.n 8006890 <_printf_float+0x194>
|
|
800688a: 3301 adds r3, #1
|
|
800688c: 440b add r3, r1
|
|
800688e: 6123 str r3, [r4, #16]
|
|
8006890: 65a1 str r1, [r4, #88] @ 0x58
|
|
8006892: f04f 0900 mov.w r9, #0
|
|
8006896: e7db b.n 8006850 <_printf_float+0x154>
|
|
8006898: b913 cbnz r3, 80068a0 <_printf_float+0x1a4>
|
|
800689a: 6822 ldr r2, [r4, #0]
|
|
800689c: 07d2 lsls r2, r2, #31
|
|
800689e: d501 bpl.n 80068a4 <_printf_float+0x1a8>
|
|
80068a0: 3302 adds r3, #2
|
|
80068a2: e7f4 b.n 800688e <_printf_float+0x192>
|
|
80068a4: 2301 movs r3, #1
|
|
80068a6: e7f2 b.n 800688e <_printf_float+0x192>
|
|
80068a8: f04f 0a67 mov.w sl, #103 @ 0x67
|
|
80068ac: 9b0a ldr r3, [sp, #40] @ 0x28
|
|
80068ae: 4299 cmp r1, r3
|
|
80068b0: db05 blt.n 80068be <_printf_float+0x1c2>
|
|
80068b2: 6823 ldr r3, [r4, #0]
|
|
80068b4: 6121 str r1, [r4, #16]
|
|
80068b6: 07d8 lsls r0, r3, #31
|
|
80068b8: d5ea bpl.n 8006890 <_printf_float+0x194>
|
|
80068ba: 1c4b adds r3, r1, #1
|
|
80068bc: e7e7 b.n 800688e <_printf_float+0x192>
|
|
80068be: 2900 cmp r1, #0
|
|
80068c0: bfd4 ite le
|
|
80068c2: f1c1 0202 rsble r2, r1, #2
|
|
80068c6: 2201 movgt r2, #1
|
|
80068c8: 4413 add r3, r2
|
|
80068ca: e7e0 b.n 800688e <_printf_float+0x192>
|
|
80068cc: 6823 ldr r3, [r4, #0]
|
|
80068ce: 055a lsls r2, r3, #21
|
|
80068d0: d407 bmi.n 80068e2 <_printf_float+0x1e6>
|
|
80068d2: 6923 ldr r3, [r4, #16]
|
|
80068d4: 4642 mov r2, r8
|
|
80068d6: 4631 mov r1, r6
|
|
80068d8: 4628 mov r0, r5
|
|
80068da: 47b8 blx r7
|
|
80068dc: 3001 adds r0, #1
|
|
80068de: d12b bne.n 8006938 <_printf_float+0x23c>
|
|
80068e0: e767 b.n 80067b2 <_printf_float+0xb6>
|
|
80068e2: f1ba 0f65 cmp.w sl, #101 @ 0x65
|
|
80068e6: f240 80dd bls.w 8006aa4 <_printf_float+0x3a8>
|
|
80068ea: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48
|
|
80068ee: 2200 movs r2, #0
|
|
80068f0: 2300 movs r3, #0
|
|
80068f2: f7fa f8e9 bl 8000ac8 <__aeabi_dcmpeq>
|
|
80068f6: 2800 cmp r0, #0
|
|
80068f8: d033 beq.n 8006962 <_printf_float+0x266>
|
|
80068fa: 4a37 ldr r2, [pc, #220] @ (80069d8 <_printf_float+0x2dc>)
|
|
80068fc: 2301 movs r3, #1
|
|
80068fe: 4631 mov r1, r6
|
|
8006900: 4628 mov r0, r5
|
|
8006902: 47b8 blx r7
|
|
8006904: 3001 adds r0, #1
|
|
8006906: f43f af54 beq.w 80067b2 <_printf_float+0xb6>
|
|
800690a: e9dd 3809 ldrd r3, r8, [sp, #36] @ 0x24
|
|
800690e: 4543 cmp r3, r8
|
|
8006910: db02 blt.n 8006918 <_printf_float+0x21c>
|
|
8006912: 6823 ldr r3, [r4, #0]
|
|
8006914: 07d8 lsls r0, r3, #31
|
|
8006916: d50f bpl.n 8006938 <_printf_float+0x23c>
|
|
8006918: e9dd 2304 ldrd r2, r3, [sp, #16]
|
|
800691c: 4631 mov r1, r6
|
|
800691e: 4628 mov r0, r5
|
|
8006920: 47b8 blx r7
|
|
8006922: 3001 adds r0, #1
|
|
8006924: f43f af45 beq.w 80067b2 <_printf_float+0xb6>
|
|
8006928: f04f 0900 mov.w r9, #0
|
|
800692c: f108 38ff add.w r8, r8, #4294967295 @ 0xffffffff
|
|
8006930: f104 0a1a add.w sl, r4, #26
|
|
8006934: 45c8 cmp r8, r9
|
|
8006936: dc09 bgt.n 800694c <_printf_float+0x250>
|
|
8006938: 6823 ldr r3, [r4, #0]
|
|
800693a: 079b lsls r3, r3, #30
|
|
800693c: f100 8103 bmi.w 8006b46 <_printf_float+0x44a>
|
|
8006940: 68e0 ldr r0, [r4, #12]
|
|
8006942: 9b0b ldr r3, [sp, #44] @ 0x2c
|
|
8006944: 4298 cmp r0, r3
|
|
8006946: bfb8 it lt
|
|
8006948: 4618 movlt r0, r3
|
|
800694a: e734 b.n 80067b6 <_printf_float+0xba>
|
|
800694c: 2301 movs r3, #1
|
|
800694e: 4652 mov r2, sl
|
|
8006950: 4631 mov r1, r6
|
|
8006952: 4628 mov r0, r5
|
|
8006954: 47b8 blx r7
|
|
8006956: 3001 adds r0, #1
|
|
8006958: f43f af2b beq.w 80067b2 <_printf_float+0xb6>
|
|
800695c: f109 0901 add.w r9, r9, #1
|
|
8006960: e7e8 b.n 8006934 <_printf_float+0x238>
|
|
8006962: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8006964: 2b00 cmp r3, #0
|
|
8006966: dc39 bgt.n 80069dc <_printf_float+0x2e0>
|
|
8006968: 4a1b ldr r2, [pc, #108] @ (80069d8 <_printf_float+0x2dc>)
|
|
800696a: 2301 movs r3, #1
|
|
800696c: 4631 mov r1, r6
|
|
800696e: 4628 mov r0, r5
|
|
8006970: 47b8 blx r7
|
|
8006972: 3001 adds r0, #1
|
|
8006974: f43f af1d beq.w 80067b2 <_printf_float+0xb6>
|
|
8006978: e9dd 3909 ldrd r3, r9, [sp, #36] @ 0x24
|
|
800697c: ea59 0303 orrs.w r3, r9, r3
|
|
8006980: d102 bne.n 8006988 <_printf_float+0x28c>
|
|
8006982: 6823 ldr r3, [r4, #0]
|
|
8006984: 07d9 lsls r1, r3, #31
|
|
8006986: d5d7 bpl.n 8006938 <_printf_float+0x23c>
|
|
8006988: e9dd 2304 ldrd r2, r3, [sp, #16]
|
|
800698c: 4631 mov r1, r6
|
|
800698e: 4628 mov r0, r5
|
|
8006990: 47b8 blx r7
|
|
8006992: 3001 adds r0, #1
|
|
8006994: f43f af0d beq.w 80067b2 <_printf_float+0xb6>
|
|
8006998: f04f 0a00 mov.w sl, #0
|
|
800699c: f104 0b1a add.w fp, r4, #26
|
|
80069a0: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
80069a2: 425b negs r3, r3
|
|
80069a4: 4553 cmp r3, sl
|
|
80069a6: dc01 bgt.n 80069ac <_printf_float+0x2b0>
|
|
80069a8: 464b mov r3, r9
|
|
80069aa: e793 b.n 80068d4 <_printf_float+0x1d8>
|
|
80069ac: 2301 movs r3, #1
|
|
80069ae: 465a mov r2, fp
|
|
80069b0: 4631 mov r1, r6
|
|
80069b2: 4628 mov r0, r5
|
|
80069b4: 47b8 blx r7
|
|
80069b6: 3001 adds r0, #1
|
|
80069b8: f43f aefb beq.w 80067b2 <_printf_float+0xb6>
|
|
80069bc: f10a 0a01 add.w sl, sl, #1
|
|
80069c0: e7ee b.n 80069a0 <_printf_float+0x2a4>
|
|
80069c2: bf00 nop
|
|
80069c4: 7fefffff .word 0x7fefffff
|
|
80069c8: 08009344 .word 0x08009344
|
|
80069cc: 08009340 .word 0x08009340
|
|
80069d0: 0800934c .word 0x0800934c
|
|
80069d4: 08009348 .word 0x08009348
|
|
80069d8: 08009350 .word 0x08009350
|
|
80069dc: 6da3 ldr r3, [r4, #88] @ 0x58
|
|
80069de: f8dd a028 ldr.w sl, [sp, #40] @ 0x28
|
|
80069e2: 4553 cmp r3, sl
|
|
80069e4: bfa8 it ge
|
|
80069e6: 4653 movge r3, sl
|
|
80069e8: 2b00 cmp r3, #0
|
|
80069ea: 4699 mov r9, r3
|
|
80069ec: dc36 bgt.n 8006a5c <_printf_float+0x360>
|
|
80069ee: f04f 0b00 mov.w fp, #0
|
|
80069f2: ea29 79e9 bic.w r9, r9, r9, asr #31
|
|
80069f6: f104 021a add.w r2, r4, #26
|
|
80069fa: 6da3 ldr r3, [r4, #88] @ 0x58
|
|
80069fc: 9306 str r3, [sp, #24]
|
|
80069fe: eba3 0309 sub.w r3, r3, r9
|
|
8006a02: 455b cmp r3, fp
|
|
8006a04: dc31 bgt.n 8006a6a <_printf_float+0x36e>
|
|
8006a06: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8006a08: 459a cmp sl, r3
|
|
8006a0a: dc3a bgt.n 8006a82 <_printf_float+0x386>
|
|
8006a0c: 6823 ldr r3, [r4, #0]
|
|
8006a0e: 07da lsls r2, r3, #31
|
|
8006a10: d437 bmi.n 8006a82 <_printf_float+0x386>
|
|
8006a12: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8006a14: ebaa 0903 sub.w r9, sl, r3
|
|
8006a18: 9b06 ldr r3, [sp, #24]
|
|
8006a1a: ebaa 0303 sub.w r3, sl, r3
|
|
8006a1e: 4599 cmp r9, r3
|
|
8006a20: bfa8 it ge
|
|
8006a22: 4699 movge r9, r3
|
|
8006a24: f1b9 0f00 cmp.w r9, #0
|
|
8006a28: dc33 bgt.n 8006a92 <_printf_float+0x396>
|
|
8006a2a: f04f 0800 mov.w r8, #0
|
|
8006a2e: ea29 79e9 bic.w r9, r9, r9, asr #31
|
|
8006a32: f104 0b1a add.w fp, r4, #26
|
|
8006a36: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8006a38: ebaa 0303 sub.w r3, sl, r3
|
|
8006a3c: eba3 0309 sub.w r3, r3, r9
|
|
8006a40: 4543 cmp r3, r8
|
|
8006a42: f77f af79 ble.w 8006938 <_printf_float+0x23c>
|
|
8006a46: 2301 movs r3, #1
|
|
8006a48: 465a mov r2, fp
|
|
8006a4a: 4631 mov r1, r6
|
|
8006a4c: 4628 mov r0, r5
|
|
8006a4e: 47b8 blx r7
|
|
8006a50: 3001 adds r0, #1
|
|
8006a52: f43f aeae beq.w 80067b2 <_printf_float+0xb6>
|
|
8006a56: f108 0801 add.w r8, r8, #1
|
|
8006a5a: e7ec b.n 8006a36 <_printf_float+0x33a>
|
|
8006a5c: 4642 mov r2, r8
|
|
8006a5e: 4631 mov r1, r6
|
|
8006a60: 4628 mov r0, r5
|
|
8006a62: 47b8 blx r7
|
|
8006a64: 3001 adds r0, #1
|
|
8006a66: d1c2 bne.n 80069ee <_printf_float+0x2f2>
|
|
8006a68: e6a3 b.n 80067b2 <_printf_float+0xb6>
|
|
8006a6a: 2301 movs r3, #1
|
|
8006a6c: 4631 mov r1, r6
|
|
8006a6e: 4628 mov r0, r5
|
|
8006a70: 9206 str r2, [sp, #24]
|
|
8006a72: 47b8 blx r7
|
|
8006a74: 3001 adds r0, #1
|
|
8006a76: f43f ae9c beq.w 80067b2 <_printf_float+0xb6>
|
|
8006a7a: 9a06 ldr r2, [sp, #24]
|
|
8006a7c: f10b 0b01 add.w fp, fp, #1
|
|
8006a80: e7bb b.n 80069fa <_printf_float+0x2fe>
|
|
8006a82: e9dd 2304 ldrd r2, r3, [sp, #16]
|
|
8006a86: 4631 mov r1, r6
|
|
8006a88: 4628 mov r0, r5
|
|
8006a8a: 47b8 blx r7
|
|
8006a8c: 3001 adds r0, #1
|
|
8006a8e: d1c0 bne.n 8006a12 <_printf_float+0x316>
|
|
8006a90: e68f b.n 80067b2 <_printf_float+0xb6>
|
|
8006a92: 9a06 ldr r2, [sp, #24]
|
|
8006a94: 464b mov r3, r9
|
|
8006a96: 4442 add r2, r8
|
|
8006a98: 4631 mov r1, r6
|
|
8006a9a: 4628 mov r0, r5
|
|
8006a9c: 47b8 blx r7
|
|
8006a9e: 3001 adds r0, #1
|
|
8006aa0: d1c3 bne.n 8006a2a <_printf_float+0x32e>
|
|
8006aa2: e686 b.n 80067b2 <_printf_float+0xb6>
|
|
8006aa4: f8dd a028 ldr.w sl, [sp, #40] @ 0x28
|
|
8006aa8: f1ba 0f01 cmp.w sl, #1
|
|
8006aac: dc01 bgt.n 8006ab2 <_printf_float+0x3b6>
|
|
8006aae: 07db lsls r3, r3, #31
|
|
8006ab0: d536 bpl.n 8006b20 <_printf_float+0x424>
|
|
8006ab2: 2301 movs r3, #1
|
|
8006ab4: 4642 mov r2, r8
|
|
8006ab6: 4631 mov r1, r6
|
|
8006ab8: 4628 mov r0, r5
|
|
8006aba: 47b8 blx r7
|
|
8006abc: 3001 adds r0, #1
|
|
8006abe: f43f ae78 beq.w 80067b2 <_printf_float+0xb6>
|
|
8006ac2: e9dd 2304 ldrd r2, r3, [sp, #16]
|
|
8006ac6: 4631 mov r1, r6
|
|
8006ac8: 4628 mov r0, r5
|
|
8006aca: 47b8 blx r7
|
|
8006acc: 3001 adds r0, #1
|
|
8006ace: f43f ae70 beq.w 80067b2 <_printf_float+0xb6>
|
|
8006ad2: e9d4 0112 ldrd r0, r1, [r4, #72] @ 0x48
|
|
8006ad6: 2200 movs r2, #0
|
|
8006ad8: 2300 movs r3, #0
|
|
8006ada: f10a 3aff add.w sl, sl, #4294967295 @ 0xffffffff
|
|
8006ade: f7f9 fff3 bl 8000ac8 <__aeabi_dcmpeq>
|
|
8006ae2: b9c0 cbnz r0, 8006b16 <_printf_float+0x41a>
|
|
8006ae4: 4653 mov r3, sl
|
|
8006ae6: f108 0201 add.w r2, r8, #1
|
|
8006aea: 4631 mov r1, r6
|
|
8006aec: 4628 mov r0, r5
|
|
8006aee: 47b8 blx r7
|
|
8006af0: 3001 adds r0, #1
|
|
8006af2: d10c bne.n 8006b0e <_printf_float+0x412>
|
|
8006af4: e65d b.n 80067b2 <_printf_float+0xb6>
|
|
8006af6: 2301 movs r3, #1
|
|
8006af8: 465a mov r2, fp
|
|
8006afa: 4631 mov r1, r6
|
|
8006afc: 4628 mov r0, r5
|
|
8006afe: 47b8 blx r7
|
|
8006b00: 3001 adds r0, #1
|
|
8006b02: f43f ae56 beq.w 80067b2 <_printf_float+0xb6>
|
|
8006b06: f108 0801 add.w r8, r8, #1
|
|
8006b0a: 45d0 cmp r8, sl
|
|
8006b0c: dbf3 blt.n 8006af6 <_printf_float+0x3fa>
|
|
8006b0e: 464b mov r3, r9
|
|
8006b10: f104 0250 add.w r2, r4, #80 @ 0x50
|
|
8006b14: e6df b.n 80068d6 <_printf_float+0x1da>
|
|
8006b16: f04f 0800 mov.w r8, #0
|
|
8006b1a: f104 0b1a add.w fp, r4, #26
|
|
8006b1e: e7f4 b.n 8006b0a <_printf_float+0x40e>
|
|
8006b20: 2301 movs r3, #1
|
|
8006b22: 4642 mov r2, r8
|
|
8006b24: e7e1 b.n 8006aea <_printf_float+0x3ee>
|
|
8006b26: 2301 movs r3, #1
|
|
8006b28: 464a mov r2, r9
|
|
8006b2a: 4631 mov r1, r6
|
|
8006b2c: 4628 mov r0, r5
|
|
8006b2e: 47b8 blx r7
|
|
8006b30: 3001 adds r0, #1
|
|
8006b32: f43f ae3e beq.w 80067b2 <_printf_float+0xb6>
|
|
8006b36: f108 0801 add.w r8, r8, #1
|
|
8006b3a: 68e3 ldr r3, [r4, #12]
|
|
8006b3c: 990b ldr r1, [sp, #44] @ 0x2c
|
|
8006b3e: 1a5b subs r3, r3, r1
|
|
8006b40: 4543 cmp r3, r8
|
|
8006b42: dcf0 bgt.n 8006b26 <_printf_float+0x42a>
|
|
8006b44: e6fc b.n 8006940 <_printf_float+0x244>
|
|
8006b46: f04f 0800 mov.w r8, #0
|
|
8006b4a: f104 0919 add.w r9, r4, #25
|
|
8006b4e: e7f4 b.n 8006b3a <_printf_float+0x43e>
|
|
|
|
08006b50 <_printf_common>:
|
|
8006b50: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
8006b54: 4616 mov r6, r2
|
|
8006b56: 4698 mov r8, r3
|
|
8006b58: 688a ldr r2, [r1, #8]
|
|
8006b5a: 690b ldr r3, [r1, #16]
|
|
8006b5c: f8dd 9020 ldr.w r9, [sp, #32]
|
|
8006b60: 4293 cmp r3, r2
|
|
8006b62: bfb8 it lt
|
|
8006b64: 4613 movlt r3, r2
|
|
8006b66: 6033 str r3, [r6, #0]
|
|
8006b68: f891 2043 ldrb.w r2, [r1, #67] @ 0x43
|
|
8006b6c: 4607 mov r7, r0
|
|
8006b6e: 460c mov r4, r1
|
|
8006b70: b10a cbz r2, 8006b76 <_printf_common+0x26>
|
|
8006b72: 3301 adds r3, #1
|
|
8006b74: 6033 str r3, [r6, #0]
|
|
8006b76: 6823 ldr r3, [r4, #0]
|
|
8006b78: 0699 lsls r1, r3, #26
|
|
8006b7a: bf42 ittt mi
|
|
8006b7c: 6833 ldrmi r3, [r6, #0]
|
|
8006b7e: 3302 addmi r3, #2
|
|
8006b80: 6033 strmi r3, [r6, #0]
|
|
8006b82: 6825 ldr r5, [r4, #0]
|
|
8006b84: f015 0506 ands.w r5, r5, #6
|
|
8006b88: d106 bne.n 8006b98 <_printf_common+0x48>
|
|
8006b8a: f104 0a19 add.w sl, r4, #25
|
|
8006b8e: 68e3 ldr r3, [r4, #12]
|
|
8006b90: 6832 ldr r2, [r6, #0]
|
|
8006b92: 1a9b subs r3, r3, r2
|
|
8006b94: 42ab cmp r3, r5
|
|
8006b96: dc26 bgt.n 8006be6 <_printf_common+0x96>
|
|
8006b98: f894 3043 ldrb.w r3, [r4, #67] @ 0x43
|
|
8006b9c: 6822 ldr r2, [r4, #0]
|
|
8006b9e: 3b00 subs r3, #0
|
|
8006ba0: bf18 it ne
|
|
8006ba2: 2301 movne r3, #1
|
|
8006ba4: 0692 lsls r2, r2, #26
|
|
8006ba6: d42b bmi.n 8006c00 <_printf_common+0xb0>
|
|
8006ba8: f104 0243 add.w r2, r4, #67 @ 0x43
|
|
8006bac: 4641 mov r1, r8
|
|
8006bae: 4638 mov r0, r7
|
|
8006bb0: 47c8 blx r9
|
|
8006bb2: 3001 adds r0, #1
|
|
8006bb4: d01e beq.n 8006bf4 <_printf_common+0xa4>
|
|
8006bb6: 6823 ldr r3, [r4, #0]
|
|
8006bb8: 6922 ldr r2, [r4, #16]
|
|
8006bba: f003 0306 and.w r3, r3, #6
|
|
8006bbe: 2b04 cmp r3, #4
|
|
8006bc0: bf02 ittt eq
|
|
8006bc2: 68e5 ldreq r5, [r4, #12]
|
|
8006bc4: 6833 ldreq r3, [r6, #0]
|
|
8006bc6: 1aed subeq r5, r5, r3
|
|
8006bc8: 68a3 ldr r3, [r4, #8]
|
|
8006bca: bf0c ite eq
|
|
8006bcc: ea25 75e5 biceq.w r5, r5, r5, asr #31
|
|
8006bd0: 2500 movne r5, #0
|
|
8006bd2: 4293 cmp r3, r2
|
|
8006bd4: bfc4 itt gt
|
|
8006bd6: 1a9b subgt r3, r3, r2
|
|
8006bd8: 18ed addgt r5, r5, r3
|
|
8006bda: 2600 movs r6, #0
|
|
8006bdc: 341a adds r4, #26
|
|
8006bde: 42b5 cmp r5, r6
|
|
8006be0: d11a bne.n 8006c18 <_printf_common+0xc8>
|
|
8006be2: 2000 movs r0, #0
|
|
8006be4: e008 b.n 8006bf8 <_printf_common+0xa8>
|
|
8006be6: 2301 movs r3, #1
|
|
8006be8: 4652 mov r2, sl
|
|
8006bea: 4641 mov r1, r8
|
|
8006bec: 4638 mov r0, r7
|
|
8006bee: 47c8 blx r9
|
|
8006bf0: 3001 adds r0, #1
|
|
8006bf2: d103 bne.n 8006bfc <_printf_common+0xac>
|
|
8006bf4: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8006bf8: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
8006bfc: 3501 adds r5, #1
|
|
8006bfe: e7c6 b.n 8006b8e <_printf_common+0x3e>
|
|
8006c00: 18e1 adds r1, r4, r3
|
|
8006c02: 1c5a adds r2, r3, #1
|
|
8006c04: 2030 movs r0, #48 @ 0x30
|
|
8006c06: f881 0043 strb.w r0, [r1, #67] @ 0x43
|
|
8006c0a: 4422 add r2, r4
|
|
8006c0c: f894 1045 ldrb.w r1, [r4, #69] @ 0x45
|
|
8006c10: f882 1043 strb.w r1, [r2, #67] @ 0x43
|
|
8006c14: 3302 adds r3, #2
|
|
8006c16: e7c7 b.n 8006ba8 <_printf_common+0x58>
|
|
8006c18: 2301 movs r3, #1
|
|
8006c1a: 4622 mov r2, r4
|
|
8006c1c: 4641 mov r1, r8
|
|
8006c1e: 4638 mov r0, r7
|
|
8006c20: 47c8 blx r9
|
|
8006c22: 3001 adds r0, #1
|
|
8006c24: d0e6 beq.n 8006bf4 <_printf_common+0xa4>
|
|
8006c26: 3601 adds r6, #1
|
|
8006c28: e7d9 b.n 8006bde <_printf_common+0x8e>
|
|
...
|
|
|
|
08006c2c <_printf_i>:
|
|
8006c2c: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr}
|
|
8006c30: 7e0f ldrb r7, [r1, #24]
|
|
8006c32: 9e0c ldr r6, [sp, #48] @ 0x30
|
|
8006c34: 2f78 cmp r7, #120 @ 0x78
|
|
8006c36: 4691 mov r9, r2
|
|
8006c38: 4680 mov r8, r0
|
|
8006c3a: 460c mov r4, r1
|
|
8006c3c: 469a mov sl, r3
|
|
8006c3e: f101 0243 add.w r2, r1, #67 @ 0x43
|
|
8006c42: d807 bhi.n 8006c54 <_printf_i+0x28>
|
|
8006c44: 2f62 cmp r7, #98 @ 0x62
|
|
8006c46: d80a bhi.n 8006c5e <_printf_i+0x32>
|
|
8006c48: 2f00 cmp r7, #0
|
|
8006c4a: f000 80d1 beq.w 8006df0 <_printf_i+0x1c4>
|
|
8006c4e: 2f58 cmp r7, #88 @ 0x58
|
|
8006c50: f000 80b8 beq.w 8006dc4 <_printf_i+0x198>
|
|
8006c54: f104 0642 add.w r6, r4, #66 @ 0x42
|
|
8006c58: f884 7042 strb.w r7, [r4, #66] @ 0x42
|
|
8006c5c: e03a b.n 8006cd4 <_printf_i+0xa8>
|
|
8006c5e: f1a7 0363 sub.w r3, r7, #99 @ 0x63
|
|
8006c62: 2b15 cmp r3, #21
|
|
8006c64: d8f6 bhi.n 8006c54 <_printf_i+0x28>
|
|
8006c66: a101 add r1, pc, #4 @ (adr r1, 8006c6c <_printf_i+0x40>)
|
|
8006c68: f851 f023 ldr.w pc, [r1, r3, lsl #2]
|
|
8006c6c: 08006cc5 .word 0x08006cc5
|
|
8006c70: 08006cd9 .word 0x08006cd9
|
|
8006c74: 08006c55 .word 0x08006c55
|
|
8006c78: 08006c55 .word 0x08006c55
|
|
8006c7c: 08006c55 .word 0x08006c55
|
|
8006c80: 08006c55 .word 0x08006c55
|
|
8006c84: 08006cd9 .word 0x08006cd9
|
|
8006c88: 08006c55 .word 0x08006c55
|
|
8006c8c: 08006c55 .word 0x08006c55
|
|
8006c90: 08006c55 .word 0x08006c55
|
|
8006c94: 08006c55 .word 0x08006c55
|
|
8006c98: 08006dd7 .word 0x08006dd7
|
|
8006c9c: 08006d03 .word 0x08006d03
|
|
8006ca0: 08006d91 .word 0x08006d91
|
|
8006ca4: 08006c55 .word 0x08006c55
|
|
8006ca8: 08006c55 .word 0x08006c55
|
|
8006cac: 08006df9 .word 0x08006df9
|
|
8006cb0: 08006c55 .word 0x08006c55
|
|
8006cb4: 08006d03 .word 0x08006d03
|
|
8006cb8: 08006c55 .word 0x08006c55
|
|
8006cbc: 08006c55 .word 0x08006c55
|
|
8006cc0: 08006d99 .word 0x08006d99
|
|
8006cc4: 6833 ldr r3, [r6, #0]
|
|
8006cc6: 1d1a adds r2, r3, #4
|
|
8006cc8: 681b ldr r3, [r3, #0]
|
|
8006cca: 6032 str r2, [r6, #0]
|
|
8006ccc: f104 0642 add.w r6, r4, #66 @ 0x42
|
|
8006cd0: f884 3042 strb.w r3, [r4, #66] @ 0x42
|
|
8006cd4: 2301 movs r3, #1
|
|
8006cd6: e09c b.n 8006e12 <_printf_i+0x1e6>
|
|
8006cd8: 6833 ldr r3, [r6, #0]
|
|
8006cda: 6820 ldr r0, [r4, #0]
|
|
8006cdc: 1d19 adds r1, r3, #4
|
|
8006cde: 6031 str r1, [r6, #0]
|
|
8006ce0: 0606 lsls r6, r0, #24
|
|
8006ce2: d501 bpl.n 8006ce8 <_printf_i+0xbc>
|
|
8006ce4: 681d ldr r5, [r3, #0]
|
|
8006ce6: e003 b.n 8006cf0 <_printf_i+0xc4>
|
|
8006ce8: 0645 lsls r5, r0, #25
|
|
8006cea: d5fb bpl.n 8006ce4 <_printf_i+0xb8>
|
|
8006cec: f9b3 5000 ldrsh.w r5, [r3]
|
|
8006cf0: 2d00 cmp r5, #0
|
|
8006cf2: da03 bge.n 8006cfc <_printf_i+0xd0>
|
|
8006cf4: 232d movs r3, #45 @ 0x2d
|
|
8006cf6: 426d negs r5, r5
|
|
8006cf8: f884 3043 strb.w r3, [r4, #67] @ 0x43
|
|
8006cfc: 4858 ldr r0, [pc, #352] @ (8006e60 <_printf_i+0x234>)
|
|
8006cfe: 230a movs r3, #10
|
|
8006d00: e011 b.n 8006d26 <_printf_i+0xfa>
|
|
8006d02: 6821 ldr r1, [r4, #0]
|
|
8006d04: 6833 ldr r3, [r6, #0]
|
|
8006d06: 0608 lsls r0, r1, #24
|
|
8006d08: f853 5b04 ldr.w r5, [r3], #4
|
|
8006d0c: d402 bmi.n 8006d14 <_printf_i+0xe8>
|
|
8006d0e: 0649 lsls r1, r1, #25
|
|
8006d10: bf48 it mi
|
|
8006d12: b2ad uxthmi r5, r5
|
|
8006d14: 2f6f cmp r7, #111 @ 0x6f
|
|
8006d16: 4852 ldr r0, [pc, #328] @ (8006e60 <_printf_i+0x234>)
|
|
8006d18: 6033 str r3, [r6, #0]
|
|
8006d1a: bf14 ite ne
|
|
8006d1c: 230a movne r3, #10
|
|
8006d1e: 2308 moveq r3, #8
|
|
8006d20: 2100 movs r1, #0
|
|
8006d22: f884 1043 strb.w r1, [r4, #67] @ 0x43
|
|
8006d26: 6866 ldr r6, [r4, #4]
|
|
8006d28: 60a6 str r6, [r4, #8]
|
|
8006d2a: 2e00 cmp r6, #0
|
|
8006d2c: db05 blt.n 8006d3a <_printf_i+0x10e>
|
|
8006d2e: 6821 ldr r1, [r4, #0]
|
|
8006d30: 432e orrs r6, r5
|
|
8006d32: f021 0104 bic.w r1, r1, #4
|
|
8006d36: 6021 str r1, [r4, #0]
|
|
8006d38: d04b beq.n 8006dd2 <_printf_i+0x1a6>
|
|
8006d3a: 4616 mov r6, r2
|
|
8006d3c: fbb5 f1f3 udiv r1, r5, r3
|
|
8006d40: fb03 5711 mls r7, r3, r1, r5
|
|
8006d44: 5dc7 ldrb r7, [r0, r7]
|
|
8006d46: f806 7d01 strb.w r7, [r6, #-1]!
|
|
8006d4a: 462f mov r7, r5
|
|
8006d4c: 42bb cmp r3, r7
|
|
8006d4e: 460d mov r5, r1
|
|
8006d50: d9f4 bls.n 8006d3c <_printf_i+0x110>
|
|
8006d52: 2b08 cmp r3, #8
|
|
8006d54: d10b bne.n 8006d6e <_printf_i+0x142>
|
|
8006d56: 6823 ldr r3, [r4, #0]
|
|
8006d58: 07df lsls r7, r3, #31
|
|
8006d5a: d508 bpl.n 8006d6e <_printf_i+0x142>
|
|
8006d5c: 6923 ldr r3, [r4, #16]
|
|
8006d5e: 6861 ldr r1, [r4, #4]
|
|
8006d60: 4299 cmp r1, r3
|
|
8006d62: bfde ittt le
|
|
8006d64: 2330 movle r3, #48 @ 0x30
|
|
8006d66: f806 3c01 strble.w r3, [r6, #-1]
|
|
8006d6a: f106 36ff addle.w r6, r6, #4294967295 @ 0xffffffff
|
|
8006d6e: 1b92 subs r2, r2, r6
|
|
8006d70: 6122 str r2, [r4, #16]
|
|
8006d72: f8cd a000 str.w sl, [sp]
|
|
8006d76: 464b mov r3, r9
|
|
8006d78: aa03 add r2, sp, #12
|
|
8006d7a: 4621 mov r1, r4
|
|
8006d7c: 4640 mov r0, r8
|
|
8006d7e: f7ff fee7 bl 8006b50 <_printf_common>
|
|
8006d82: 3001 adds r0, #1
|
|
8006d84: d14a bne.n 8006e1c <_printf_i+0x1f0>
|
|
8006d86: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8006d8a: b004 add sp, #16
|
|
8006d8c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
8006d90: 6823 ldr r3, [r4, #0]
|
|
8006d92: f043 0320 orr.w r3, r3, #32
|
|
8006d96: 6023 str r3, [r4, #0]
|
|
8006d98: 4832 ldr r0, [pc, #200] @ (8006e64 <_printf_i+0x238>)
|
|
8006d9a: 2778 movs r7, #120 @ 0x78
|
|
8006d9c: f884 7045 strb.w r7, [r4, #69] @ 0x45
|
|
8006da0: 6823 ldr r3, [r4, #0]
|
|
8006da2: 6831 ldr r1, [r6, #0]
|
|
8006da4: 061f lsls r7, r3, #24
|
|
8006da6: f851 5b04 ldr.w r5, [r1], #4
|
|
8006daa: d402 bmi.n 8006db2 <_printf_i+0x186>
|
|
8006dac: 065f lsls r7, r3, #25
|
|
8006dae: bf48 it mi
|
|
8006db0: b2ad uxthmi r5, r5
|
|
8006db2: 6031 str r1, [r6, #0]
|
|
8006db4: 07d9 lsls r1, r3, #31
|
|
8006db6: bf44 itt mi
|
|
8006db8: f043 0320 orrmi.w r3, r3, #32
|
|
8006dbc: 6023 strmi r3, [r4, #0]
|
|
8006dbe: b11d cbz r5, 8006dc8 <_printf_i+0x19c>
|
|
8006dc0: 2310 movs r3, #16
|
|
8006dc2: e7ad b.n 8006d20 <_printf_i+0xf4>
|
|
8006dc4: 4826 ldr r0, [pc, #152] @ (8006e60 <_printf_i+0x234>)
|
|
8006dc6: e7e9 b.n 8006d9c <_printf_i+0x170>
|
|
8006dc8: 6823 ldr r3, [r4, #0]
|
|
8006dca: f023 0320 bic.w r3, r3, #32
|
|
8006dce: 6023 str r3, [r4, #0]
|
|
8006dd0: e7f6 b.n 8006dc0 <_printf_i+0x194>
|
|
8006dd2: 4616 mov r6, r2
|
|
8006dd4: e7bd b.n 8006d52 <_printf_i+0x126>
|
|
8006dd6: 6833 ldr r3, [r6, #0]
|
|
8006dd8: 6825 ldr r5, [r4, #0]
|
|
8006dda: 6961 ldr r1, [r4, #20]
|
|
8006ddc: 1d18 adds r0, r3, #4
|
|
8006dde: 6030 str r0, [r6, #0]
|
|
8006de0: 062e lsls r6, r5, #24
|
|
8006de2: 681b ldr r3, [r3, #0]
|
|
8006de4: d501 bpl.n 8006dea <_printf_i+0x1be>
|
|
8006de6: 6019 str r1, [r3, #0]
|
|
8006de8: e002 b.n 8006df0 <_printf_i+0x1c4>
|
|
8006dea: 0668 lsls r0, r5, #25
|
|
8006dec: d5fb bpl.n 8006de6 <_printf_i+0x1ba>
|
|
8006dee: 8019 strh r1, [r3, #0]
|
|
8006df0: 2300 movs r3, #0
|
|
8006df2: 6123 str r3, [r4, #16]
|
|
8006df4: 4616 mov r6, r2
|
|
8006df6: e7bc b.n 8006d72 <_printf_i+0x146>
|
|
8006df8: 6833 ldr r3, [r6, #0]
|
|
8006dfa: 1d1a adds r2, r3, #4
|
|
8006dfc: 6032 str r2, [r6, #0]
|
|
8006dfe: 681e ldr r6, [r3, #0]
|
|
8006e00: 6862 ldr r2, [r4, #4]
|
|
8006e02: 2100 movs r1, #0
|
|
8006e04: 4630 mov r0, r6
|
|
8006e06: f7f9 f9e3 bl 80001d0 <memchr>
|
|
8006e0a: b108 cbz r0, 8006e10 <_printf_i+0x1e4>
|
|
8006e0c: 1b80 subs r0, r0, r6
|
|
8006e0e: 6060 str r0, [r4, #4]
|
|
8006e10: 6863 ldr r3, [r4, #4]
|
|
8006e12: 6123 str r3, [r4, #16]
|
|
8006e14: 2300 movs r3, #0
|
|
8006e16: f884 3043 strb.w r3, [r4, #67] @ 0x43
|
|
8006e1a: e7aa b.n 8006d72 <_printf_i+0x146>
|
|
8006e1c: 6923 ldr r3, [r4, #16]
|
|
8006e1e: 4632 mov r2, r6
|
|
8006e20: 4649 mov r1, r9
|
|
8006e22: 4640 mov r0, r8
|
|
8006e24: 47d0 blx sl
|
|
8006e26: 3001 adds r0, #1
|
|
8006e28: d0ad beq.n 8006d86 <_printf_i+0x15a>
|
|
8006e2a: 6823 ldr r3, [r4, #0]
|
|
8006e2c: 079b lsls r3, r3, #30
|
|
8006e2e: d413 bmi.n 8006e58 <_printf_i+0x22c>
|
|
8006e30: 68e0 ldr r0, [r4, #12]
|
|
8006e32: 9b03 ldr r3, [sp, #12]
|
|
8006e34: 4298 cmp r0, r3
|
|
8006e36: bfb8 it lt
|
|
8006e38: 4618 movlt r0, r3
|
|
8006e3a: e7a6 b.n 8006d8a <_printf_i+0x15e>
|
|
8006e3c: 2301 movs r3, #1
|
|
8006e3e: 4632 mov r2, r6
|
|
8006e40: 4649 mov r1, r9
|
|
8006e42: 4640 mov r0, r8
|
|
8006e44: 47d0 blx sl
|
|
8006e46: 3001 adds r0, #1
|
|
8006e48: d09d beq.n 8006d86 <_printf_i+0x15a>
|
|
8006e4a: 3501 adds r5, #1
|
|
8006e4c: 68e3 ldr r3, [r4, #12]
|
|
8006e4e: 9903 ldr r1, [sp, #12]
|
|
8006e50: 1a5b subs r3, r3, r1
|
|
8006e52: 42ab cmp r3, r5
|
|
8006e54: dcf2 bgt.n 8006e3c <_printf_i+0x210>
|
|
8006e56: e7eb b.n 8006e30 <_printf_i+0x204>
|
|
8006e58: 2500 movs r5, #0
|
|
8006e5a: f104 0619 add.w r6, r4, #25
|
|
8006e5e: e7f5 b.n 8006e4c <_printf_i+0x220>
|
|
8006e60: 08009352 .word 0x08009352
|
|
8006e64: 08009363 .word 0x08009363
|
|
|
|
08006e68 <std>:
|
|
8006e68: 2300 movs r3, #0
|
|
8006e6a: b510 push {r4, lr}
|
|
8006e6c: 4604 mov r4, r0
|
|
8006e6e: e9c0 3300 strd r3, r3, [r0]
|
|
8006e72: e9c0 3304 strd r3, r3, [r0, #16]
|
|
8006e76: 6083 str r3, [r0, #8]
|
|
8006e78: 8181 strh r1, [r0, #12]
|
|
8006e7a: 6643 str r3, [r0, #100] @ 0x64
|
|
8006e7c: 81c2 strh r2, [r0, #14]
|
|
8006e7e: 6183 str r3, [r0, #24]
|
|
8006e80: 4619 mov r1, r3
|
|
8006e82: 2208 movs r2, #8
|
|
8006e84: 305c adds r0, #92 @ 0x5c
|
|
8006e86: f000 f928 bl 80070da <memset>
|
|
8006e8a: 4b0d ldr r3, [pc, #52] @ (8006ec0 <std+0x58>)
|
|
8006e8c: 6263 str r3, [r4, #36] @ 0x24
|
|
8006e8e: 4b0d ldr r3, [pc, #52] @ (8006ec4 <std+0x5c>)
|
|
8006e90: 62a3 str r3, [r4, #40] @ 0x28
|
|
8006e92: 4b0d ldr r3, [pc, #52] @ (8006ec8 <std+0x60>)
|
|
8006e94: 62e3 str r3, [r4, #44] @ 0x2c
|
|
8006e96: 4b0d ldr r3, [pc, #52] @ (8006ecc <std+0x64>)
|
|
8006e98: 6323 str r3, [r4, #48] @ 0x30
|
|
8006e9a: 4b0d ldr r3, [pc, #52] @ (8006ed0 <std+0x68>)
|
|
8006e9c: 6224 str r4, [r4, #32]
|
|
8006e9e: 429c cmp r4, r3
|
|
8006ea0: d006 beq.n 8006eb0 <std+0x48>
|
|
8006ea2: f103 0268 add.w r2, r3, #104 @ 0x68
|
|
8006ea6: 4294 cmp r4, r2
|
|
8006ea8: d002 beq.n 8006eb0 <std+0x48>
|
|
8006eaa: 33d0 adds r3, #208 @ 0xd0
|
|
8006eac: 429c cmp r4, r3
|
|
8006eae: d105 bne.n 8006ebc <std+0x54>
|
|
8006eb0: f104 0058 add.w r0, r4, #88 @ 0x58
|
|
8006eb4: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
8006eb8: f000 b98c b.w 80071d4 <__retarget_lock_init_recursive>
|
|
8006ebc: bd10 pop {r4, pc}
|
|
8006ebe: bf00 nop
|
|
8006ec0: 08007055 .word 0x08007055
|
|
8006ec4: 08007077 .word 0x08007077
|
|
8006ec8: 080070af .word 0x080070af
|
|
8006ecc: 080070d3 .word 0x080070d3
|
|
8006ed0: 2000032c .word 0x2000032c
|
|
|
|
08006ed4 <stdio_exit_handler>:
|
|
8006ed4: 4a02 ldr r2, [pc, #8] @ (8006ee0 <stdio_exit_handler+0xc>)
|
|
8006ed6: 4903 ldr r1, [pc, #12] @ (8006ee4 <stdio_exit_handler+0x10>)
|
|
8006ed8: 4803 ldr r0, [pc, #12] @ (8006ee8 <stdio_exit_handler+0x14>)
|
|
8006eda: f000 b869 b.w 8006fb0 <_fwalk_sglue>
|
|
8006ede: bf00 nop
|
|
8006ee0: 20000020 .word 0x20000020
|
|
8006ee4: 08008dc1 .word 0x08008dc1
|
|
8006ee8: 20000030 .word 0x20000030
|
|
|
|
08006eec <cleanup_stdio>:
|
|
8006eec: 6841 ldr r1, [r0, #4]
|
|
8006eee: 4b0c ldr r3, [pc, #48] @ (8006f20 <cleanup_stdio+0x34>)
|
|
8006ef0: 4299 cmp r1, r3
|
|
8006ef2: b510 push {r4, lr}
|
|
8006ef4: 4604 mov r4, r0
|
|
8006ef6: d001 beq.n 8006efc <cleanup_stdio+0x10>
|
|
8006ef8: f001 ff62 bl 8008dc0 <_fflush_r>
|
|
8006efc: 68a1 ldr r1, [r4, #8]
|
|
8006efe: 4b09 ldr r3, [pc, #36] @ (8006f24 <cleanup_stdio+0x38>)
|
|
8006f00: 4299 cmp r1, r3
|
|
8006f02: d002 beq.n 8006f0a <cleanup_stdio+0x1e>
|
|
8006f04: 4620 mov r0, r4
|
|
8006f06: f001 ff5b bl 8008dc0 <_fflush_r>
|
|
8006f0a: 68e1 ldr r1, [r4, #12]
|
|
8006f0c: 4b06 ldr r3, [pc, #24] @ (8006f28 <cleanup_stdio+0x3c>)
|
|
8006f0e: 4299 cmp r1, r3
|
|
8006f10: d004 beq.n 8006f1c <cleanup_stdio+0x30>
|
|
8006f12: 4620 mov r0, r4
|
|
8006f14: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
8006f18: f001 bf52 b.w 8008dc0 <_fflush_r>
|
|
8006f1c: bd10 pop {r4, pc}
|
|
8006f1e: bf00 nop
|
|
8006f20: 2000032c .word 0x2000032c
|
|
8006f24: 20000394 .word 0x20000394
|
|
8006f28: 200003fc .word 0x200003fc
|
|
|
|
08006f2c <global_stdio_init.part.0>:
|
|
8006f2c: b510 push {r4, lr}
|
|
8006f2e: 4b0b ldr r3, [pc, #44] @ (8006f5c <global_stdio_init.part.0+0x30>)
|
|
8006f30: 4c0b ldr r4, [pc, #44] @ (8006f60 <global_stdio_init.part.0+0x34>)
|
|
8006f32: 4a0c ldr r2, [pc, #48] @ (8006f64 <global_stdio_init.part.0+0x38>)
|
|
8006f34: 601a str r2, [r3, #0]
|
|
8006f36: 4620 mov r0, r4
|
|
8006f38: 2200 movs r2, #0
|
|
8006f3a: 2104 movs r1, #4
|
|
8006f3c: f7ff ff94 bl 8006e68 <std>
|
|
8006f40: f104 0068 add.w r0, r4, #104 @ 0x68
|
|
8006f44: 2201 movs r2, #1
|
|
8006f46: 2109 movs r1, #9
|
|
8006f48: f7ff ff8e bl 8006e68 <std>
|
|
8006f4c: f104 00d0 add.w r0, r4, #208 @ 0xd0
|
|
8006f50: 2202 movs r2, #2
|
|
8006f52: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
8006f56: 2112 movs r1, #18
|
|
8006f58: f7ff bf86 b.w 8006e68 <std>
|
|
8006f5c: 20000464 .word 0x20000464
|
|
8006f60: 2000032c .word 0x2000032c
|
|
8006f64: 08006ed5 .word 0x08006ed5
|
|
|
|
08006f68 <__sfp_lock_acquire>:
|
|
8006f68: 4801 ldr r0, [pc, #4] @ (8006f70 <__sfp_lock_acquire+0x8>)
|
|
8006f6a: f000 b934 b.w 80071d6 <__retarget_lock_acquire_recursive>
|
|
8006f6e: bf00 nop
|
|
8006f70: 2000046d .word 0x2000046d
|
|
|
|
08006f74 <__sfp_lock_release>:
|
|
8006f74: 4801 ldr r0, [pc, #4] @ (8006f7c <__sfp_lock_release+0x8>)
|
|
8006f76: f000 b92f b.w 80071d8 <__retarget_lock_release_recursive>
|
|
8006f7a: bf00 nop
|
|
8006f7c: 2000046d .word 0x2000046d
|
|
|
|
08006f80 <__sinit>:
|
|
8006f80: b510 push {r4, lr}
|
|
8006f82: 4604 mov r4, r0
|
|
8006f84: f7ff fff0 bl 8006f68 <__sfp_lock_acquire>
|
|
8006f88: 6a23 ldr r3, [r4, #32]
|
|
8006f8a: b11b cbz r3, 8006f94 <__sinit+0x14>
|
|
8006f8c: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
8006f90: f7ff bff0 b.w 8006f74 <__sfp_lock_release>
|
|
8006f94: 4b04 ldr r3, [pc, #16] @ (8006fa8 <__sinit+0x28>)
|
|
8006f96: 6223 str r3, [r4, #32]
|
|
8006f98: 4b04 ldr r3, [pc, #16] @ (8006fac <__sinit+0x2c>)
|
|
8006f9a: 681b ldr r3, [r3, #0]
|
|
8006f9c: 2b00 cmp r3, #0
|
|
8006f9e: d1f5 bne.n 8006f8c <__sinit+0xc>
|
|
8006fa0: f7ff ffc4 bl 8006f2c <global_stdio_init.part.0>
|
|
8006fa4: e7f2 b.n 8006f8c <__sinit+0xc>
|
|
8006fa6: bf00 nop
|
|
8006fa8: 08006eed .word 0x08006eed
|
|
8006fac: 20000464 .word 0x20000464
|
|
|
|
08006fb0 <_fwalk_sglue>:
|
|
8006fb0: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
|
|
8006fb4: 4607 mov r7, r0
|
|
8006fb6: 4688 mov r8, r1
|
|
8006fb8: 4614 mov r4, r2
|
|
8006fba: 2600 movs r6, #0
|
|
8006fbc: e9d4 9501 ldrd r9, r5, [r4, #4]
|
|
8006fc0: f1b9 0901 subs.w r9, r9, #1
|
|
8006fc4: d505 bpl.n 8006fd2 <_fwalk_sglue+0x22>
|
|
8006fc6: 6824 ldr r4, [r4, #0]
|
|
8006fc8: 2c00 cmp r4, #0
|
|
8006fca: d1f7 bne.n 8006fbc <_fwalk_sglue+0xc>
|
|
8006fcc: 4630 mov r0, r6
|
|
8006fce: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
|
|
8006fd2: 89ab ldrh r3, [r5, #12]
|
|
8006fd4: 2b01 cmp r3, #1
|
|
8006fd6: d907 bls.n 8006fe8 <_fwalk_sglue+0x38>
|
|
8006fd8: f9b5 300e ldrsh.w r3, [r5, #14]
|
|
8006fdc: 3301 adds r3, #1
|
|
8006fde: d003 beq.n 8006fe8 <_fwalk_sglue+0x38>
|
|
8006fe0: 4629 mov r1, r5
|
|
8006fe2: 4638 mov r0, r7
|
|
8006fe4: 47c0 blx r8
|
|
8006fe6: 4306 orrs r6, r0
|
|
8006fe8: 3568 adds r5, #104 @ 0x68
|
|
8006fea: e7e9 b.n 8006fc0 <_fwalk_sglue+0x10>
|
|
|
|
08006fec <iprintf>:
|
|
8006fec: b40f push {r0, r1, r2, r3}
|
|
8006fee: b507 push {r0, r1, r2, lr}
|
|
8006ff0: 4906 ldr r1, [pc, #24] @ (800700c <iprintf+0x20>)
|
|
8006ff2: ab04 add r3, sp, #16
|
|
8006ff4: 6808 ldr r0, [r1, #0]
|
|
8006ff6: f853 2b04 ldr.w r2, [r3], #4
|
|
8006ffa: 6881 ldr r1, [r0, #8]
|
|
8006ffc: 9301 str r3, [sp, #4]
|
|
8006ffe: f001 fd43 bl 8008a88 <_vfiprintf_r>
|
|
8007002: b003 add sp, #12
|
|
8007004: f85d eb04 ldr.w lr, [sp], #4
|
|
8007008: b004 add sp, #16
|
|
800700a: 4770 bx lr
|
|
800700c: 2000002c .word 0x2000002c
|
|
|
|
08007010 <siprintf>:
|
|
8007010: b40e push {r1, r2, r3}
|
|
8007012: b510 push {r4, lr}
|
|
8007014: b09d sub sp, #116 @ 0x74
|
|
8007016: ab1f add r3, sp, #124 @ 0x7c
|
|
8007018: 9002 str r0, [sp, #8]
|
|
800701a: 9006 str r0, [sp, #24]
|
|
800701c: f06f 4100 mvn.w r1, #2147483648 @ 0x80000000
|
|
8007020: 480a ldr r0, [pc, #40] @ (800704c <siprintf+0x3c>)
|
|
8007022: 9107 str r1, [sp, #28]
|
|
8007024: 9104 str r1, [sp, #16]
|
|
8007026: 490a ldr r1, [pc, #40] @ (8007050 <siprintf+0x40>)
|
|
8007028: f853 2b04 ldr.w r2, [r3], #4
|
|
800702c: 9105 str r1, [sp, #20]
|
|
800702e: 2400 movs r4, #0
|
|
8007030: a902 add r1, sp, #8
|
|
8007032: 6800 ldr r0, [r0, #0]
|
|
8007034: 9301 str r3, [sp, #4]
|
|
8007036: 941b str r4, [sp, #108] @ 0x6c
|
|
8007038: f001 fc00 bl 800883c <_svfiprintf_r>
|
|
800703c: 9b02 ldr r3, [sp, #8]
|
|
800703e: 701c strb r4, [r3, #0]
|
|
8007040: b01d add sp, #116 @ 0x74
|
|
8007042: e8bd 4010 ldmia.w sp!, {r4, lr}
|
|
8007046: b003 add sp, #12
|
|
8007048: 4770 bx lr
|
|
800704a: bf00 nop
|
|
800704c: 2000002c .word 0x2000002c
|
|
8007050: ffff0208 .word 0xffff0208
|
|
|
|
08007054 <__sread>:
|
|
8007054: b510 push {r4, lr}
|
|
8007056: 460c mov r4, r1
|
|
8007058: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
800705c: f000 f86c bl 8007138 <_read_r>
|
|
8007060: 2800 cmp r0, #0
|
|
8007062: bfab itete ge
|
|
8007064: 6d63 ldrge r3, [r4, #84] @ 0x54
|
|
8007066: 89a3 ldrhlt r3, [r4, #12]
|
|
8007068: 181b addge r3, r3, r0
|
|
800706a: f423 5380 biclt.w r3, r3, #4096 @ 0x1000
|
|
800706e: bfac ite ge
|
|
8007070: 6563 strge r3, [r4, #84] @ 0x54
|
|
8007072: 81a3 strhlt r3, [r4, #12]
|
|
8007074: bd10 pop {r4, pc}
|
|
|
|
08007076 <__swrite>:
|
|
8007076: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
800707a: 461f mov r7, r3
|
|
800707c: 898b ldrh r3, [r1, #12]
|
|
800707e: 05db lsls r3, r3, #23
|
|
8007080: 4605 mov r5, r0
|
|
8007082: 460c mov r4, r1
|
|
8007084: 4616 mov r6, r2
|
|
8007086: d505 bpl.n 8007094 <__swrite+0x1e>
|
|
8007088: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
800708c: 2302 movs r3, #2
|
|
800708e: 2200 movs r2, #0
|
|
8007090: f000 f840 bl 8007114 <_lseek_r>
|
|
8007094: 89a3 ldrh r3, [r4, #12]
|
|
8007096: f9b4 100e ldrsh.w r1, [r4, #14]
|
|
800709a: f423 5380 bic.w r3, r3, #4096 @ 0x1000
|
|
800709e: 81a3 strh r3, [r4, #12]
|
|
80070a0: 4632 mov r2, r6
|
|
80070a2: 463b mov r3, r7
|
|
80070a4: 4628 mov r0, r5
|
|
80070a6: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
|
|
80070aa: f000 b857 b.w 800715c <_write_r>
|
|
|
|
080070ae <__sseek>:
|
|
80070ae: b510 push {r4, lr}
|
|
80070b0: 460c mov r4, r1
|
|
80070b2: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
80070b6: f000 f82d bl 8007114 <_lseek_r>
|
|
80070ba: 1c43 adds r3, r0, #1
|
|
80070bc: 89a3 ldrh r3, [r4, #12]
|
|
80070be: bf15 itete ne
|
|
80070c0: 6560 strne r0, [r4, #84] @ 0x54
|
|
80070c2: f423 5380 biceq.w r3, r3, #4096 @ 0x1000
|
|
80070c6: f443 5380 orrne.w r3, r3, #4096 @ 0x1000
|
|
80070ca: 81a3 strheq r3, [r4, #12]
|
|
80070cc: bf18 it ne
|
|
80070ce: 81a3 strhne r3, [r4, #12]
|
|
80070d0: bd10 pop {r4, pc}
|
|
|
|
080070d2 <__sclose>:
|
|
80070d2: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
80070d6: f000 b80d b.w 80070f4 <_close_r>
|
|
|
|
080070da <memset>:
|
|
80070da: 4402 add r2, r0
|
|
80070dc: 4603 mov r3, r0
|
|
80070de: 4293 cmp r3, r2
|
|
80070e0: d100 bne.n 80070e4 <memset+0xa>
|
|
80070e2: 4770 bx lr
|
|
80070e4: f803 1b01 strb.w r1, [r3], #1
|
|
80070e8: e7f9 b.n 80070de <memset+0x4>
|
|
...
|
|
|
|
080070ec <_localeconv_r>:
|
|
80070ec: 4800 ldr r0, [pc, #0] @ (80070f0 <_localeconv_r+0x4>)
|
|
80070ee: 4770 bx lr
|
|
80070f0: 2000016c .word 0x2000016c
|
|
|
|
080070f4 <_close_r>:
|
|
80070f4: b538 push {r3, r4, r5, lr}
|
|
80070f6: 4d06 ldr r5, [pc, #24] @ (8007110 <_close_r+0x1c>)
|
|
80070f8: 2300 movs r3, #0
|
|
80070fa: 4604 mov r4, r0
|
|
80070fc: 4608 mov r0, r1
|
|
80070fe: 602b str r3, [r5, #0]
|
|
8007100: f7fb f89e bl 8002240 <_close>
|
|
8007104: 1c43 adds r3, r0, #1
|
|
8007106: d102 bne.n 800710e <_close_r+0x1a>
|
|
8007108: 682b ldr r3, [r5, #0]
|
|
800710a: b103 cbz r3, 800710e <_close_r+0x1a>
|
|
800710c: 6023 str r3, [r4, #0]
|
|
800710e: bd38 pop {r3, r4, r5, pc}
|
|
8007110: 20000468 .word 0x20000468
|
|
|
|
08007114 <_lseek_r>:
|
|
8007114: b538 push {r3, r4, r5, lr}
|
|
8007116: 4d07 ldr r5, [pc, #28] @ (8007134 <_lseek_r+0x20>)
|
|
8007118: 4604 mov r4, r0
|
|
800711a: 4608 mov r0, r1
|
|
800711c: 4611 mov r1, r2
|
|
800711e: 2200 movs r2, #0
|
|
8007120: 602a str r2, [r5, #0]
|
|
8007122: 461a mov r2, r3
|
|
8007124: f7fb f8b3 bl 800228e <_lseek>
|
|
8007128: 1c43 adds r3, r0, #1
|
|
800712a: d102 bne.n 8007132 <_lseek_r+0x1e>
|
|
800712c: 682b ldr r3, [r5, #0]
|
|
800712e: b103 cbz r3, 8007132 <_lseek_r+0x1e>
|
|
8007130: 6023 str r3, [r4, #0]
|
|
8007132: bd38 pop {r3, r4, r5, pc}
|
|
8007134: 20000468 .word 0x20000468
|
|
|
|
08007138 <_read_r>:
|
|
8007138: b538 push {r3, r4, r5, lr}
|
|
800713a: 4d07 ldr r5, [pc, #28] @ (8007158 <_read_r+0x20>)
|
|
800713c: 4604 mov r4, r0
|
|
800713e: 4608 mov r0, r1
|
|
8007140: 4611 mov r1, r2
|
|
8007142: 2200 movs r2, #0
|
|
8007144: 602a str r2, [r5, #0]
|
|
8007146: 461a mov r2, r3
|
|
8007148: f7fb f841 bl 80021ce <_read>
|
|
800714c: 1c43 adds r3, r0, #1
|
|
800714e: d102 bne.n 8007156 <_read_r+0x1e>
|
|
8007150: 682b ldr r3, [r5, #0]
|
|
8007152: b103 cbz r3, 8007156 <_read_r+0x1e>
|
|
8007154: 6023 str r3, [r4, #0]
|
|
8007156: bd38 pop {r3, r4, r5, pc}
|
|
8007158: 20000468 .word 0x20000468
|
|
|
|
0800715c <_write_r>:
|
|
800715c: b538 push {r3, r4, r5, lr}
|
|
800715e: 4d07 ldr r5, [pc, #28] @ (800717c <_write_r+0x20>)
|
|
8007160: 4604 mov r4, r0
|
|
8007162: 4608 mov r0, r1
|
|
8007164: 4611 mov r1, r2
|
|
8007166: 2200 movs r2, #0
|
|
8007168: 602a str r2, [r5, #0]
|
|
800716a: 461a mov r2, r3
|
|
800716c: f7fb f84c bl 8002208 <_write>
|
|
8007170: 1c43 adds r3, r0, #1
|
|
8007172: d102 bne.n 800717a <_write_r+0x1e>
|
|
8007174: 682b ldr r3, [r5, #0]
|
|
8007176: b103 cbz r3, 800717a <_write_r+0x1e>
|
|
8007178: 6023 str r3, [r4, #0]
|
|
800717a: bd38 pop {r3, r4, r5, pc}
|
|
800717c: 20000468 .word 0x20000468
|
|
|
|
08007180 <__errno>:
|
|
8007180: 4b01 ldr r3, [pc, #4] @ (8007188 <__errno+0x8>)
|
|
8007182: 6818 ldr r0, [r3, #0]
|
|
8007184: 4770 bx lr
|
|
8007186: bf00 nop
|
|
8007188: 2000002c .word 0x2000002c
|
|
|
|
0800718c <__libc_init_array>:
|
|
800718c: b570 push {r4, r5, r6, lr}
|
|
800718e: 4d0d ldr r5, [pc, #52] @ (80071c4 <__libc_init_array+0x38>)
|
|
8007190: 4c0d ldr r4, [pc, #52] @ (80071c8 <__libc_init_array+0x3c>)
|
|
8007192: 1b64 subs r4, r4, r5
|
|
8007194: 10a4 asrs r4, r4, #2
|
|
8007196: 2600 movs r6, #0
|
|
8007198: 42a6 cmp r6, r4
|
|
800719a: d109 bne.n 80071b0 <__libc_init_array+0x24>
|
|
800719c: 4d0b ldr r5, [pc, #44] @ (80071cc <__libc_init_array+0x40>)
|
|
800719e: 4c0c ldr r4, [pc, #48] @ (80071d0 <__libc_init_array+0x44>)
|
|
80071a0: f002 f86c bl 800927c <_init>
|
|
80071a4: 1b64 subs r4, r4, r5
|
|
80071a6: 10a4 asrs r4, r4, #2
|
|
80071a8: 2600 movs r6, #0
|
|
80071aa: 42a6 cmp r6, r4
|
|
80071ac: d105 bne.n 80071ba <__libc_init_array+0x2e>
|
|
80071ae: bd70 pop {r4, r5, r6, pc}
|
|
80071b0: f855 3b04 ldr.w r3, [r5], #4
|
|
80071b4: 4798 blx r3
|
|
80071b6: 3601 adds r6, #1
|
|
80071b8: e7ee b.n 8007198 <__libc_init_array+0xc>
|
|
80071ba: f855 3b04 ldr.w r3, [r5], #4
|
|
80071be: 4798 blx r3
|
|
80071c0: 3601 adds r6, #1
|
|
80071c2: e7f2 b.n 80071aa <__libc_init_array+0x1e>
|
|
80071c4: 080096bc .word 0x080096bc
|
|
80071c8: 080096bc .word 0x080096bc
|
|
80071cc: 080096bc .word 0x080096bc
|
|
80071d0: 080096c0 .word 0x080096c0
|
|
|
|
080071d4 <__retarget_lock_init_recursive>:
|
|
80071d4: 4770 bx lr
|
|
|
|
080071d6 <__retarget_lock_acquire_recursive>:
|
|
80071d6: 4770 bx lr
|
|
|
|
080071d8 <__retarget_lock_release_recursive>:
|
|
80071d8: 4770 bx lr
|
|
|
|
080071da <quorem>:
|
|
80071da: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
80071de: 6903 ldr r3, [r0, #16]
|
|
80071e0: 690c ldr r4, [r1, #16]
|
|
80071e2: 42a3 cmp r3, r4
|
|
80071e4: 4607 mov r7, r0
|
|
80071e6: db7e blt.n 80072e6 <quorem+0x10c>
|
|
80071e8: 3c01 subs r4, #1
|
|
80071ea: f101 0814 add.w r8, r1, #20
|
|
80071ee: 00a3 lsls r3, r4, #2
|
|
80071f0: f100 0514 add.w r5, r0, #20
|
|
80071f4: 9300 str r3, [sp, #0]
|
|
80071f6: eb05 0384 add.w r3, r5, r4, lsl #2
|
|
80071fa: 9301 str r3, [sp, #4]
|
|
80071fc: f858 3024 ldr.w r3, [r8, r4, lsl #2]
|
|
8007200: f855 2024 ldr.w r2, [r5, r4, lsl #2]
|
|
8007204: 3301 adds r3, #1
|
|
8007206: 429a cmp r2, r3
|
|
8007208: eb08 0984 add.w r9, r8, r4, lsl #2
|
|
800720c: fbb2 f6f3 udiv r6, r2, r3
|
|
8007210: d32e bcc.n 8007270 <quorem+0x96>
|
|
8007212: f04f 0a00 mov.w sl, #0
|
|
8007216: 46c4 mov ip, r8
|
|
8007218: 46ae mov lr, r5
|
|
800721a: 46d3 mov fp, sl
|
|
800721c: f85c 3b04 ldr.w r3, [ip], #4
|
|
8007220: b298 uxth r0, r3
|
|
8007222: fb06 a000 mla r0, r6, r0, sl
|
|
8007226: 0c02 lsrs r2, r0, #16
|
|
8007228: 0c1b lsrs r3, r3, #16
|
|
800722a: fb06 2303 mla r3, r6, r3, r2
|
|
800722e: f8de 2000 ldr.w r2, [lr]
|
|
8007232: b280 uxth r0, r0
|
|
8007234: b292 uxth r2, r2
|
|
8007236: 1a12 subs r2, r2, r0
|
|
8007238: 445a add r2, fp
|
|
800723a: f8de 0000 ldr.w r0, [lr]
|
|
800723e: ea4f 4a13 mov.w sl, r3, lsr #16
|
|
8007242: b29b uxth r3, r3
|
|
8007244: ebc3 4322 rsb r3, r3, r2, asr #16
|
|
8007248: eb03 4310 add.w r3, r3, r0, lsr #16
|
|
800724c: b292 uxth r2, r2
|
|
800724e: ea42 4203 orr.w r2, r2, r3, lsl #16
|
|
8007252: 45e1 cmp r9, ip
|
|
8007254: f84e 2b04 str.w r2, [lr], #4
|
|
8007258: ea4f 4b23 mov.w fp, r3, asr #16
|
|
800725c: d2de bcs.n 800721c <quorem+0x42>
|
|
800725e: 9b00 ldr r3, [sp, #0]
|
|
8007260: 58eb ldr r3, [r5, r3]
|
|
8007262: b92b cbnz r3, 8007270 <quorem+0x96>
|
|
8007264: 9b01 ldr r3, [sp, #4]
|
|
8007266: 3b04 subs r3, #4
|
|
8007268: 429d cmp r5, r3
|
|
800726a: 461a mov r2, r3
|
|
800726c: d32f bcc.n 80072ce <quorem+0xf4>
|
|
800726e: 613c str r4, [r7, #16]
|
|
8007270: 4638 mov r0, r7
|
|
8007272: f001 f97f bl 8008574 <__mcmp>
|
|
8007276: 2800 cmp r0, #0
|
|
8007278: db25 blt.n 80072c6 <quorem+0xec>
|
|
800727a: 4629 mov r1, r5
|
|
800727c: 2000 movs r0, #0
|
|
800727e: f858 2b04 ldr.w r2, [r8], #4
|
|
8007282: f8d1 c000 ldr.w ip, [r1]
|
|
8007286: fa1f fe82 uxth.w lr, r2
|
|
800728a: fa1f f38c uxth.w r3, ip
|
|
800728e: eba3 030e sub.w r3, r3, lr
|
|
8007292: 4403 add r3, r0
|
|
8007294: 0c12 lsrs r2, r2, #16
|
|
8007296: ebc2 4223 rsb r2, r2, r3, asr #16
|
|
800729a: eb02 421c add.w r2, r2, ip, lsr #16
|
|
800729e: b29b uxth r3, r3
|
|
80072a0: ea43 4302 orr.w r3, r3, r2, lsl #16
|
|
80072a4: 45c1 cmp r9, r8
|
|
80072a6: f841 3b04 str.w r3, [r1], #4
|
|
80072aa: ea4f 4022 mov.w r0, r2, asr #16
|
|
80072ae: d2e6 bcs.n 800727e <quorem+0xa4>
|
|
80072b0: f855 2024 ldr.w r2, [r5, r4, lsl #2]
|
|
80072b4: eb05 0384 add.w r3, r5, r4, lsl #2
|
|
80072b8: b922 cbnz r2, 80072c4 <quorem+0xea>
|
|
80072ba: 3b04 subs r3, #4
|
|
80072bc: 429d cmp r5, r3
|
|
80072be: 461a mov r2, r3
|
|
80072c0: d30b bcc.n 80072da <quorem+0x100>
|
|
80072c2: 613c str r4, [r7, #16]
|
|
80072c4: 3601 adds r6, #1
|
|
80072c6: 4630 mov r0, r6
|
|
80072c8: b003 add sp, #12
|
|
80072ca: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
80072ce: 6812 ldr r2, [r2, #0]
|
|
80072d0: 3b04 subs r3, #4
|
|
80072d2: 2a00 cmp r2, #0
|
|
80072d4: d1cb bne.n 800726e <quorem+0x94>
|
|
80072d6: 3c01 subs r4, #1
|
|
80072d8: e7c6 b.n 8007268 <quorem+0x8e>
|
|
80072da: 6812 ldr r2, [r2, #0]
|
|
80072dc: 3b04 subs r3, #4
|
|
80072de: 2a00 cmp r2, #0
|
|
80072e0: d1ef bne.n 80072c2 <quorem+0xe8>
|
|
80072e2: 3c01 subs r4, #1
|
|
80072e4: e7ea b.n 80072bc <quorem+0xe2>
|
|
80072e6: 2000 movs r0, #0
|
|
80072e8: e7ee b.n 80072c8 <quorem+0xee>
|
|
80072ea: 0000 movs r0, r0
|
|
80072ec: 0000 movs r0, r0
|
|
...
|
|
|
|
080072f0 <_dtoa_r>:
|
|
80072f0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
80072f4: 69c7 ldr r7, [r0, #28]
|
|
80072f6: b097 sub sp, #92 @ 0x5c
|
|
80072f8: ed8d 0b04 vstr d0, [sp, #16]
|
|
80072fc: ec55 4b10 vmov r4, r5, d0
|
|
8007300: 9e20 ldr r6, [sp, #128] @ 0x80
|
|
8007302: 9107 str r1, [sp, #28]
|
|
8007304: 4681 mov r9, r0
|
|
8007306: 920c str r2, [sp, #48] @ 0x30
|
|
8007308: 9311 str r3, [sp, #68] @ 0x44
|
|
800730a: b97f cbnz r7, 800732c <_dtoa_r+0x3c>
|
|
800730c: 2010 movs r0, #16
|
|
800730e: f000 fe09 bl 8007f24 <malloc>
|
|
8007312: 4602 mov r2, r0
|
|
8007314: f8c9 001c str.w r0, [r9, #28]
|
|
8007318: b920 cbnz r0, 8007324 <_dtoa_r+0x34>
|
|
800731a: 4ba9 ldr r3, [pc, #676] @ (80075c0 <_dtoa_r+0x2d0>)
|
|
800731c: 21ef movs r1, #239 @ 0xef
|
|
800731e: 48a9 ldr r0, [pc, #676] @ (80075c4 <_dtoa_r+0x2d4>)
|
|
8007320: f001 fe42 bl 8008fa8 <__assert_func>
|
|
8007324: e9c0 7701 strd r7, r7, [r0, #4]
|
|
8007328: 6007 str r7, [r0, #0]
|
|
800732a: 60c7 str r7, [r0, #12]
|
|
800732c: f8d9 301c ldr.w r3, [r9, #28]
|
|
8007330: 6819 ldr r1, [r3, #0]
|
|
8007332: b159 cbz r1, 800734c <_dtoa_r+0x5c>
|
|
8007334: 685a ldr r2, [r3, #4]
|
|
8007336: 604a str r2, [r1, #4]
|
|
8007338: 2301 movs r3, #1
|
|
800733a: 4093 lsls r3, r2
|
|
800733c: 608b str r3, [r1, #8]
|
|
800733e: 4648 mov r0, r9
|
|
8007340: f000 fee6 bl 8008110 <_Bfree>
|
|
8007344: f8d9 301c ldr.w r3, [r9, #28]
|
|
8007348: 2200 movs r2, #0
|
|
800734a: 601a str r2, [r3, #0]
|
|
800734c: 1e2b subs r3, r5, #0
|
|
800734e: bfb9 ittee lt
|
|
8007350: f023 4300 biclt.w r3, r3, #2147483648 @ 0x80000000
|
|
8007354: 9305 strlt r3, [sp, #20]
|
|
8007356: 2300 movge r3, #0
|
|
8007358: 6033 strge r3, [r6, #0]
|
|
800735a: 9f05 ldr r7, [sp, #20]
|
|
800735c: 4b9a ldr r3, [pc, #616] @ (80075c8 <_dtoa_r+0x2d8>)
|
|
800735e: bfbc itt lt
|
|
8007360: 2201 movlt r2, #1
|
|
8007362: 6032 strlt r2, [r6, #0]
|
|
8007364: 43bb bics r3, r7
|
|
8007366: d112 bne.n 800738e <_dtoa_r+0x9e>
|
|
8007368: 9a11 ldr r2, [sp, #68] @ 0x44
|
|
800736a: f242 730f movw r3, #9999 @ 0x270f
|
|
800736e: 6013 str r3, [r2, #0]
|
|
8007370: f3c7 0313 ubfx r3, r7, #0, #20
|
|
8007374: 4323 orrs r3, r4
|
|
8007376: f000 855a beq.w 8007e2e <_dtoa_r+0xb3e>
|
|
800737a: 9b21 ldr r3, [sp, #132] @ 0x84
|
|
800737c: f8df a25c ldr.w sl, [pc, #604] @ 80075dc <_dtoa_r+0x2ec>
|
|
8007380: 2b00 cmp r3, #0
|
|
8007382: f000 855c beq.w 8007e3e <_dtoa_r+0xb4e>
|
|
8007386: f10a 0303 add.w r3, sl, #3
|
|
800738a: f000 bd56 b.w 8007e3a <_dtoa_r+0xb4a>
|
|
800738e: ed9d 7b04 vldr d7, [sp, #16]
|
|
8007392: 2200 movs r2, #0
|
|
8007394: ec51 0b17 vmov r0, r1, d7
|
|
8007398: 2300 movs r3, #0
|
|
800739a: ed8d 7b0a vstr d7, [sp, #40] @ 0x28
|
|
800739e: f7f9 fb93 bl 8000ac8 <__aeabi_dcmpeq>
|
|
80073a2: 4680 mov r8, r0
|
|
80073a4: b158 cbz r0, 80073be <_dtoa_r+0xce>
|
|
80073a6: 9a11 ldr r2, [sp, #68] @ 0x44
|
|
80073a8: 2301 movs r3, #1
|
|
80073aa: 6013 str r3, [r2, #0]
|
|
80073ac: 9b21 ldr r3, [sp, #132] @ 0x84
|
|
80073ae: b113 cbz r3, 80073b6 <_dtoa_r+0xc6>
|
|
80073b0: 9a21 ldr r2, [sp, #132] @ 0x84
|
|
80073b2: 4b86 ldr r3, [pc, #536] @ (80075cc <_dtoa_r+0x2dc>)
|
|
80073b4: 6013 str r3, [r2, #0]
|
|
80073b6: f8df a228 ldr.w sl, [pc, #552] @ 80075e0 <_dtoa_r+0x2f0>
|
|
80073ba: f000 bd40 b.w 8007e3e <_dtoa_r+0xb4e>
|
|
80073be: ed9d 0b0a vldr d0, [sp, #40] @ 0x28
|
|
80073c2: aa14 add r2, sp, #80 @ 0x50
|
|
80073c4: a915 add r1, sp, #84 @ 0x54
|
|
80073c6: 4648 mov r0, r9
|
|
80073c8: f001 f984 bl 80086d4 <__d2b>
|
|
80073cc: f3c7 560a ubfx r6, r7, #20, #11
|
|
80073d0: 9002 str r0, [sp, #8]
|
|
80073d2: 2e00 cmp r6, #0
|
|
80073d4: d078 beq.n 80074c8 <_dtoa_r+0x1d8>
|
|
80073d6: 9b0b ldr r3, [sp, #44] @ 0x2c
|
|
80073d8: f8cd 8048 str.w r8, [sp, #72] @ 0x48
|
|
80073dc: f3c3 0313 ubfx r3, r3, #0, #20
|
|
80073e0: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28
|
|
80073e4: f043 537f orr.w r3, r3, #1069547520 @ 0x3fc00000
|
|
80073e8: f443 1340 orr.w r3, r3, #3145728 @ 0x300000
|
|
80073ec: f2a6 36ff subw r6, r6, #1023 @ 0x3ff
|
|
80073f0: 4619 mov r1, r3
|
|
80073f2: 2200 movs r2, #0
|
|
80073f4: 4b76 ldr r3, [pc, #472] @ (80075d0 <_dtoa_r+0x2e0>)
|
|
80073f6: f7f8 ff47 bl 8000288 <__aeabi_dsub>
|
|
80073fa: a36b add r3, pc, #428 @ (adr r3, 80075a8 <_dtoa_r+0x2b8>)
|
|
80073fc: e9d3 2300 ldrd r2, r3, [r3]
|
|
8007400: f7f9 f8fa bl 80005f8 <__aeabi_dmul>
|
|
8007404: a36a add r3, pc, #424 @ (adr r3, 80075b0 <_dtoa_r+0x2c0>)
|
|
8007406: e9d3 2300 ldrd r2, r3, [r3]
|
|
800740a: f7f8 ff3f bl 800028c <__adddf3>
|
|
800740e: 4604 mov r4, r0
|
|
8007410: 4630 mov r0, r6
|
|
8007412: 460d mov r5, r1
|
|
8007414: f7f9 f886 bl 8000524 <__aeabi_i2d>
|
|
8007418: a367 add r3, pc, #412 @ (adr r3, 80075b8 <_dtoa_r+0x2c8>)
|
|
800741a: e9d3 2300 ldrd r2, r3, [r3]
|
|
800741e: f7f9 f8eb bl 80005f8 <__aeabi_dmul>
|
|
8007422: 4602 mov r2, r0
|
|
8007424: 460b mov r3, r1
|
|
8007426: 4620 mov r0, r4
|
|
8007428: 4629 mov r1, r5
|
|
800742a: f7f8 ff2f bl 800028c <__adddf3>
|
|
800742e: 4604 mov r4, r0
|
|
8007430: 460d mov r5, r1
|
|
8007432: f7f9 fb91 bl 8000b58 <__aeabi_d2iz>
|
|
8007436: 2200 movs r2, #0
|
|
8007438: 4607 mov r7, r0
|
|
800743a: 2300 movs r3, #0
|
|
800743c: 4620 mov r0, r4
|
|
800743e: 4629 mov r1, r5
|
|
8007440: f7f9 fb4c bl 8000adc <__aeabi_dcmplt>
|
|
8007444: b140 cbz r0, 8007458 <_dtoa_r+0x168>
|
|
8007446: 4638 mov r0, r7
|
|
8007448: f7f9 f86c bl 8000524 <__aeabi_i2d>
|
|
800744c: 4622 mov r2, r4
|
|
800744e: 462b mov r3, r5
|
|
8007450: f7f9 fb3a bl 8000ac8 <__aeabi_dcmpeq>
|
|
8007454: b900 cbnz r0, 8007458 <_dtoa_r+0x168>
|
|
8007456: 3f01 subs r7, #1
|
|
8007458: 2f16 cmp r7, #22
|
|
800745a: d852 bhi.n 8007502 <_dtoa_r+0x212>
|
|
800745c: 4b5d ldr r3, [pc, #372] @ (80075d4 <_dtoa_r+0x2e4>)
|
|
800745e: eb03 03c7 add.w r3, r3, r7, lsl #3
|
|
8007462: e9d3 2300 ldrd r2, r3, [r3]
|
|
8007466: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28
|
|
800746a: f7f9 fb37 bl 8000adc <__aeabi_dcmplt>
|
|
800746e: 2800 cmp r0, #0
|
|
8007470: d049 beq.n 8007506 <_dtoa_r+0x216>
|
|
8007472: 3f01 subs r7, #1
|
|
8007474: 2300 movs r3, #0
|
|
8007476: 9310 str r3, [sp, #64] @ 0x40
|
|
8007478: 9b14 ldr r3, [sp, #80] @ 0x50
|
|
800747a: 1b9b subs r3, r3, r6
|
|
800747c: 1e5a subs r2, r3, #1
|
|
800747e: bf45 ittet mi
|
|
8007480: f1c3 0301 rsbmi r3, r3, #1
|
|
8007484: 9300 strmi r3, [sp, #0]
|
|
8007486: 2300 movpl r3, #0
|
|
8007488: 2300 movmi r3, #0
|
|
800748a: 9206 str r2, [sp, #24]
|
|
800748c: bf54 ite pl
|
|
800748e: 9300 strpl r3, [sp, #0]
|
|
8007490: 9306 strmi r3, [sp, #24]
|
|
8007492: 2f00 cmp r7, #0
|
|
8007494: db39 blt.n 800750a <_dtoa_r+0x21a>
|
|
8007496: 9b06 ldr r3, [sp, #24]
|
|
8007498: 970d str r7, [sp, #52] @ 0x34
|
|
800749a: 443b add r3, r7
|
|
800749c: 9306 str r3, [sp, #24]
|
|
800749e: 2300 movs r3, #0
|
|
80074a0: 9308 str r3, [sp, #32]
|
|
80074a2: 9b07 ldr r3, [sp, #28]
|
|
80074a4: 2b09 cmp r3, #9
|
|
80074a6: d863 bhi.n 8007570 <_dtoa_r+0x280>
|
|
80074a8: 2b05 cmp r3, #5
|
|
80074aa: bfc4 itt gt
|
|
80074ac: 3b04 subgt r3, #4
|
|
80074ae: 9307 strgt r3, [sp, #28]
|
|
80074b0: 9b07 ldr r3, [sp, #28]
|
|
80074b2: f1a3 0302 sub.w r3, r3, #2
|
|
80074b6: bfcc ite gt
|
|
80074b8: 2400 movgt r4, #0
|
|
80074ba: 2401 movle r4, #1
|
|
80074bc: 2b03 cmp r3, #3
|
|
80074be: d863 bhi.n 8007588 <_dtoa_r+0x298>
|
|
80074c0: e8df f003 tbb [pc, r3]
|
|
80074c4: 2b375452 .word 0x2b375452
|
|
80074c8: e9dd 6314 ldrd r6, r3, [sp, #80] @ 0x50
|
|
80074cc: 441e add r6, r3
|
|
80074ce: f206 4332 addw r3, r6, #1074 @ 0x432
|
|
80074d2: 2b20 cmp r3, #32
|
|
80074d4: bfc1 itttt gt
|
|
80074d6: f1c3 0340 rsbgt r3, r3, #64 @ 0x40
|
|
80074da: 409f lslgt r7, r3
|
|
80074dc: f206 4312 addwgt r3, r6, #1042 @ 0x412
|
|
80074e0: fa24 f303 lsrgt.w r3, r4, r3
|
|
80074e4: bfd6 itet le
|
|
80074e6: f1c3 0320 rsble r3, r3, #32
|
|
80074ea: ea47 0003 orrgt.w r0, r7, r3
|
|
80074ee: fa04 f003 lslle.w r0, r4, r3
|
|
80074f2: f7f9 f807 bl 8000504 <__aeabi_ui2d>
|
|
80074f6: 2201 movs r2, #1
|
|
80074f8: f1a1 73f8 sub.w r3, r1, #32505856 @ 0x1f00000
|
|
80074fc: 3e01 subs r6, #1
|
|
80074fe: 9212 str r2, [sp, #72] @ 0x48
|
|
8007500: e776 b.n 80073f0 <_dtoa_r+0x100>
|
|
8007502: 2301 movs r3, #1
|
|
8007504: e7b7 b.n 8007476 <_dtoa_r+0x186>
|
|
8007506: 9010 str r0, [sp, #64] @ 0x40
|
|
8007508: e7b6 b.n 8007478 <_dtoa_r+0x188>
|
|
800750a: 9b00 ldr r3, [sp, #0]
|
|
800750c: 1bdb subs r3, r3, r7
|
|
800750e: 9300 str r3, [sp, #0]
|
|
8007510: 427b negs r3, r7
|
|
8007512: 9308 str r3, [sp, #32]
|
|
8007514: 2300 movs r3, #0
|
|
8007516: 930d str r3, [sp, #52] @ 0x34
|
|
8007518: e7c3 b.n 80074a2 <_dtoa_r+0x1b2>
|
|
800751a: 2301 movs r3, #1
|
|
800751c: 9309 str r3, [sp, #36] @ 0x24
|
|
800751e: 9b0c ldr r3, [sp, #48] @ 0x30
|
|
8007520: eb07 0b03 add.w fp, r7, r3
|
|
8007524: f10b 0301 add.w r3, fp, #1
|
|
8007528: 2b01 cmp r3, #1
|
|
800752a: 9303 str r3, [sp, #12]
|
|
800752c: bfb8 it lt
|
|
800752e: 2301 movlt r3, #1
|
|
8007530: e006 b.n 8007540 <_dtoa_r+0x250>
|
|
8007532: 2301 movs r3, #1
|
|
8007534: 9309 str r3, [sp, #36] @ 0x24
|
|
8007536: 9b0c ldr r3, [sp, #48] @ 0x30
|
|
8007538: 2b00 cmp r3, #0
|
|
800753a: dd28 ble.n 800758e <_dtoa_r+0x29e>
|
|
800753c: 469b mov fp, r3
|
|
800753e: 9303 str r3, [sp, #12]
|
|
8007540: f8d9 001c ldr.w r0, [r9, #28]
|
|
8007544: 2100 movs r1, #0
|
|
8007546: 2204 movs r2, #4
|
|
8007548: f102 0514 add.w r5, r2, #20
|
|
800754c: 429d cmp r5, r3
|
|
800754e: d926 bls.n 800759e <_dtoa_r+0x2ae>
|
|
8007550: 6041 str r1, [r0, #4]
|
|
8007552: 4648 mov r0, r9
|
|
8007554: f000 fd9c bl 8008090 <_Balloc>
|
|
8007558: 4682 mov sl, r0
|
|
800755a: 2800 cmp r0, #0
|
|
800755c: d142 bne.n 80075e4 <_dtoa_r+0x2f4>
|
|
800755e: 4b1e ldr r3, [pc, #120] @ (80075d8 <_dtoa_r+0x2e8>)
|
|
8007560: 4602 mov r2, r0
|
|
8007562: f240 11af movw r1, #431 @ 0x1af
|
|
8007566: e6da b.n 800731e <_dtoa_r+0x2e>
|
|
8007568: 2300 movs r3, #0
|
|
800756a: e7e3 b.n 8007534 <_dtoa_r+0x244>
|
|
800756c: 2300 movs r3, #0
|
|
800756e: e7d5 b.n 800751c <_dtoa_r+0x22c>
|
|
8007570: 2401 movs r4, #1
|
|
8007572: 2300 movs r3, #0
|
|
8007574: 9307 str r3, [sp, #28]
|
|
8007576: 9409 str r4, [sp, #36] @ 0x24
|
|
8007578: f04f 3bff mov.w fp, #4294967295 @ 0xffffffff
|
|
800757c: 2200 movs r2, #0
|
|
800757e: f8cd b00c str.w fp, [sp, #12]
|
|
8007582: 2312 movs r3, #18
|
|
8007584: 920c str r2, [sp, #48] @ 0x30
|
|
8007586: e7db b.n 8007540 <_dtoa_r+0x250>
|
|
8007588: 2301 movs r3, #1
|
|
800758a: 9309 str r3, [sp, #36] @ 0x24
|
|
800758c: e7f4 b.n 8007578 <_dtoa_r+0x288>
|
|
800758e: f04f 0b01 mov.w fp, #1
|
|
8007592: f8cd b00c str.w fp, [sp, #12]
|
|
8007596: 465b mov r3, fp
|
|
8007598: f8cd b030 str.w fp, [sp, #48] @ 0x30
|
|
800759c: e7d0 b.n 8007540 <_dtoa_r+0x250>
|
|
800759e: 3101 adds r1, #1
|
|
80075a0: 0052 lsls r2, r2, #1
|
|
80075a2: e7d1 b.n 8007548 <_dtoa_r+0x258>
|
|
80075a4: f3af 8000 nop.w
|
|
80075a8: 636f4361 .word 0x636f4361
|
|
80075ac: 3fd287a7 .word 0x3fd287a7
|
|
80075b0: 8b60c8b3 .word 0x8b60c8b3
|
|
80075b4: 3fc68a28 .word 0x3fc68a28
|
|
80075b8: 509f79fb .word 0x509f79fb
|
|
80075bc: 3fd34413 .word 0x3fd34413
|
|
80075c0: 08009381 .word 0x08009381
|
|
80075c4: 08009398 .word 0x08009398
|
|
80075c8: 7ff00000 .word 0x7ff00000
|
|
80075cc: 08009351 .word 0x08009351
|
|
80075d0: 3ff80000 .word 0x3ff80000
|
|
80075d4: 080094e8 .word 0x080094e8
|
|
80075d8: 080093f0 .word 0x080093f0
|
|
80075dc: 0800937d .word 0x0800937d
|
|
80075e0: 08009350 .word 0x08009350
|
|
80075e4: f8d9 301c ldr.w r3, [r9, #28]
|
|
80075e8: 6018 str r0, [r3, #0]
|
|
80075ea: 9b03 ldr r3, [sp, #12]
|
|
80075ec: 2b0e cmp r3, #14
|
|
80075ee: f200 80a1 bhi.w 8007734 <_dtoa_r+0x444>
|
|
80075f2: 2c00 cmp r4, #0
|
|
80075f4: f000 809e beq.w 8007734 <_dtoa_r+0x444>
|
|
80075f8: 2f00 cmp r7, #0
|
|
80075fa: dd33 ble.n 8007664 <_dtoa_r+0x374>
|
|
80075fc: 4b9c ldr r3, [pc, #624] @ (8007870 <_dtoa_r+0x580>)
|
|
80075fe: f007 020f and.w r2, r7, #15
|
|
8007602: eb03 03c2 add.w r3, r3, r2, lsl #3
|
|
8007606: ed93 7b00 vldr d7, [r3]
|
|
800760a: 05f8 lsls r0, r7, #23
|
|
800760c: ed8d 7b0e vstr d7, [sp, #56] @ 0x38
|
|
8007610: ea4f 1427 mov.w r4, r7, asr #4
|
|
8007614: d516 bpl.n 8007644 <_dtoa_r+0x354>
|
|
8007616: 4b97 ldr r3, [pc, #604] @ (8007874 <_dtoa_r+0x584>)
|
|
8007618: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28
|
|
800761c: e9d3 2308 ldrd r2, r3, [r3, #32]
|
|
8007620: f7f9 f914 bl 800084c <__aeabi_ddiv>
|
|
8007624: e9cd 0104 strd r0, r1, [sp, #16]
|
|
8007628: f004 040f and.w r4, r4, #15
|
|
800762c: 2603 movs r6, #3
|
|
800762e: 4d91 ldr r5, [pc, #580] @ (8007874 <_dtoa_r+0x584>)
|
|
8007630: b954 cbnz r4, 8007648 <_dtoa_r+0x358>
|
|
8007632: e9dd 230e ldrd r2, r3, [sp, #56] @ 0x38
|
|
8007636: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
800763a: f7f9 f907 bl 800084c <__aeabi_ddiv>
|
|
800763e: e9cd 0104 strd r0, r1, [sp, #16]
|
|
8007642: e028 b.n 8007696 <_dtoa_r+0x3a6>
|
|
8007644: 2602 movs r6, #2
|
|
8007646: e7f2 b.n 800762e <_dtoa_r+0x33e>
|
|
8007648: 07e1 lsls r1, r4, #31
|
|
800764a: d508 bpl.n 800765e <_dtoa_r+0x36e>
|
|
800764c: e9dd 010e ldrd r0, r1, [sp, #56] @ 0x38
|
|
8007650: e9d5 2300 ldrd r2, r3, [r5]
|
|
8007654: f7f8 ffd0 bl 80005f8 <__aeabi_dmul>
|
|
8007658: e9cd 010e strd r0, r1, [sp, #56] @ 0x38
|
|
800765c: 3601 adds r6, #1
|
|
800765e: 1064 asrs r4, r4, #1
|
|
8007660: 3508 adds r5, #8
|
|
8007662: e7e5 b.n 8007630 <_dtoa_r+0x340>
|
|
8007664: f000 80af beq.w 80077c6 <_dtoa_r+0x4d6>
|
|
8007668: 427c negs r4, r7
|
|
800766a: 4b81 ldr r3, [pc, #516] @ (8007870 <_dtoa_r+0x580>)
|
|
800766c: 4d81 ldr r5, [pc, #516] @ (8007874 <_dtoa_r+0x584>)
|
|
800766e: f004 020f and.w r2, r4, #15
|
|
8007672: eb03 03c2 add.w r3, r3, r2, lsl #3
|
|
8007676: e9d3 2300 ldrd r2, r3, [r3]
|
|
800767a: e9dd 010a ldrd r0, r1, [sp, #40] @ 0x28
|
|
800767e: f7f8 ffbb bl 80005f8 <__aeabi_dmul>
|
|
8007682: e9cd 0104 strd r0, r1, [sp, #16]
|
|
8007686: 1124 asrs r4, r4, #4
|
|
8007688: 2300 movs r3, #0
|
|
800768a: 2602 movs r6, #2
|
|
800768c: 2c00 cmp r4, #0
|
|
800768e: f040 808f bne.w 80077b0 <_dtoa_r+0x4c0>
|
|
8007692: 2b00 cmp r3, #0
|
|
8007694: d1d3 bne.n 800763e <_dtoa_r+0x34e>
|
|
8007696: 9b10 ldr r3, [sp, #64] @ 0x40
|
|
8007698: e9dd 4504 ldrd r4, r5, [sp, #16]
|
|
800769c: 2b00 cmp r3, #0
|
|
800769e: f000 8094 beq.w 80077ca <_dtoa_r+0x4da>
|
|
80076a2: 4b75 ldr r3, [pc, #468] @ (8007878 <_dtoa_r+0x588>)
|
|
80076a4: 2200 movs r2, #0
|
|
80076a6: 4620 mov r0, r4
|
|
80076a8: 4629 mov r1, r5
|
|
80076aa: f7f9 fa17 bl 8000adc <__aeabi_dcmplt>
|
|
80076ae: 2800 cmp r0, #0
|
|
80076b0: f000 808b beq.w 80077ca <_dtoa_r+0x4da>
|
|
80076b4: 9b03 ldr r3, [sp, #12]
|
|
80076b6: 2b00 cmp r3, #0
|
|
80076b8: f000 8087 beq.w 80077ca <_dtoa_r+0x4da>
|
|
80076bc: f1bb 0f00 cmp.w fp, #0
|
|
80076c0: dd34 ble.n 800772c <_dtoa_r+0x43c>
|
|
80076c2: 4620 mov r0, r4
|
|
80076c4: 4b6d ldr r3, [pc, #436] @ (800787c <_dtoa_r+0x58c>)
|
|
80076c6: 2200 movs r2, #0
|
|
80076c8: 4629 mov r1, r5
|
|
80076ca: f7f8 ff95 bl 80005f8 <__aeabi_dmul>
|
|
80076ce: e9cd 0104 strd r0, r1, [sp, #16]
|
|
80076d2: f107 38ff add.w r8, r7, #4294967295 @ 0xffffffff
|
|
80076d6: 3601 adds r6, #1
|
|
80076d8: 465c mov r4, fp
|
|
80076da: 4630 mov r0, r6
|
|
80076dc: f7f8 ff22 bl 8000524 <__aeabi_i2d>
|
|
80076e0: e9dd 2304 ldrd r2, r3, [sp, #16]
|
|
80076e4: f7f8 ff88 bl 80005f8 <__aeabi_dmul>
|
|
80076e8: 4b65 ldr r3, [pc, #404] @ (8007880 <_dtoa_r+0x590>)
|
|
80076ea: 2200 movs r2, #0
|
|
80076ec: f7f8 fdce bl 800028c <__adddf3>
|
|
80076f0: 4605 mov r5, r0
|
|
80076f2: f1a1 7650 sub.w r6, r1, #54525952 @ 0x3400000
|
|
80076f6: 2c00 cmp r4, #0
|
|
80076f8: d16a bne.n 80077d0 <_dtoa_r+0x4e0>
|
|
80076fa: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
80076fe: 4b61 ldr r3, [pc, #388] @ (8007884 <_dtoa_r+0x594>)
|
|
8007700: 2200 movs r2, #0
|
|
8007702: f7f8 fdc1 bl 8000288 <__aeabi_dsub>
|
|
8007706: 4602 mov r2, r0
|
|
8007708: 460b mov r3, r1
|
|
800770a: e9cd 2304 strd r2, r3, [sp, #16]
|
|
800770e: 462a mov r2, r5
|
|
8007710: 4633 mov r3, r6
|
|
8007712: f7f9 fa01 bl 8000b18 <__aeabi_dcmpgt>
|
|
8007716: 2800 cmp r0, #0
|
|
8007718: f040 8298 bne.w 8007c4c <_dtoa_r+0x95c>
|
|
800771c: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
8007720: 462a mov r2, r5
|
|
8007722: f106 4300 add.w r3, r6, #2147483648 @ 0x80000000
|
|
8007726: f7f9 f9d9 bl 8000adc <__aeabi_dcmplt>
|
|
800772a: bb38 cbnz r0, 800777c <_dtoa_r+0x48c>
|
|
800772c: e9dd 340a ldrd r3, r4, [sp, #40] @ 0x28
|
|
8007730: e9cd 3404 strd r3, r4, [sp, #16]
|
|
8007734: 9b15 ldr r3, [sp, #84] @ 0x54
|
|
8007736: 2b00 cmp r3, #0
|
|
8007738: f2c0 8157 blt.w 80079ea <_dtoa_r+0x6fa>
|
|
800773c: 2f0e cmp r7, #14
|
|
800773e: f300 8154 bgt.w 80079ea <_dtoa_r+0x6fa>
|
|
8007742: 4b4b ldr r3, [pc, #300] @ (8007870 <_dtoa_r+0x580>)
|
|
8007744: eb03 03c7 add.w r3, r3, r7, lsl #3
|
|
8007748: ed93 7b00 vldr d7, [r3]
|
|
800774c: 9b0c ldr r3, [sp, #48] @ 0x30
|
|
800774e: 2b00 cmp r3, #0
|
|
8007750: ed8d 7b00 vstr d7, [sp]
|
|
8007754: f280 80e5 bge.w 8007922 <_dtoa_r+0x632>
|
|
8007758: 9b03 ldr r3, [sp, #12]
|
|
800775a: 2b00 cmp r3, #0
|
|
800775c: f300 80e1 bgt.w 8007922 <_dtoa_r+0x632>
|
|
8007760: d10c bne.n 800777c <_dtoa_r+0x48c>
|
|
8007762: 4b48 ldr r3, [pc, #288] @ (8007884 <_dtoa_r+0x594>)
|
|
8007764: 2200 movs r2, #0
|
|
8007766: ec51 0b17 vmov r0, r1, d7
|
|
800776a: f7f8 ff45 bl 80005f8 <__aeabi_dmul>
|
|
800776e: e9dd 2304 ldrd r2, r3, [sp, #16]
|
|
8007772: f7f9 f9c7 bl 8000b04 <__aeabi_dcmpge>
|
|
8007776: 2800 cmp r0, #0
|
|
8007778: f000 8266 beq.w 8007c48 <_dtoa_r+0x958>
|
|
800777c: 2400 movs r4, #0
|
|
800777e: 4625 mov r5, r4
|
|
8007780: 9b0c ldr r3, [sp, #48] @ 0x30
|
|
8007782: 4656 mov r6, sl
|
|
8007784: ea6f 0803 mvn.w r8, r3
|
|
8007788: 2700 movs r7, #0
|
|
800778a: 4621 mov r1, r4
|
|
800778c: 4648 mov r0, r9
|
|
800778e: f000 fcbf bl 8008110 <_Bfree>
|
|
8007792: 2d00 cmp r5, #0
|
|
8007794: f000 80bd beq.w 8007912 <_dtoa_r+0x622>
|
|
8007798: b12f cbz r7, 80077a6 <_dtoa_r+0x4b6>
|
|
800779a: 42af cmp r7, r5
|
|
800779c: d003 beq.n 80077a6 <_dtoa_r+0x4b6>
|
|
800779e: 4639 mov r1, r7
|
|
80077a0: 4648 mov r0, r9
|
|
80077a2: f000 fcb5 bl 8008110 <_Bfree>
|
|
80077a6: 4629 mov r1, r5
|
|
80077a8: 4648 mov r0, r9
|
|
80077aa: f000 fcb1 bl 8008110 <_Bfree>
|
|
80077ae: e0b0 b.n 8007912 <_dtoa_r+0x622>
|
|
80077b0: 07e2 lsls r2, r4, #31
|
|
80077b2: d505 bpl.n 80077c0 <_dtoa_r+0x4d0>
|
|
80077b4: e9d5 2300 ldrd r2, r3, [r5]
|
|
80077b8: f7f8 ff1e bl 80005f8 <__aeabi_dmul>
|
|
80077bc: 3601 adds r6, #1
|
|
80077be: 2301 movs r3, #1
|
|
80077c0: 1064 asrs r4, r4, #1
|
|
80077c2: 3508 adds r5, #8
|
|
80077c4: e762 b.n 800768c <_dtoa_r+0x39c>
|
|
80077c6: 2602 movs r6, #2
|
|
80077c8: e765 b.n 8007696 <_dtoa_r+0x3a6>
|
|
80077ca: 9c03 ldr r4, [sp, #12]
|
|
80077cc: 46b8 mov r8, r7
|
|
80077ce: e784 b.n 80076da <_dtoa_r+0x3ea>
|
|
80077d0: 4b27 ldr r3, [pc, #156] @ (8007870 <_dtoa_r+0x580>)
|
|
80077d2: 9909 ldr r1, [sp, #36] @ 0x24
|
|
80077d4: eb03 03c4 add.w r3, r3, r4, lsl #3
|
|
80077d8: e953 2302 ldrd r2, r3, [r3, #-8]
|
|
80077dc: 4454 add r4, sl
|
|
80077de: 2900 cmp r1, #0
|
|
80077e0: d054 beq.n 800788c <_dtoa_r+0x59c>
|
|
80077e2: 4929 ldr r1, [pc, #164] @ (8007888 <_dtoa_r+0x598>)
|
|
80077e4: 2000 movs r0, #0
|
|
80077e6: f7f9 f831 bl 800084c <__aeabi_ddiv>
|
|
80077ea: 4633 mov r3, r6
|
|
80077ec: 462a mov r2, r5
|
|
80077ee: f7f8 fd4b bl 8000288 <__aeabi_dsub>
|
|
80077f2: e9cd 010e strd r0, r1, [sp, #56] @ 0x38
|
|
80077f6: 4656 mov r6, sl
|
|
80077f8: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
80077fc: f7f9 f9ac bl 8000b58 <__aeabi_d2iz>
|
|
8007800: 4605 mov r5, r0
|
|
8007802: f7f8 fe8f bl 8000524 <__aeabi_i2d>
|
|
8007806: 4602 mov r2, r0
|
|
8007808: 460b mov r3, r1
|
|
800780a: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
800780e: f7f8 fd3b bl 8000288 <__aeabi_dsub>
|
|
8007812: 3530 adds r5, #48 @ 0x30
|
|
8007814: 4602 mov r2, r0
|
|
8007816: 460b mov r3, r1
|
|
8007818: e9cd 2304 strd r2, r3, [sp, #16]
|
|
800781c: f806 5b01 strb.w r5, [r6], #1
|
|
8007820: e9dd 230e ldrd r2, r3, [sp, #56] @ 0x38
|
|
8007824: f7f9 f95a bl 8000adc <__aeabi_dcmplt>
|
|
8007828: 2800 cmp r0, #0
|
|
800782a: d172 bne.n 8007912 <_dtoa_r+0x622>
|
|
800782c: e9dd 2304 ldrd r2, r3, [sp, #16]
|
|
8007830: 4911 ldr r1, [pc, #68] @ (8007878 <_dtoa_r+0x588>)
|
|
8007832: 2000 movs r0, #0
|
|
8007834: f7f8 fd28 bl 8000288 <__aeabi_dsub>
|
|
8007838: e9dd 230e ldrd r2, r3, [sp, #56] @ 0x38
|
|
800783c: f7f9 f94e bl 8000adc <__aeabi_dcmplt>
|
|
8007840: 2800 cmp r0, #0
|
|
8007842: f040 80b4 bne.w 80079ae <_dtoa_r+0x6be>
|
|
8007846: 42a6 cmp r6, r4
|
|
8007848: f43f af70 beq.w 800772c <_dtoa_r+0x43c>
|
|
800784c: e9dd 010e ldrd r0, r1, [sp, #56] @ 0x38
|
|
8007850: 4b0a ldr r3, [pc, #40] @ (800787c <_dtoa_r+0x58c>)
|
|
8007852: 2200 movs r2, #0
|
|
8007854: f7f8 fed0 bl 80005f8 <__aeabi_dmul>
|
|
8007858: 4b08 ldr r3, [pc, #32] @ (800787c <_dtoa_r+0x58c>)
|
|
800785a: e9cd 010e strd r0, r1, [sp, #56] @ 0x38
|
|
800785e: 2200 movs r2, #0
|
|
8007860: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
8007864: f7f8 fec8 bl 80005f8 <__aeabi_dmul>
|
|
8007868: e9cd 0104 strd r0, r1, [sp, #16]
|
|
800786c: e7c4 b.n 80077f8 <_dtoa_r+0x508>
|
|
800786e: bf00 nop
|
|
8007870: 080094e8 .word 0x080094e8
|
|
8007874: 080094c0 .word 0x080094c0
|
|
8007878: 3ff00000 .word 0x3ff00000
|
|
800787c: 40240000 .word 0x40240000
|
|
8007880: 401c0000 .word 0x401c0000
|
|
8007884: 40140000 .word 0x40140000
|
|
8007888: 3fe00000 .word 0x3fe00000
|
|
800788c: 4631 mov r1, r6
|
|
800788e: 4628 mov r0, r5
|
|
8007890: f7f8 feb2 bl 80005f8 <__aeabi_dmul>
|
|
8007894: e9cd 010e strd r0, r1, [sp, #56] @ 0x38
|
|
8007898: 9413 str r4, [sp, #76] @ 0x4c
|
|
800789a: 4656 mov r6, sl
|
|
800789c: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
80078a0: f7f9 f95a bl 8000b58 <__aeabi_d2iz>
|
|
80078a4: 4605 mov r5, r0
|
|
80078a6: f7f8 fe3d bl 8000524 <__aeabi_i2d>
|
|
80078aa: 4602 mov r2, r0
|
|
80078ac: 460b mov r3, r1
|
|
80078ae: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
80078b2: f7f8 fce9 bl 8000288 <__aeabi_dsub>
|
|
80078b6: 3530 adds r5, #48 @ 0x30
|
|
80078b8: f806 5b01 strb.w r5, [r6], #1
|
|
80078bc: 4602 mov r2, r0
|
|
80078be: 460b mov r3, r1
|
|
80078c0: 42a6 cmp r6, r4
|
|
80078c2: e9cd 2304 strd r2, r3, [sp, #16]
|
|
80078c6: f04f 0200 mov.w r2, #0
|
|
80078ca: d124 bne.n 8007916 <_dtoa_r+0x626>
|
|
80078cc: 4baf ldr r3, [pc, #700] @ (8007b8c <_dtoa_r+0x89c>)
|
|
80078ce: e9dd 010e ldrd r0, r1, [sp, #56] @ 0x38
|
|
80078d2: f7f8 fcdb bl 800028c <__adddf3>
|
|
80078d6: 4602 mov r2, r0
|
|
80078d8: 460b mov r3, r1
|
|
80078da: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
80078de: f7f9 f91b bl 8000b18 <__aeabi_dcmpgt>
|
|
80078e2: 2800 cmp r0, #0
|
|
80078e4: d163 bne.n 80079ae <_dtoa_r+0x6be>
|
|
80078e6: e9dd 230e ldrd r2, r3, [sp, #56] @ 0x38
|
|
80078ea: 49a8 ldr r1, [pc, #672] @ (8007b8c <_dtoa_r+0x89c>)
|
|
80078ec: 2000 movs r0, #0
|
|
80078ee: f7f8 fccb bl 8000288 <__aeabi_dsub>
|
|
80078f2: 4602 mov r2, r0
|
|
80078f4: 460b mov r3, r1
|
|
80078f6: e9dd 0104 ldrd r0, r1, [sp, #16]
|
|
80078fa: f7f9 f8ef bl 8000adc <__aeabi_dcmplt>
|
|
80078fe: 2800 cmp r0, #0
|
|
8007900: f43f af14 beq.w 800772c <_dtoa_r+0x43c>
|
|
8007904: 9e13 ldr r6, [sp, #76] @ 0x4c
|
|
8007906: 1e73 subs r3, r6, #1
|
|
8007908: 9313 str r3, [sp, #76] @ 0x4c
|
|
800790a: f816 3c01 ldrb.w r3, [r6, #-1]
|
|
800790e: 2b30 cmp r3, #48 @ 0x30
|
|
8007910: d0f8 beq.n 8007904 <_dtoa_r+0x614>
|
|
8007912: 4647 mov r7, r8
|
|
8007914: e03b b.n 800798e <_dtoa_r+0x69e>
|
|
8007916: 4b9e ldr r3, [pc, #632] @ (8007b90 <_dtoa_r+0x8a0>)
|
|
8007918: f7f8 fe6e bl 80005f8 <__aeabi_dmul>
|
|
800791c: e9cd 0104 strd r0, r1, [sp, #16]
|
|
8007920: e7bc b.n 800789c <_dtoa_r+0x5ac>
|
|
8007922: e9dd 4504 ldrd r4, r5, [sp, #16]
|
|
8007926: 4656 mov r6, sl
|
|
8007928: e9dd 2300 ldrd r2, r3, [sp]
|
|
800792c: 4620 mov r0, r4
|
|
800792e: 4629 mov r1, r5
|
|
8007930: f7f8 ff8c bl 800084c <__aeabi_ddiv>
|
|
8007934: f7f9 f910 bl 8000b58 <__aeabi_d2iz>
|
|
8007938: 4680 mov r8, r0
|
|
800793a: f7f8 fdf3 bl 8000524 <__aeabi_i2d>
|
|
800793e: e9dd 2300 ldrd r2, r3, [sp]
|
|
8007942: f7f8 fe59 bl 80005f8 <__aeabi_dmul>
|
|
8007946: 4602 mov r2, r0
|
|
8007948: 460b mov r3, r1
|
|
800794a: 4620 mov r0, r4
|
|
800794c: 4629 mov r1, r5
|
|
800794e: f108 0430 add.w r4, r8, #48 @ 0x30
|
|
8007952: f7f8 fc99 bl 8000288 <__aeabi_dsub>
|
|
8007956: f806 4b01 strb.w r4, [r6], #1
|
|
800795a: 9d03 ldr r5, [sp, #12]
|
|
800795c: eba6 040a sub.w r4, r6, sl
|
|
8007960: 42a5 cmp r5, r4
|
|
8007962: 4602 mov r2, r0
|
|
8007964: 460b mov r3, r1
|
|
8007966: d133 bne.n 80079d0 <_dtoa_r+0x6e0>
|
|
8007968: f7f8 fc90 bl 800028c <__adddf3>
|
|
800796c: e9dd 2300 ldrd r2, r3, [sp]
|
|
8007970: 4604 mov r4, r0
|
|
8007972: 460d mov r5, r1
|
|
8007974: f7f9 f8d0 bl 8000b18 <__aeabi_dcmpgt>
|
|
8007978: b9c0 cbnz r0, 80079ac <_dtoa_r+0x6bc>
|
|
800797a: e9dd 2300 ldrd r2, r3, [sp]
|
|
800797e: 4620 mov r0, r4
|
|
8007980: 4629 mov r1, r5
|
|
8007982: f7f9 f8a1 bl 8000ac8 <__aeabi_dcmpeq>
|
|
8007986: b110 cbz r0, 800798e <_dtoa_r+0x69e>
|
|
8007988: f018 0f01 tst.w r8, #1
|
|
800798c: d10e bne.n 80079ac <_dtoa_r+0x6bc>
|
|
800798e: 9902 ldr r1, [sp, #8]
|
|
8007990: 4648 mov r0, r9
|
|
8007992: f000 fbbd bl 8008110 <_Bfree>
|
|
8007996: 2300 movs r3, #0
|
|
8007998: 7033 strb r3, [r6, #0]
|
|
800799a: 9b11 ldr r3, [sp, #68] @ 0x44
|
|
800799c: 3701 adds r7, #1
|
|
800799e: 601f str r7, [r3, #0]
|
|
80079a0: 9b21 ldr r3, [sp, #132] @ 0x84
|
|
80079a2: 2b00 cmp r3, #0
|
|
80079a4: f000 824b beq.w 8007e3e <_dtoa_r+0xb4e>
|
|
80079a8: 601e str r6, [r3, #0]
|
|
80079aa: e248 b.n 8007e3e <_dtoa_r+0xb4e>
|
|
80079ac: 46b8 mov r8, r7
|
|
80079ae: 4633 mov r3, r6
|
|
80079b0: 461e mov r6, r3
|
|
80079b2: f813 2d01 ldrb.w r2, [r3, #-1]!
|
|
80079b6: 2a39 cmp r2, #57 @ 0x39
|
|
80079b8: d106 bne.n 80079c8 <_dtoa_r+0x6d8>
|
|
80079ba: 459a cmp sl, r3
|
|
80079bc: d1f8 bne.n 80079b0 <_dtoa_r+0x6c0>
|
|
80079be: 2230 movs r2, #48 @ 0x30
|
|
80079c0: f108 0801 add.w r8, r8, #1
|
|
80079c4: f88a 2000 strb.w r2, [sl]
|
|
80079c8: 781a ldrb r2, [r3, #0]
|
|
80079ca: 3201 adds r2, #1
|
|
80079cc: 701a strb r2, [r3, #0]
|
|
80079ce: e7a0 b.n 8007912 <_dtoa_r+0x622>
|
|
80079d0: 4b6f ldr r3, [pc, #444] @ (8007b90 <_dtoa_r+0x8a0>)
|
|
80079d2: 2200 movs r2, #0
|
|
80079d4: f7f8 fe10 bl 80005f8 <__aeabi_dmul>
|
|
80079d8: 2200 movs r2, #0
|
|
80079da: 2300 movs r3, #0
|
|
80079dc: 4604 mov r4, r0
|
|
80079de: 460d mov r5, r1
|
|
80079e0: f7f9 f872 bl 8000ac8 <__aeabi_dcmpeq>
|
|
80079e4: 2800 cmp r0, #0
|
|
80079e6: d09f beq.n 8007928 <_dtoa_r+0x638>
|
|
80079e8: e7d1 b.n 800798e <_dtoa_r+0x69e>
|
|
80079ea: 9a09 ldr r2, [sp, #36] @ 0x24
|
|
80079ec: 2a00 cmp r2, #0
|
|
80079ee: f000 80ea beq.w 8007bc6 <_dtoa_r+0x8d6>
|
|
80079f2: 9a07 ldr r2, [sp, #28]
|
|
80079f4: 2a01 cmp r2, #1
|
|
80079f6: f300 80cd bgt.w 8007b94 <_dtoa_r+0x8a4>
|
|
80079fa: 9a12 ldr r2, [sp, #72] @ 0x48
|
|
80079fc: 2a00 cmp r2, #0
|
|
80079fe: f000 80c1 beq.w 8007b84 <_dtoa_r+0x894>
|
|
8007a02: f203 4333 addw r3, r3, #1075 @ 0x433
|
|
8007a06: 9c08 ldr r4, [sp, #32]
|
|
8007a08: 9e00 ldr r6, [sp, #0]
|
|
8007a0a: 9a00 ldr r2, [sp, #0]
|
|
8007a0c: 441a add r2, r3
|
|
8007a0e: 9200 str r2, [sp, #0]
|
|
8007a10: 9a06 ldr r2, [sp, #24]
|
|
8007a12: 2101 movs r1, #1
|
|
8007a14: 441a add r2, r3
|
|
8007a16: 4648 mov r0, r9
|
|
8007a18: 9206 str r2, [sp, #24]
|
|
8007a1a: f000 fc2d bl 8008278 <__i2b>
|
|
8007a1e: 4605 mov r5, r0
|
|
8007a20: b166 cbz r6, 8007a3c <_dtoa_r+0x74c>
|
|
8007a22: 9b06 ldr r3, [sp, #24]
|
|
8007a24: 2b00 cmp r3, #0
|
|
8007a26: dd09 ble.n 8007a3c <_dtoa_r+0x74c>
|
|
8007a28: 42b3 cmp r3, r6
|
|
8007a2a: 9a00 ldr r2, [sp, #0]
|
|
8007a2c: bfa8 it ge
|
|
8007a2e: 4633 movge r3, r6
|
|
8007a30: 1ad2 subs r2, r2, r3
|
|
8007a32: 9200 str r2, [sp, #0]
|
|
8007a34: 9a06 ldr r2, [sp, #24]
|
|
8007a36: 1af6 subs r6, r6, r3
|
|
8007a38: 1ad3 subs r3, r2, r3
|
|
8007a3a: 9306 str r3, [sp, #24]
|
|
8007a3c: 9b08 ldr r3, [sp, #32]
|
|
8007a3e: b30b cbz r3, 8007a84 <_dtoa_r+0x794>
|
|
8007a40: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8007a42: 2b00 cmp r3, #0
|
|
8007a44: f000 80c6 beq.w 8007bd4 <_dtoa_r+0x8e4>
|
|
8007a48: 2c00 cmp r4, #0
|
|
8007a4a: f000 80c0 beq.w 8007bce <_dtoa_r+0x8de>
|
|
8007a4e: 4629 mov r1, r5
|
|
8007a50: 4622 mov r2, r4
|
|
8007a52: 4648 mov r0, r9
|
|
8007a54: f000 fcc8 bl 80083e8 <__pow5mult>
|
|
8007a58: 9a02 ldr r2, [sp, #8]
|
|
8007a5a: 4601 mov r1, r0
|
|
8007a5c: 4605 mov r5, r0
|
|
8007a5e: 4648 mov r0, r9
|
|
8007a60: f000 fc20 bl 80082a4 <__multiply>
|
|
8007a64: 9902 ldr r1, [sp, #8]
|
|
8007a66: 4680 mov r8, r0
|
|
8007a68: 4648 mov r0, r9
|
|
8007a6a: f000 fb51 bl 8008110 <_Bfree>
|
|
8007a6e: 9b08 ldr r3, [sp, #32]
|
|
8007a70: 1b1b subs r3, r3, r4
|
|
8007a72: 9308 str r3, [sp, #32]
|
|
8007a74: f000 80b1 beq.w 8007bda <_dtoa_r+0x8ea>
|
|
8007a78: 9a08 ldr r2, [sp, #32]
|
|
8007a7a: 4641 mov r1, r8
|
|
8007a7c: 4648 mov r0, r9
|
|
8007a7e: f000 fcb3 bl 80083e8 <__pow5mult>
|
|
8007a82: 9002 str r0, [sp, #8]
|
|
8007a84: 2101 movs r1, #1
|
|
8007a86: 4648 mov r0, r9
|
|
8007a88: f000 fbf6 bl 8008278 <__i2b>
|
|
8007a8c: 9b0d ldr r3, [sp, #52] @ 0x34
|
|
8007a8e: 4604 mov r4, r0
|
|
8007a90: 2b00 cmp r3, #0
|
|
8007a92: f000 81d8 beq.w 8007e46 <_dtoa_r+0xb56>
|
|
8007a96: 461a mov r2, r3
|
|
8007a98: 4601 mov r1, r0
|
|
8007a9a: 4648 mov r0, r9
|
|
8007a9c: f000 fca4 bl 80083e8 <__pow5mult>
|
|
8007aa0: 9b07 ldr r3, [sp, #28]
|
|
8007aa2: 2b01 cmp r3, #1
|
|
8007aa4: 4604 mov r4, r0
|
|
8007aa6: f300 809f bgt.w 8007be8 <_dtoa_r+0x8f8>
|
|
8007aaa: 9b04 ldr r3, [sp, #16]
|
|
8007aac: 2b00 cmp r3, #0
|
|
8007aae: f040 8097 bne.w 8007be0 <_dtoa_r+0x8f0>
|
|
8007ab2: 9b05 ldr r3, [sp, #20]
|
|
8007ab4: f3c3 0313 ubfx r3, r3, #0, #20
|
|
8007ab8: 2b00 cmp r3, #0
|
|
8007aba: f040 8093 bne.w 8007be4 <_dtoa_r+0x8f4>
|
|
8007abe: 9b05 ldr r3, [sp, #20]
|
|
8007ac0: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
|
|
8007ac4: 0d1b lsrs r3, r3, #20
|
|
8007ac6: 051b lsls r3, r3, #20
|
|
8007ac8: b133 cbz r3, 8007ad8 <_dtoa_r+0x7e8>
|
|
8007aca: 9b00 ldr r3, [sp, #0]
|
|
8007acc: 3301 adds r3, #1
|
|
8007ace: 9300 str r3, [sp, #0]
|
|
8007ad0: 9b06 ldr r3, [sp, #24]
|
|
8007ad2: 3301 adds r3, #1
|
|
8007ad4: 9306 str r3, [sp, #24]
|
|
8007ad6: 2301 movs r3, #1
|
|
8007ad8: 9308 str r3, [sp, #32]
|
|
8007ada: 9b0d ldr r3, [sp, #52] @ 0x34
|
|
8007adc: 2b00 cmp r3, #0
|
|
8007ade: f000 81b8 beq.w 8007e52 <_dtoa_r+0xb62>
|
|
8007ae2: 6923 ldr r3, [r4, #16]
|
|
8007ae4: eb04 0383 add.w r3, r4, r3, lsl #2
|
|
8007ae8: 6918 ldr r0, [r3, #16]
|
|
8007aea: f000 fb79 bl 80081e0 <__hi0bits>
|
|
8007aee: f1c0 0020 rsb r0, r0, #32
|
|
8007af2: 9b06 ldr r3, [sp, #24]
|
|
8007af4: 4418 add r0, r3
|
|
8007af6: f010 001f ands.w r0, r0, #31
|
|
8007afa: f000 8082 beq.w 8007c02 <_dtoa_r+0x912>
|
|
8007afe: f1c0 0320 rsb r3, r0, #32
|
|
8007b02: 2b04 cmp r3, #4
|
|
8007b04: dd73 ble.n 8007bee <_dtoa_r+0x8fe>
|
|
8007b06: 9b00 ldr r3, [sp, #0]
|
|
8007b08: f1c0 001c rsb r0, r0, #28
|
|
8007b0c: 4403 add r3, r0
|
|
8007b0e: 9300 str r3, [sp, #0]
|
|
8007b10: 9b06 ldr r3, [sp, #24]
|
|
8007b12: 4403 add r3, r0
|
|
8007b14: 4406 add r6, r0
|
|
8007b16: 9306 str r3, [sp, #24]
|
|
8007b18: 9b00 ldr r3, [sp, #0]
|
|
8007b1a: 2b00 cmp r3, #0
|
|
8007b1c: dd05 ble.n 8007b2a <_dtoa_r+0x83a>
|
|
8007b1e: 9902 ldr r1, [sp, #8]
|
|
8007b20: 461a mov r2, r3
|
|
8007b22: 4648 mov r0, r9
|
|
8007b24: f000 fcba bl 800849c <__lshift>
|
|
8007b28: 9002 str r0, [sp, #8]
|
|
8007b2a: 9b06 ldr r3, [sp, #24]
|
|
8007b2c: 2b00 cmp r3, #0
|
|
8007b2e: dd05 ble.n 8007b3c <_dtoa_r+0x84c>
|
|
8007b30: 4621 mov r1, r4
|
|
8007b32: 461a mov r2, r3
|
|
8007b34: 4648 mov r0, r9
|
|
8007b36: f000 fcb1 bl 800849c <__lshift>
|
|
8007b3a: 4604 mov r4, r0
|
|
8007b3c: 9b10 ldr r3, [sp, #64] @ 0x40
|
|
8007b3e: 2b00 cmp r3, #0
|
|
8007b40: d061 beq.n 8007c06 <_dtoa_r+0x916>
|
|
8007b42: 9802 ldr r0, [sp, #8]
|
|
8007b44: 4621 mov r1, r4
|
|
8007b46: f000 fd15 bl 8008574 <__mcmp>
|
|
8007b4a: 2800 cmp r0, #0
|
|
8007b4c: da5b bge.n 8007c06 <_dtoa_r+0x916>
|
|
8007b4e: 2300 movs r3, #0
|
|
8007b50: 9902 ldr r1, [sp, #8]
|
|
8007b52: 220a movs r2, #10
|
|
8007b54: 4648 mov r0, r9
|
|
8007b56: f000 fafd bl 8008154 <__multadd>
|
|
8007b5a: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8007b5c: 9002 str r0, [sp, #8]
|
|
8007b5e: f107 38ff add.w r8, r7, #4294967295 @ 0xffffffff
|
|
8007b62: 2b00 cmp r3, #0
|
|
8007b64: f000 8177 beq.w 8007e56 <_dtoa_r+0xb66>
|
|
8007b68: 4629 mov r1, r5
|
|
8007b6a: 2300 movs r3, #0
|
|
8007b6c: 220a movs r2, #10
|
|
8007b6e: 4648 mov r0, r9
|
|
8007b70: f000 faf0 bl 8008154 <__multadd>
|
|
8007b74: f1bb 0f00 cmp.w fp, #0
|
|
8007b78: 4605 mov r5, r0
|
|
8007b7a: dc6f bgt.n 8007c5c <_dtoa_r+0x96c>
|
|
8007b7c: 9b07 ldr r3, [sp, #28]
|
|
8007b7e: 2b02 cmp r3, #2
|
|
8007b80: dc49 bgt.n 8007c16 <_dtoa_r+0x926>
|
|
8007b82: e06b b.n 8007c5c <_dtoa_r+0x96c>
|
|
8007b84: 9b14 ldr r3, [sp, #80] @ 0x50
|
|
8007b86: f1c3 0336 rsb r3, r3, #54 @ 0x36
|
|
8007b8a: e73c b.n 8007a06 <_dtoa_r+0x716>
|
|
8007b8c: 3fe00000 .word 0x3fe00000
|
|
8007b90: 40240000 .word 0x40240000
|
|
8007b94: 9b03 ldr r3, [sp, #12]
|
|
8007b96: 1e5c subs r4, r3, #1
|
|
8007b98: 9b08 ldr r3, [sp, #32]
|
|
8007b9a: 42a3 cmp r3, r4
|
|
8007b9c: db09 blt.n 8007bb2 <_dtoa_r+0x8c2>
|
|
8007b9e: 1b1c subs r4, r3, r4
|
|
8007ba0: 9b03 ldr r3, [sp, #12]
|
|
8007ba2: 2b00 cmp r3, #0
|
|
8007ba4: f6bf af30 bge.w 8007a08 <_dtoa_r+0x718>
|
|
8007ba8: 9b00 ldr r3, [sp, #0]
|
|
8007baa: 9a03 ldr r2, [sp, #12]
|
|
8007bac: 1a9e subs r6, r3, r2
|
|
8007bae: 2300 movs r3, #0
|
|
8007bb0: e72b b.n 8007a0a <_dtoa_r+0x71a>
|
|
8007bb2: 9b08 ldr r3, [sp, #32]
|
|
8007bb4: 9a0d ldr r2, [sp, #52] @ 0x34
|
|
8007bb6: 9408 str r4, [sp, #32]
|
|
8007bb8: 1ae3 subs r3, r4, r3
|
|
8007bba: 441a add r2, r3
|
|
8007bbc: 9e00 ldr r6, [sp, #0]
|
|
8007bbe: 9b03 ldr r3, [sp, #12]
|
|
8007bc0: 920d str r2, [sp, #52] @ 0x34
|
|
8007bc2: 2400 movs r4, #0
|
|
8007bc4: e721 b.n 8007a0a <_dtoa_r+0x71a>
|
|
8007bc6: 9c08 ldr r4, [sp, #32]
|
|
8007bc8: 9e00 ldr r6, [sp, #0]
|
|
8007bca: 9d09 ldr r5, [sp, #36] @ 0x24
|
|
8007bcc: e728 b.n 8007a20 <_dtoa_r+0x730>
|
|
8007bce: f8dd 8008 ldr.w r8, [sp, #8]
|
|
8007bd2: e751 b.n 8007a78 <_dtoa_r+0x788>
|
|
8007bd4: 9a08 ldr r2, [sp, #32]
|
|
8007bd6: 9902 ldr r1, [sp, #8]
|
|
8007bd8: e750 b.n 8007a7c <_dtoa_r+0x78c>
|
|
8007bda: f8cd 8008 str.w r8, [sp, #8]
|
|
8007bde: e751 b.n 8007a84 <_dtoa_r+0x794>
|
|
8007be0: 2300 movs r3, #0
|
|
8007be2: e779 b.n 8007ad8 <_dtoa_r+0x7e8>
|
|
8007be4: 9b04 ldr r3, [sp, #16]
|
|
8007be6: e777 b.n 8007ad8 <_dtoa_r+0x7e8>
|
|
8007be8: 2300 movs r3, #0
|
|
8007bea: 9308 str r3, [sp, #32]
|
|
8007bec: e779 b.n 8007ae2 <_dtoa_r+0x7f2>
|
|
8007bee: d093 beq.n 8007b18 <_dtoa_r+0x828>
|
|
8007bf0: 9a00 ldr r2, [sp, #0]
|
|
8007bf2: 331c adds r3, #28
|
|
8007bf4: 441a add r2, r3
|
|
8007bf6: 9200 str r2, [sp, #0]
|
|
8007bf8: 9a06 ldr r2, [sp, #24]
|
|
8007bfa: 441a add r2, r3
|
|
8007bfc: 441e add r6, r3
|
|
8007bfe: 9206 str r2, [sp, #24]
|
|
8007c00: e78a b.n 8007b18 <_dtoa_r+0x828>
|
|
8007c02: 4603 mov r3, r0
|
|
8007c04: e7f4 b.n 8007bf0 <_dtoa_r+0x900>
|
|
8007c06: 9b03 ldr r3, [sp, #12]
|
|
8007c08: 2b00 cmp r3, #0
|
|
8007c0a: 46b8 mov r8, r7
|
|
8007c0c: dc20 bgt.n 8007c50 <_dtoa_r+0x960>
|
|
8007c0e: 469b mov fp, r3
|
|
8007c10: 9b07 ldr r3, [sp, #28]
|
|
8007c12: 2b02 cmp r3, #2
|
|
8007c14: dd1e ble.n 8007c54 <_dtoa_r+0x964>
|
|
8007c16: f1bb 0f00 cmp.w fp, #0
|
|
8007c1a: f47f adb1 bne.w 8007780 <_dtoa_r+0x490>
|
|
8007c1e: 4621 mov r1, r4
|
|
8007c20: 465b mov r3, fp
|
|
8007c22: 2205 movs r2, #5
|
|
8007c24: 4648 mov r0, r9
|
|
8007c26: f000 fa95 bl 8008154 <__multadd>
|
|
8007c2a: 4601 mov r1, r0
|
|
8007c2c: 4604 mov r4, r0
|
|
8007c2e: 9802 ldr r0, [sp, #8]
|
|
8007c30: f000 fca0 bl 8008574 <__mcmp>
|
|
8007c34: 2800 cmp r0, #0
|
|
8007c36: f77f ada3 ble.w 8007780 <_dtoa_r+0x490>
|
|
8007c3a: 4656 mov r6, sl
|
|
8007c3c: 2331 movs r3, #49 @ 0x31
|
|
8007c3e: f806 3b01 strb.w r3, [r6], #1
|
|
8007c42: f108 0801 add.w r8, r8, #1
|
|
8007c46: e59f b.n 8007788 <_dtoa_r+0x498>
|
|
8007c48: 9c03 ldr r4, [sp, #12]
|
|
8007c4a: 46b8 mov r8, r7
|
|
8007c4c: 4625 mov r5, r4
|
|
8007c4e: e7f4 b.n 8007c3a <_dtoa_r+0x94a>
|
|
8007c50: f8dd b00c ldr.w fp, [sp, #12]
|
|
8007c54: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8007c56: 2b00 cmp r3, #0
|
|
8007c58: f000 8101 beq.w 8007e5e <_dtoa_r+0xb6e>
|
|
8007c5c: 2e00 cmp r6, #0
|
|
8007c5e: dd05 ble.n 8007c6c <_dtoa_r+0x97c>
|
|
8007c60: 4629 mov r1, r5
|
|
8007c62: 4632 mov r2, r6
|
|
8007c64: 4648 mov r0, r9
|
|
8007c66: f000 fc19 bl 800849c <__lshift>
|
|
8007c6a: 4605 mov r5, r0
|
|
8007c6c: 9b08 ldr r3, [sp, #32]
|
|
8007c6e: 2b00 cmp r3, #0
|
|
8007c70: d05c beq.n 8007d2c <_dtoa_r+0xa3c>
|
|
8007c72: 6869 ldr r1, [r5, #4]
|
|
8007c74: 4648 mov r0, r9
|
|
8007c76: f000 fa0b bl 8008090 <_Balloc>
|
|
8007c7a: 4606 mov r6, r0
|
|
8007c7c: b928 cbnz r0, 8007c8a <_dtoa_r+0x99a>
|
|
8007c7e: 4b82 ldr r3, [pc, #520] @ (8007e88 <_dtoa_r+0xb98>)
|
|
8007c80: 4602 mov r2, r0
|
|
8007c82: f240 21ef movw r1, #751 @ 0x2ef
|
|
8007c86: f7ff bb4a b.w 800731e <_dtoa_r+0x2e>
|
|
8007c8a: 692a ldr r2, [r5, #16]
|
|
8007c8c: 3202 adds r2, #2
|
|
8007c8e: 0092 lsls r2, r2, #2
|
|
8007c90: f105 010c add.w r1, r5, #12
|
|
8007c94: 300c adds r0, #12
|
|
8007c96: f001 f979 bl 8008f8c <memcpy>
|
|
8007c9a: 2201 movs r2, #1
|
|
8007c9c: 4631 mov r1, r6
|
|
8007c9e: 4648 mov r0, r9
|
|
8007ca0: f000 fbfc bl 800849c <__lshift>
|
|
8007ca4: f10a 0301 add.w r3, sl, #1
|
|
8007ca8: 9300 str r3, [sp, #0]
|
|
8007caa: eb0a 030b add.w r3, sl, fp
|
|
8007cae: 9308 str r3, [sp, #32]
|
|
8007cb0: 9b04 ldr r3, [sp, #16]
|
|
8007cb2: f003 0301 and.w r3, r3, #1
|
|
8007cb6: 462f mov r7, r5
|
|
8007cb8: 9306 str r3, [sp, #24]
|
|
8007cba: 4605 mov r5, r0
|
|
8007cbc: 9b00 ldr r3, [sp, #0]
|
|
8007cbe: 9802 ldr r0, [sp, #8]
|
|
8007cc0: 4621 mov r1, r4
|
|
8007cc2: f103 3bff add.w fp, r3, #4294967295 @ 0xffffffff
|
|
8007cc6: f7ff fa88 bl 80071da <quorem>
|
|
8007cca: 4603 mov r3, r0
|
|
8007ccc: 3330 adds r3, #48 @ 0x30
|
|
8007cce: 9003 str r0, [sp, #12]
|
|
8007cd0: 4639 mov r1, r7
|
|
8007cd2: 9802 ldr r0, [sp, #8]
|
|
8007cd4: 9309 str r3, [sp, #36] @ 0x24
|
|
8007cd6: f000 fc4d bl 8008574 <__mcmp>
|
|
8007cda: 462a mov r2, r5
|
|
8007cdc: 9004 str r0, [sp, #16]
|
|
8007cde: 4621 mov r1, r4
|
|
8007ce0: 4648 mov r0, r9
|
|
8007ce2: f000 fc63 bl 80085ac <__mdiff>
|
|
8007ce6: 68c2 ldr r2, [r0, #12]
|
|
8007ce8: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8007cea: 4606 mov r6, r0
|
|
8007cec: bb02 cbnz r2, 8007d30 <_dtoa_r+0xa40>
|
|
8007cee: 4601 mov r1, r0
|
|
8007cf0: 9802 ldr r0, [sp, #8]
|
|
8007cf2: f000 fc3f bl 8008574 <__mcmp>
|
|
8007cf6: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8007cf8: 4602 mov r2, r0
|
|
8007cfa: 4631 mov r1, r6
|
|
8007cfc: 4648 mov r0, r9
|
|
8007cfe: 920c str r2, [sp, #48] @ 0x30
|
|
8007d00: 9309 str r3, [sp, #36] @ 0x24
|
|
8007d02: f000 fa05 bl 8008110 <_Bfree>
|
|
8007d06: 9b07 ldr r3, [sp, #28]
|
|
8007d08: 9a0c ldr r2, [sp, #48] @ 0x30
|
|
8007d0a: 9e00 ldr r6, [sp, #0]
|
|
8007d0c: ea42 0103 orr.w r1, r2, r3
|
|
8007d10: 9b06 ldr r3, [sp, #24]
|
|
8007d12: 4319 orrs r1, r3
|
|
8007d14: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8007d16: d10d bne.n 8007d34 <_dtoa_r+0xa44>
|
|
8007d18: 2b39 cmp r3, #57 @ 0x39
|
|
8007d1a: d027 beq.n 8007d6c <_dtoa_r+0xa7c>
|
|
8007d1c: 9a04 ldr r2, [sp, #16]
|
|
8007d1e: 2a00 cmp r2, #0
|
|
8007d20: dd01 ble.n 8007d26 <_dtoa_r+0xa36>
|
|
8007d22: 9b03 ldr r3, [sp, #12]
|
|
8007d24: 3331 adds r3, #49 @ 0x31
|
|
8007d26: f88b 3000 strb.w r3, [fp]
|
|
8007d2a: e52e b.n 800778a <_dtoa_r+0x49a>
|
|
8007d2c: 4628 mov r0, r5
|
|
8007d2e: e7b9 b.n 8007ca4 <_dtoa_r+0x9b4>
|
|
8007d30: 2201 movs r2, #1
|
|
8007d32: e7e2 b.n 8007cfa <_dtoa_r+0xa0a>
|
|
8007d34: 9904 ldr r1, [sp, #16]
|
|
8007d36: 2900 cmp r1, #0
|
|
8007d38: db04 blt.n 8007d44 <_dtoa_r+0xa54>
|
|
8007d3a: 9807 ldr r0, [sp, #28]
|
|
8007d3c: 4301 orrs r1, r0
|
|
8007d3e: 9806 ldr r0, [sp, #24]
|
|
8007d40: 4301 orrs r1, r0
|
|
8007d42: d120 bne.n 8007d86 <_dtoa_r+0xa96>
|
|
8007d44: 2a00 cmp r2, #0
|
|
8007d46: ddee ble.n 8007d26 <_dtoa_r+0xa36>
|
|
8007d48: 9902 ldr r1, [sp, #8]
|
|
8007d4a: 9300 str r3, [sp, #0]
|
|
8007d4c: 2201 movs r2, #1
|
|
8007d4e: 4648 mov r0, r9
|
|
8007d50: f000 fba4 bl 800849c <__lshift>
|
|
8007d54: 4621 mov r1, r4
|
|
8007d56: 9002 str r0, [sp, #8]
|
|
8007d58: f000 fc0c bl 8008574 <__mcmp>
|
|
8007d5c: 2800 cmp r0, #0
|
|
8007d5e: 9b00 ldr r3, [sp, #0]
|
|
8007d60: dc02 bgt.n 8007d68 <_dtoa_r+0xa78>
|
|
8007d62: d1e0 bne.n 8007d26 <_dtoa_r+0xa36>
|
|
8007d64: 07da lsls r2, r3, #31
|
|
8007d66: d5de bpl.n 8007d26 <_dtoa_r+0xa36>
|
|
8007d68: 2b39 cmp r3, #57 @ 0x39
|
|
8007d6a: d1da bne.n 8007d22 <_dtoa_r+0xa32>
|
|
8007d6c: 2339 movs r3, #57 @ 0x39
|
|
8007d6e: f88b 3000 strb.w r3, [fp]
|
|
8007d72: 4633 mov r3, r6
|
|
8007d74: 461e mov r6, r3
|
|
8007d76: 3b01 subs r3, #1
|
|
8007d78: f816 2c01 ldrb.w r2, [r6, #-1]
|
|
8007d7c: 2a39 cmp r2, #57 @ 0x39
|
|
8007d7e: d04e beq.n 8007e1e <_dtoa_r+0xb2e>
|
|
8007d80: 3201 adds r2, #1
|
|
8007d82: 701a strb r2, [r3, #0]
|
|
8007d84: e501 b.n 800778a <_dtoa_r+0x49a>
|
|
8007d86: 2a00 cmp r2, #0
|
|
8007d88: dd03 ble.n 8007d92 <_dtoa_r+0xaa2>
|
|
8007d8a: 2b39 cmp r3, #57 @ 0x39
|
|
8007d8c: d0ee beq.n 8007d6c <_dtoa_r+0xa7c>
|
|
8007d8e: 3301 adds r3, #1
|
|
8007d90: e7c9 b.n 8007d26 <_dtoa_r+0xa36>
|
|
8007d92: 9a00 ldr r2, [sp, #0]
|
|
8007d94: 9908 ldr r1, [sp, #32]
|
|
8007d96: f802 3c01 strb.w r3, [r2, #-1]
|
|
8007d9a: 428a cmp r2, r1
|
|
8007d9c: d028 beq.n 8007df0 <_dtoa_r+0xb00>
|
|
8007d9e: 9902 ldr r1, [sp, #8]
|
|
8007da0: 2300 movs r3, #0
|
|
8007da2: 220a movs r2, #10
|
|
8007da4: 4648 mov r0, r9
|
|
8007da6: f000 f9d5 bl 8008154 <__multadd>
|
|
8007daa: 42af cmp r7, r5
|
|
8007dac: 9002 str r0, [sp, #8]
|
|
8007dae: f04f 0300 mov.w r3, #0
|
|
8007db2: f04f 020a mov.w r2, #10
|
|
8007db6: 4639 mov r1, r7
|
|
8007db8: 4648 mov r0, r9
|
|
8007dba: d107 bne.n 8007dcc <_dtoa_r+0xadc>
|
|
8007dbc: f000 f9ca bl 8008154 <__multadd>
|
|
8007dc0: 4607 mov r7, r0
|
|
8007dc2: 4605 mov r5, r0
|
|
8007dc4: 9b00 ldr r3, [sp, #0]
|
|
8007dc6: 3301 adds r3, #1
|
|
8007dc8: 9300 str r3, [sp, #0]
|
|
8007dca: e777 b.n 8007cbc <_dtoa_r+0x9cc>
|
|
8007dcc: f000 f9c2 bl 8008154 <__multadd>
|
|
8007dd0: 4629 mov r1, r5
|
|
8007dd2: 4607 mov r7, r0
|
|
8007dd4: 2300 movs r3, #0
|
|
8007dd6: 220a movs r2, #10
|
|
8007dd8: 4648 mov r0, r9
|
|
8007dda: f000 f9bb bl 8008154 <__multadd>
|
|
8007dde: 4605 mov r5, r0
|
|
8007de0: e7f0 b.n 8007dc4 <_dtoa_r+0xad4>
|
|
8007de2: f1bb 0f00 cmp.w fp, #0
|
|
8007de6: bfcc ite gt
|
|
8007de8: 465e movgt r6, fp
|
|
8007dea: 2601 movle r6, #1
|
|
8007dec: 4456 add r6, sl
|
|
8007dee: 2700 movs r7, #0
|
|
8007df0: 9902 ldr r1, [sp, #8]
|
|
8007df2: 9300 str r3, [sp, #0]
|
|
8007df4: 2201 movs r2, #1
|
|
8007df6: 4648 mov r0, r9
|
|
8007df8: f000 fb50 bl 800849c <__lshift>
|
|
8007dfc: 4621 mov r1, r4
|
|
8007dfe: 9002 str r0, [sp, #8]
|
|
8007e00: f000 fbb8 bl 8008574 <__mcmp>
|
|
8007e04: 2800 cmp r0, #0
|
|
8007e06: dcb4 bgt.n 8007d72 <_dtoa_r+0xa82>
|
|
8007e08: d102 bne.n 8007e10 <_dtoa_r+0xb20>
|
|
8007e0a: 9b00 ldr r3, [sp, #0]
|
|
8007e0c: 07db lsls r3, r3, #31
|
|
8007e0e: d4b0 bmi.n 8007d72 <_dtoa_r+0xa82>
|
|
8007e10: 4633 mov r3, r6
|
|
8007e12: 461e mov r6, r3
|
|
8007e14: f813 2d01 ldrb.w r2, [r3, #-1]!
|
|
8007e18: 2a30 cmp r2, #48 @ 0x30
|
|
8007e1a: d0fa beq.n 8007e12 <_dtoa_r+0xb22>
|
|
8007e1c: e4b5 b.n 800778a <_dtoa_r+0x49a>
|
|
8007e1e: 459a cmp sl, r3
|
|
8007e20: d1a8 bne.n 8007d74 <_dtoa_r+0xa84>
|
|
8007e22: 2331 movs r3, #49 @ 0x31
|
|
8007e24: f108 0801 add.w r8, r8, #1
|
|
8007e28: f88a 3000 strb.w r3, [sl]
|
|
8007e2c: e4ad b.n 800778a <_dtoa_r+0x49a>
|
|
8007e2e: 9b21 ldr r3, [sp, #132] @ 0x84
|
|
8007e30: f8df a058 ldr.w sl, [pc, #88] @ 8007e8c <_dtoa_r+0xb9c>
|
|
8007e34: b11b cbz r3, 8007e3e <_dtoa_r+0xb4e>
|
|
8007e36: f10a 0308 add.w r3, sl, #8
|
|
8007e3a: 9a21 ldr r2, [sp, #132] @ 0x84
|
|
8007e3c: 6013 str r3, [r2, #0]
|
|
8007e3e: 4650 mov r0, sl
|
|
8007e40: b017 add sp, #92 @ 0x5c
|
|
8007e42: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
8007e46: 9b07 ldr r3, [sp, #28]
|
|
8007e48: 2b01 cmp r3, #1
|
|
8007e4a: f77f ae2e ble.w 8007aaa <_dtoa_r+0x7ba>
|
|
8007e4e: 9b0d ldr r3, [sp, #52] @ 0x34
|
|
8007e50: 9308 str r3, [sp, #32]
|
|
8007e52: 2001 movs r0, #1
|
|
8007e54: e64d b.n 8007af2 <_dtoa_r+0x802>
|
|
8007e56: f1bb 0f00 cmp.w fp, #0
|
|
8007e5a: f77f aed9 ble.w 8007c10 <_dtoa_r+0x920>
|
|
8007e5e: 4656 mov r6, sl
|
|
8007e60: 9802 ldr r0, [sp, #8]
|
|
8007e62: 4621 mov r1, r4
|
|
8007e64: f7ff f9b9 bl 80071da <quorem>
|
|
8007e68: f100 0330 add.w r3, r0, #48 @ 0x30
|
|
8007e6c: f806 3b01 strb.w r3, [r6], #1
|
|
8007e70: eba6 020a sub.w r2, r6, sl
|
|
8007e74: 4593 cmp fp, r2
|
|
8007e76: ddb4 ble.n 8007de2 <_dtoa_r+0xaf2>
|
|
8007e78: 9902 ldr r1, [sp, #8]
|
|
8007e7a: 2300 movs r3, #0
|
|
8007e7c: 220a movs r2, #10
|
|
8007e7e: 4648 mov r0, r9
|
|
8007e80: f000 f968 bl 8008154 <__multadd>
|
|
8007e84: 9002 str r0, [sp, #8]
|
|
8007e86: e7eb b.n 8007e60 <_dtoa_r+0xb70>
|
|
8007e88: 080093f0 .word 0x080093f0
|
|
8007e8c: 08009374 .word 0x08009374
|
|
|
|
08007e90 <_free_r>:
|
|
8007e90: b538 push {r3, r4, r5, lr}
|
|
8007e92: 4605 mov r5, r0
|
|
8007e94: 2900 cmp r1, #0
|
|
8007e96: d041 beq.n 8007f1c <_free_r+0x8c>
|
|
8007e98: f851 3c04 ldr.w r3, [r1, #-4]
|
|
8007e9c: 1f0c subs r4, r1, #4
|
|
8007e9e: 2b00 cmp r3, #0
|
|
8007ea0: bfb8 it lt
|
|
8007ea2: 18e4 addlt r4, r4, r3
|
|
8007ea4: f000 f8e8 bl 8008078 <__malloc_lock>
|
|
8007ea8: 4a1d ldr r2, [pc, #116] @ (8007f20 <_free_r+0x90>)
|
|
8007eaa: 6813 ldr r3, [r2, #0]
|
|
8007eac: b933 cbnz r3, 8007ebc <_free_r+0x2c>
|
|
8007eae: 6063 str r3, [r4, #4]
|
|
8007eb0: 6014 str r4, [r2, #0]
|
|
8007eb2: 4628 mov r0, r5
|
|
8007eb4: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
|
|
8007eb8: f000 b8e4 b.w 8008084 <__malloc_unlock>
|
|
8007ebc: 42a3 cmp r3, r4
|
|
8007ebe: d908 bls.n 8007ed2 <_free_r+0x42>
|
|
8007ec0: 6820 ldr r0, [r4, #0]
|
|
8007ec2: 1821 adds r1, r4, r0
|
|
8007ec4: 428b cmp r3, r1
|
|
8007ec6: bf01 itttt eq
|
|
8007ec8: 6819 ldreq r1, [r3, #0]
|
|
8007eca: 685b ldreq r3, [r3, #4]
|
|
8007ecc: 1809 addeq r1, r1, r0
|
|
8007ece: 6021 streq r1, [r4, #0]
|
|
8007ed0: e7ed b.n 8007eae <_free_r+0x1e>
|
|
8007ed2: 461a mov r2, r3
|
|
8007ed4: 685b ldr r3, [r3, #4]
|
|
8007ed6: b10b cbz r3, 8007edc <_free_r+0x4c>
|
|
8007ed8: 42a3 cmp r3, r4
|
|
8007eda: d9fa bls.n 8007ed2 <_free_r+0x42>
|
|
8007edc: 6811 ldr r1, [r2, #0]
|
|
8007ede: 1850 adds r0, r2, r1
|
|
8007ee0: 42a0 cmp r0, r4
|
|
8007ee2: d10b bne.n 8007efc <_free_r+0x6c>
|
|
8007ee4: 6820 ldr r0, [r4, #0]
|
|
8007ee6: 4401 add r1, r0
|
|
8007ee8: 1850 adds r0, r2, r1
|
|
8007eea: 4283 cmp r3, r0
|
|
8007eec: 6011 str r1, [r2, #0]
|
|
8007eee: d1e0 bne.n 8007eb2 <_free_r+0x22>
|
|
8007ef0: 6818 ldr r0, [r3, #0]
|
|
8007ef2: 685b ldr r3, [r3, #4]
|
|
8007ef4: 6053 str r3, [r2, #4]
|
|
8007ef6: 4408 add r0, r1
|
|
8007ef8: 6010 str r0, [r2, #0]
|
|
8007efa: e7da b.n 8007eb2 <_free_r+0x22>
|
|
8007efc: d902 bls.n 8007f04 <_free_r+0x74>
|
|
8007efe: 230c movs r3, #12
|
|
8007f00: 602b str r3, [r5, #0]
|
|
8007f02: e7d6 b.n 8007eb2 <_free_r+0x22>
|
|
8007f04: 6820 ldr r0, [r4, #0]
|
|
8007f06: 1821 adds r1, r4, r0
|
|
8007f08: 428b cmp r3, r1
|
|
8007f0a: bf04 itt eq
|
|
8007f0c: 6819 ldreq r1, [r3, #0]
|
|
8007f0e: 685b ldreq r3, [r3, #4]
|
|
8007f10: 6063 str r3, [r4, #4]
|
|
8007f12: bf04 itt eq
|
|
8007f14: 1809 addeq r1, r1, r0
|
|
8007f16: 6021 streq r1, [r4, #0]
|
|
8007f18: 6054 str r4, [r2, #4]
|
|
8007f1a: e7ca b.n 8007eb2 <_free_r+0x22>
|
|
8007f1c: bd38 pop {r3, r4, r5, pc}
|
|
8007f1e: bf00 nop
|
|
8007f20: 20000474 .word 0x20000474
|
|
|
|
08007f24 <malloc>:
|
|
8007f24: 4b02 ldr r3, [pc, #8] @ (8007f30 <malloc+0xc>)
|
|
8007f26: 4601 mov r1, r0
|
|
8007f28: 6818 ldr r0, [r3, #0]
|
|
8007f2a: f000 b825 b.w 8007f78 <_malloc_r>
|
|
8007f2e: bf00 nop
|
|
8007f30: 2000002c .word 0x2000002c
|
|
|
|
08007f34 <sbrk_aligned>:
|
|
8007f34: b570 push {r4, r5, r6, lr}
|
|
8007f36: 4e0f ldr r6, [pc, #60] @ (8007f74 <sbrk_aligned+0x40>)
|
|
8007f38: 460c mov r4, r1
|
|
8007f3a: 6831 ldr r1, [r6, #0]
|
|
8007f3c: 4605 mov r5, r0
|
|
8007f3e: b911 cbnz r1, 8007f46 <sbrk_aligned+0x12>
|
|
8007f40: f001 f814 bl 8008f6c <_sbrk_r>
|
|
8007f44: 6030 str r0, [r6, #0]
|
|
8007f46: 4621 mov r1, r4
|
|
8007f48: 4628 mov r0, r5
|
|
8007f4a: f001 f80f bl 8008f6c <_sbrk_r>
|
|
8007f4e: 1c43 adds r3, r0, #1
|
|
8007f50: d103 bne.n 8007f5a <sbrk_aligned+0x26>
|
|
8007f52: f04f 34ff mov.w r4, #4294967295 @ 0xffffffff
|
|
8007f56: 4620 mov r0, r4
|
|
8007f58: bd70 pop {r4, r5, r6, pc}
|
|
8007f5a: 1cc4 adds r4, r0, #3
|
|
8007f5c: f024 0403 bic.w r4, r4, #3
|
|
8007f60: 42a0 cmp r0, r4
|
|
8007f62: d0f8 beq.n 8007f56 <sbrk_aligned+0x22>
|
|
8007f64: 1a21 subs r1, r4, r0
|
|
8007f66: 4628 mov r0, r5
|
|
8007f68: f001 f800 bl 8008f6c <_sbrk_r>
|
|
8007f6c: 3001 adds r0, #1
|
|
8007f6e: d1f2 bne.n 8007f56 <sbrk_aligned+0x22>
|
|
8007f70: e7ef b.n 8007f52 <sbrk_aligned+0x1e>
|
|
8007f72: bf00 nop
|
|
8007f74: 20000470 .word 0x20000470
|
|
|
|
08007f78 <_malloc_r>:
|
|
8007f78: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
|
|
8007f7c: 1ccd adds r5, r1, #3
|
|
8007f7e: f025 0503 bic.w r5, r5, #3
|
|
8007f82: 3508 adds r5, #8
|
|
8007f84: 2d0c cmp r5, #12
|
|
8007f86: bf38 it cc
|
|
8007f88: 250c movcc r5, #12
|
|
8007f8a: 2d00 cmp r5, #0
|
|
8007f8c: 4606 mov r6, r0
|
|
8007f8e: db01 blt.n 8007f94 <_malloc_r+0x1c>
|
|
8007f90: 42a9 cmp r1, r5
|
|
8007f92: d904 bls.n 8007f9e <_malloc_r+0x26>
|
|
8007f94: 230c movs r3, #12
|
|
8007f96: 6033 str r3, [r6, #0]
|
|
8007f98: 2000 movs r0, #0
|
|
8007f9a: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
|
|
8007f9e: f8df 80d4 ldr.w r8, [pc, #212] @ 8008074 <_malloc_r+0xfc>
|
|
8007fa2: f000 f869 bl 8008078 <__malloc_lock>
|
|
8007fa6: f8d8 3000 ldr.w r3, [r8]
|
|
8007faa: 461c mov r4, r3
|
|
8007fac: bb44 cbnz r4, 8008000 <_malloc_r+0x88>
|
|
8007fae: 4629 mov r1, r5
|
|
8007fb0: 4630 mov r0, r6
|
|
8007fb2: f7ff ffbf bl 8007f34 <sbrk_aligned>
|
|
8007fb6: 1c43 adds r3, r0, #1
|
|
8007fb8: 4604 mov r4, r0
|
|
8007fba: d158 bne.n 800806e <_malloc_r+0xf6>
|
|
8007fbc: f8d8 4000 ldr.w r4, [r8]
|
|
8007fc0: 4627 mov r7, r4
|
|
8007fc2: 2f00 cmp r7, #0
|
|
8007fc4: d143 bne.n 800804e <_malloc_r+0xd6>
|
|
8007fc6: 2c00 cmp r4, #0
|
|
8007fc8: d04b beq.n 8008062 <_malloc_r+0xea>
|
|
8007fca: 6823 ldr r3, [r4, #0]
|
|
8007fcc: 4639 mov r1, r7
|
|
8007fce: 4630 mov r0, r6
|
|
8007fd0: eb04 0903 add.w r9, r4, r3
|
|
8007fd4: f000 ffca bl 8008f6c <_sbrk_r>
|
|
8007fd8: 4581 cmp r9, r0
|
|
8007fda: d142 bne.n 8008062 <_malloc_r+0xea>
|
|
8007fdc: 6821 ldr r1, [r4, #0]
|
|
8007fde: 1a6d subs r5, r5, r1
|
|
8007fe0: 4629 mov r1, r5
|
|
8007fe2: 4630 mov r0, r6
|
|
8007fe4: f7ff ffa6 bl 8007f34 <sbrk_aligned>
|
|
8007fe8: 3001 adds r0, #1
|
|
8007fea: d03a beq.n 8008062 <_malloc_r+0xea>
|
|
8007fec: 6823 ldr r3, [r4, #0]
|
|
8007fee: 442b add r3, r5
|
|
8007ff0: 6023 str r3, [r4, #0]
|
|
8007ff2: f8d8 3000 ldr.w r3, [r8]
|
|
8007ff6: 685a ldr r2, [r3, #4]
|
|
8007ff8: bb62 cbnz r2, 8008054 <_malloc_r+0xdc>
|
|
8007ffa: f8c8 7000 str.w r7, [r8]
|
|
8007ffe: e00f b.n 8008020 <_malloc_r+0xa8>
|
|
8008000: 6822 ldr r2, [r4, #0]
|
|
8008002: 1b52 subs r2, r2, r5
|
|
8008004: d420 bmi.n 8008048 <_malloc_r+0xd0>
|
|
8008006: 2a0b cmp r2, #11
|
|
8008008: d917 bls.n 800803a <_malloc_r+0xc2>
|
|
800800a: 1961 adds r1, r4, r5
|
|
800800c: 42a3 cmp r3, r4
|
|
800800e: 6025 str r5, [r4, #0]
|
|
8008010: bf18 it ne
|
|
8008012: 6059 strne r1, [r3, #4]
|
|
8008014: 6863 ldr r3, [r4, #4]
|
|
8008016: bf08 it eq
|
|
8008018: f8c8 1000 streq.w r1, [r8]
|
|
800801c: 5162 str r2, [r4, r5]
|
|
800801e: 604b str r3, [r1, #4]
|
|
8008020: 4630 mov r0, r6
|
|
8008022: f000 f82f bl 8008084 <__malloc_unlock>
|
|
8008026: f104 000b add.w r0, r4, #11
|
|
800802a: 1d23 adds r3, r4, #4
|
|
800802c: f020 0007 bic.w r0, r0, #7
|
|
8008030: 1ac2 subs r2, r0, r3
|
|
8008032: bf1c itt ne
|
|
8008034: 1a1b subne r3, r3, r0
|
|
8008036: 50a3 strne r3, [r4, r2]
|
|
8008038: e7af b.n 8007f9a <_malloc_r+0x22>
|
|
800803a: 6862 ldr r2, [r4, #4]
|
|
800803c: 42a3 cmp r3, r4
|
|
800803e: bf0c ite eq
|
|
8008040: f8c8 2000 streq.w r2, [r8]
|
|
8008044: 605a strne r2, [r3, #4]
|
|
8008046: e7eb b.n 8008020 <_malloc_r+0xa8>
|
|
8008048: 4623 mov r3, r4
|
|
800804a: 6864 ldr r4, [r4, #4]
|
|
800804c: e7ae b.n 8007fac <_malloc_r+0x34>
|
|
800804e: 463c mov r4, r7
|
|
8008050: 687f ldr r7, [r7, #4]
|
|
8008052: e7b6 b.n 8007fc2 <_malloc_r+0x4a>
|
|
8008054: 461a mov r2, r3
|
|
8008056: 685b ldr r3, [r3, #4]
|
|
8008058: 42a3 cmp r3, r4
|
|
800805a: d1fb bne.n 8008054 <_malloc_r+0xdc>
|
|
800805c: 2300 movs r3, #0
|
|
800805e: 6053 str r3, [r2, #4]
|
|
8008060: e7de b.n 8008020 <_malloc_r+0xa8>
|
|
8008062: 230c movs r3, #12
|
|
8008064: 6033 str r3, [r6, #0]
|
|
8008066: 4630 mov r0, r6
|
|
8008068: f000 f80c bl 8008084 <__malloc_unlock>
|
|
800806c: e794 b.n 8007f98 <_malloc_r+0x20>
|
|
800806e: 6005 str r5, [r0, #0]
|
|
8008070: e7d6 b.n 8008020 <_malloc_r+0xa8>
|
|
8008072: bf00 nop
|
|
8008074: 20000474 .word 0x20000474
|
|
|
|
08008078 <__malloc_lock>:
|
|
8008078: 4801 ldr r0, [pc, #4] @ (8008080 <__malloc_lock+0x8>)
|
|
800807a: f7ff b8ac b.w 80071d6 <__retarget_lock_acquire_recursive>
|
|
800807e: bf00 nop
|
|
8008080: 2000046c .word 0x2000046c
|
|
|
|
08008084 <__malloc_unlock>:
|
|
8008084: 4801 ldr r0, [pc, #4] @ (800808c <__malloc_unlock+0x8>)
|
|
8008086: f7ff b8a7 b.w 80071d8 <__retarget_lock_release_recursive>
|
|
800808a: bf00 nop
|
|
800808c: 2000046c .word 0x2000046c
|
|
|
|
08008090 <_Balloc>:
|
|
8008090: b570 push {r4, r5, r6, lr}
|
|
8008092: 69c6 ldr r6, [r0, #28]
|
|
8008094: 4604 mov r4, r0
|
|
8008096: 460d mov r5, r1
|
|
8008098: b976 cbnz r6, 80080b8 <_Balloc+0x28>
|
|
800809a: 2010 movs r0, #16
|
|
800809c: f7ff ff42 bl 8007f24 <malloc>
|
|
80080a0: 4602 mov r2, r0
|
|
80080a2: 61e0 str r0, [r4, #28]
|
|
80080a4: b920 cbnz r0, 80080b0 <_Balloc+0x20>
|
|
80080a6: 4b18 ldr r3, [pc, #96] @ (8008108 <_Balloc+0x78>)
|
|
80080a8: 4818 ldr r0, [pc, #96] @ (800810c <_Balloc+0x7c>)
|
|
80080aa: 216b movs r1, #107 @ 0x6b
|
|
80080ac: f000 ff7c bl 8008fa8 <__assert_func>
|
|
80080b0: e9c0 6601 strd r6, r6, [r0, #4]
|
|
80080b4: 6006 str r6, [r0, #0]
|
|
80080b6: 60c6 str r6, [r0, #12]
|
|
80080b8: 69e6 ldr r6, [r4, #28]
|
|
80080ba: 68f3 ldr r3, [r6, #12]
|
|
80080bc: b183 cbz r3, 80080e0 <_Balloc+0x50>
|
|
80080be: 69e3 ldr r3, [r4, #28]
|
|
80080c0: 68db ldr r3, [r3, #12]
|
|
80080c2: f853 0025 ldr.w r0, [r3, r5, lsl #2]
|
|
80080c6: b9b8 cbnz r0, 80080f8 <_Balloc+0x68>
|
|
80080c8: 2101 movs r1, #1
|
|
80080ca: fa01 f605 lsl.w r6, r1, r5
|
|
80080ce: 1d72 adds r2, r6, #5
|
|
80080d0: 0092 lsls r2, r2, #2
|
|
80080d2: 4620 mov r0, r4
|
|
80080d4: f000 ff86 bl 8008fe4 <_calloc_r>
|
|
80080d8: b160 cbz r0, 80080f4 <_Balloc+0x64>
|
|
80080da: e9c0 5601 strd r5, r6, [r0, #4]
|
|
80080de: e00e b.n 80080fe <_Balloc+0x6e>
|
|
80080e0: 2221 movs r2, #33 @ 0x21
|
|
80080e2: 2104 movs r1, #4
|
|
80080e4: 4620 mov r0, r4
|
|
80080e6: f000 ff7d bl 8008fe4 <_calloc_r>
|
|
80080ea: 69e3 ldr r3, [r4, #28]
|
|
80080ec: 60f0 str r0, [r6, #12]
|
|
80080ee: 68db ldr r3, [r3, #12]
|
|
80080f0: 2b00 cmp r3, #0
|
|
80080f2: d1e4 bne.n 80080be <_Balloc+0x2e>
|
|
80080f4: 2000 movs r0, #0
|
|
80080f6: bd70 pop {r4, r5, r6, pc}
|
|
80080f8: 6802 ldr r2, [r0, #0]
|
|
80080fa: f843 2025 str.w r2, [r3, r5, lsl #2]
|
|
80080fe: 2300 movs r3, #0
|
|
8008100: e9c0 3303 strd r3, r3, [r0, #12]
|
|
8008104: e7f7 b.n 80080f6 <_Balloc+0x66>
|
|
8008106: bf00 nop
|
|
8008108: 08009381 .word 0x08009381
|
|
800810c: 08009401 .word 0x08009401
|
|
|
|
08008110 <_Bfree>:
|
|
8008110: b570 push {r4, r5, r6, lr}
|
|
8008112: 69c6 ldr r6, [r0, #28]
|
|
8008114: 4605 mov r5, r0
|
|
8008116: 460c mov r4, r1
|
|
8008118: b976 cbnz r6, 8008138 <_Bfree+0x28>
|
|
800811a: 2010 movs r0, #16
|
|
800811c: f7ff ff02 bl 8007f24 <malloc>
|
|
8008120: 4602 mov r2, r0
|
|
8008122: 61e8 str r0, [r5, #28]
|
|
8008124: b920 cbnz r0, 8008130 <_Bfree+0x20>
|
|
8008126: 4b09 ldr r3, [pc, #36] @ (800814c <_Bfree+0x3c>)
|
|
8008128: 4809 ldr r0, [pc, #36] @ (8008150 <_Bfree+0x40>)
|
|
800812a: 218f movs r1, #143 @ 0x8f
|
|
800812c: f000 ff3c bl 8008fa8 <__assert_func>
|
|
8008130: e9c0 6601 strd r6, r6, [r0, #4]
|
|
8008134: 6006 str r6, [r0, #0]
|
|
8008136: 60c6 str r6, [r0, #12]
|
|
8008138: b13c cbz r4, 800814a <_Bfree+0x3a>
|
|
800813a: 69eb ldr r3, [r5, #28]
|
|
800813c: 6862 ldr r2, [r4, #4]
|
|
800813e: 68db ldr r3, [r3, #12]
|
|
8008140: f853 1022 ldr.w r1, [r3, r2, lsl #2]
|
|
8008144: 6021 str r1, [r4, #0]
|
|
8008146: f843 4022 str.w r4, [r3, r2, lsl #2]
|
|
800814a: bd70 pop {r4, r5, r6, pc}
|
|
800814c: 08009381 .word 0x08009381
|
|
8008150: 08009401 .word 0x08009401
|
|
|
|
08008154 <__multadd>:
|
|
8008154: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
8008158: 690d ldr r5, [r1, #16]
|
|
800815a: 4607 mov r7, r0
|
|
800815c: 460c mov r4, r1
|
|
800815e: 461e mov r6, r3
|
|
8008160: f101 0c14 add.w ip, r1, #20
|
|
8008164: 2000 movs r0, #0
|
|
8008166: f8dc 3000 ldr.w r3, [ip]
|
|
800816a: b299 uxth r1, r3
|
|
800816c: fb02 6101 mla r1, r2, r1, r6
|
|
8008170: 0c1e lsrs r6, r3, #16
|
|
8008172: 0c0b lsrs r3, r1, #16
|
|
8008174: fb02 3306 mla r3, r2, r6, r3
|
|
8008178: b289 uxth r1, r1
|
|
800817a: 3001 adds r0, #1
|
|
800817c: eb01 4103 add.w r1, r1, r3, lsl #16
|
|
8008180: 4285 cmp r5, r0
|
|
8008182: f84c 1b04 str.w r1, [ip], #4
|
|
8008186: ea4f 4613 mov.w r6, r3, lsr #16
|
|
800818a: dcec bgt.n 8008166 <__multadd+0x12>
|
|
800818c: b30e cbz r6, 80081d2 <__multadd+0x7e>
|
|
800818e: 68a3 ldr r3, [r4, #8]
|
|
8008190: 42ab cmp r3, r5
|
|
8008192: dc19 bgt.n 80081c8 <__multadd+0x74>
|
|
8008194: 6861 ldr r1, [r4, #4]
|
|
8008196: 4638 mov r0, r7
|
|
8008198: 3101 adds r1, #1
|
|
800819a: f7ff ff79 bl 8008090 <_Balloc>
|
|
800819e: 4680 mov r8, r0
|
|
80081a0: b928 cbnz r0, 80081ae <__multadd+0x5a>
|
|
80081a2: 4602 mov r2, r0
|
|
80081a4: 4b0c ldr r3, [pc, #48] @ (80081d8 <__multadd+0x84>)
|
|
80081a6: 480d ldr r0, [pc, #52] @ (80081dc <__multadd+0x88>)
|
|
80081a8: 21ba movs r1, #186 @ 0xba
|
|
80081aa: f000 fefd bl 8008fa8 <__assert_func>
|
|
80081ae: 6922 ldr r2, [r4, #16]
|
|
80081b0: 3202 adds r2, #2
|
|
80081b2: f104 010c add.w r1, r4, #12
|
|
80081b6: 0092 lsls r2, r2, #2
|
|
80081b8: 300c adds r0, #12
|
|
80081ba: f000 fee7 bl 8008f8c <memcpy>
|
|
80081be: 4621 mov r1, r4
|
|
80081c0: 4638 mov r0, r7
|
|
80081c2: f7ff ffa5 bl 8008110 <_Bfree>
|
|
80081c6: 4644 mov r4, r8
|
|
80081c8: eb04 0385 add.w r3, r4, r5, lsl #2
|
|
80081cc: 3501 adds r5, #1
|
|
80081ce: 615e str r6, [r3, #20]
|
|
80081d0: 6125 str r5, [r4, #16]
|
|
80081d2: 4620 mov r0, r4
|
|
80081d4: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
|
80081d8: 080093f0 .word 0x080093f0
|
|
80081dc: 08009401 .word 0x08009401
|
|
|
|
080081e0 <__hi0bits>:
|
|
80081e0: f5b0 3f80 cmp.w r0, #65536 @ 0x10000
|
|
80081e4: 4603 mov r3, r0
|
|
80081e6: bf36 itet cc
|
|
80081e8: 0403 lslcc r3, r0, #16
|
|
80081ea: 2000 movcs r0, #0
|
|
80081ec: 2010 movcc r0, #16
|
|
80081ee: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
|
|
80081f2: bf3c itt cc
|
|
80081f4: 021b lslcc r3, r3, #8
|
|
80081f6: 3008 addcc r0, #8
|
|
80081f8: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
|
|
80081fc: bf3c itt cc
|
|
80081fe: 011b lslcc r3, r3, #4
|
|
8008200: 3004 addcc r0, #4
|
|
8008202: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
|
|
8008206: bf3c itt cc
|
|
8008208: 009b lslcc r3, r3, #2
|
|
800820a: 3002 addcc r0, #2
|
|
800820c: 2b00 cmp r3, #0
|
|
800820e: db05 blt.n 800821c <__hi0bits+0x3c>
|
|
8008210: f013 4f80 tst.w r3, #1073741824 @ 0x40000000
|
|
8008214: f100 0001 add.w r0, r0, #1
|
|
8008218: bf08 it eq
|
|
800821a: 2020 moveq r0, #32
|
|
800821c: 4770 bx lr
|
|
|
|
0800821e <__lo0bits>:
|
|
800821e: 6803 ldr r3, [r0, #0]
|
|
8008220: 4602 mov r2, r0
|
|
8008222: f013 0007 ands.w r0, r3, #7
|
|
8008226: d00b beq.n 8008240 <__lo0bits+0x22>
|
|
8008228: 07d9 lsls r1, r3, #31
|
|
800822a: d421 bmi.n 8008270 <__lo0bits+0x52>
|
|
800822c: 0798 lsls r0, r3, #30
|
|
800822e: bf49 itett mi
|
|
8008230: 085b lsrmi r3, r3, #1
|
|
8008232: 089b lsrpl r3, r3, #2
|
|
8008234: 2001 movmi r0, #1
|
|
8008236: 6013 strmi r3, [r2, #0]
|
|
8008238: bf5c itt pl
|
|
800823a: 6013 strpl r3, [r2, #0]
|
|
800823c: 2002 movpl r0, #2
|
|
800823e: 4770 bx lr
|
|
8008240: b299 uxth r1, r3
|
|
8008242: b909 cbnz r1, 8008248 <__lo0bits+0x2a>
|
|
8008244: 0c1b lsrs r3, r3, #16
|
|
8008246: 2010 movs r0, #16
|
|
8008248: b2d9 uxtb r1, r3
|
|
800824a: b909 cbnz r1, 8008250 <__lo0bits+0x32>
|
|
800824c: 3008 adds r0, #8
|
|
800824e: 0a1b lsrs r3, r3, #8
|
|
8008250: 0719 lsls r1, r3, #28
|
|
8008252: bf04 itt eq
|
|
8008254: 091b lsreq r3, r3, #4
|
|
8008256: 3004 addeq r0, #4
|
|
8008258: 0799 lsls r1, r3, #30
|
|
800825a: bf04 itt eq
|
|
800825c: 089b lsreq r3, r3, #2
|
|
800825e: 3002 addeq r0, #2
|
|
8008260: 07d9 lsls r1, r3, #31
|
|
8008262: d403 bmi.n 800826c <__lo0bits+0x4e>
|
|
8008264: 085b lsrs r3, r3, #1
|
|
8008266: f100 0001 add.w r0, r0, #1
|
|
800826a: d003 beq.n 8008274 <__lo0bits+0x56>
|
|
800826c: 6013 str r3, [r2, #0]
|
|
800826e: 4770 bx lr
|
|
8008270: 2000 movs r0, #0
|
|
8008272: 4770 bx lr
|
|
8008274: 2020 movs r0, #32
|
|
8008276: 4770 bx lr
|
|
|
|
08008278 <__i2b>:
|
|
8008278: b510 push {r4, lr}
|
|
800827a: 460c mov r4, r1
|
|
800827c: 2101 movs r1, #1
|
|
800827e: f7ff ff07 bl 8008090 <_Balloc>
|
|
8008282: 4602 mov r2, r0
|
|
8008284: b928 cbnz r0, 8008292 <__i2b+0x1a>
|
|
8008286: 4b05 ldr r3, [pc, #20] @ (800829c <__i2b+0x24>)
|
|
8008288: 4805 ldr r0, [pc, #20] @ (80082a0 <__i2b+0x28>)
|
|
800828a: f240 1145 movw r1, #325 @ 0x145
|
|
800828e: f000 fe8b bl 8008fa8 <__assert_func>
|
|
8008292: 2301 movs r3, #1
|
|
8008294: 6144 str r4, [r0, #20]
|
|
8008296: 6103 str r3, [r0, #16]
|
|
8008298: bd10 pop {r4, pc}
|
|
800829a: bf00 nop
|
|
800829c: 080093f0 .word 0x080093f0
|
|
80082a0: 08009401 .word 0x08009401
|
|
|
|
080082a4 <__multiply>:
|
|
80082a4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
80082a8: 4617 mov r7, r2
|
|
80082aa: 690a ldr r2, [r1, #16]
|
|
80082ac: 693b ldr r3, [r7, #16]
|
|
80082ae: 429a cmp r2, r3
|
|
80082b0: bfa8 it ge
|
|
80082b2: 463b movge r3, r7
|
|
80082b4: 4689 mov r9, r1
|
|
80082b6: bfa4 itt ge
|
|
80082b8: 460f movge r7, r1
|
|
80082ba: 4699 movge r9, r3
|
|
80082bc: 693d ldr r5, [r7, #16]
|
|
80082be: f8d9 a010 ldr.w sl, [r9, #16]
|
|
80082c2: 68bb ldr r3, [r7, #8]
|
|
80082c4: 6879 ldr r1, [r7, #4]
|
|
80082c6: eb05 060a add.w r6, r5, sl
|
|
80082ca: 42b3 cmp r3, r6
|
|
80082cc: b085 sub sp, #20
|
|
80082ce: bfb8 it lt
|
|
80082d0: 3101 addlt r1, #1
|
|
80082d2: f7ff fedd bl 8008090 <_Balloc>
|
|
80082d6: b930 cbnz r0, 80082e6 <__multiply+0x42>
|
|
80082d8: 4602 mov r2, r0
|
|
80082da: 4b41 ldr r3, [pc, #260] @ (80083e0 <__multiply+0x13c>)
|
|
80082dc: 4841 ldr r0, [pc, #260] @ (80083e4 <__multiply+0x140>)
|
|
80082de: f44f 71b1 mov.w r1, #354 @ 0x162
|
|
80082e2: f000 fe61 bl 8008fa8 <__assert_func>
|
|
80082e6: f100 0414 add.w r4, r0, #20
|
|
80082ea: eb04 0e86 add.w lr, r4, r6, lsl #2
|
|
80082ee: 4623 mov r3, r4
|
|
80082f0: 2200 movs r2, #0
|
|
80082f2: 4573 cmp r3, lr
|
|
80082f4: d320 bcc.n 8008338 <__multiply+0x94>
|
|
80082f6: f107 0814 add.w r8, r7, #20
|
|
80082fa: f109 0114 add.w r1, r9, #20
|
|
80082fe: eb08 0585 add.w r5, r8, r5, lsl #2
|
|
8008302: eb01 038a add.w r3, r1, sl, lsl #2
|
|
8008306: 9302 str r3, [sp, #8]
|
|
8008308: 1beb subs r3, r5, r7
|
|
800830a: 3b15 subs r3, #21
|
|
800830c: f023 0303 bic.w r3, r3, #3
|
|
8008310: 3304 adds r3, #4
|
|
8008312: 3715 adds r7, #21
|
|
8008314: 42bd cmp r5, r7
|
|
8008316: bf38 it cc
|
|
8008318: 2304 movcc r3, #4
|
|
800831a: 9301 str r3, [sp, #4]
|
|
800831c: 9b02 ldr r3, [sp, #8]
|
|
800831e: 9103 str r1, [sp, #12]
|
|
8008320: 428b cmp r3, r1
|
|
8008322: d80c bhi.n 800833e <__multiply+0x9a>
|
|
8008324: 2e00 cmp r6, #0
|
|
8008326: dd03 ble.n 8008330 <__multiply+0x8c>
|
|
8008328: f85e 3d04 ldr.w r3, [lr, #-4]!
|
|
800832c: 2b00 cmp r3, #0
|
|
800832e: d055 beq.n 80083dc <__multiply+0x138>
|
|
8008330: 6106 str r6, [r0, #16]
|
|
8008332: b005 add sp, #20
|
|
8008334: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
8008338: f843 2b04 str.w r2, [r3], #4
|
|
800833c: e7d9 b.n 80082f2 <__multiply+0x4e>
|
|
800833e: f8b1 a000 ldrh.w sl, [r1]
|
|
8008342: f1ba 0f00 cmp.w sl, #0
|
|
8008346: d01f beq.n 8008388 <__multiply+0xe4>
|
|
8008348: 46c4 mov ip, r8
|
|
800834a: 46a1 mov r9, r4
|
|
800834c: 2700 movs r7, #0
|
|
800834e: f85c 2b04 ldr.w r2, [ip], #4
|
|
8008352: f8d9 3000 ldr.w r3, [r9]
|
|
8008356: fa1f fb82 uxth.w fp, r2
|
|
800835a: b29b uxth r3, r3
|
|
800835c: fb0a 330b mla r3, sl, fp, r3
|
|
8008360: 443b add r3, r7
|
|
8008362: f8d9 7000 ldr.w r7, [r9]
|
|
8008366: 0c12 lsrs r2, r2, #16
|
|
8008368: 0c3f lsrs r7, r7, #16
|
|
800836a: fb0a 7202 mla r2, sl, r2, r7
|
|
800836e: eb02 4213 add.w r2, r2, r3, lsr #16
|
|
8008372: b29b uxth r3, r3
|
|
8008374: ea43 4302 orr.w r3, r3, r2, lsl #16
|
|
8008378: 4565 cmp r5, ip
|
|
800837a: f849 3b04 str.w r3, [r9], #4
|
|
800837e: ea4f 4712 mov.w r7, r2, lsr #16
|
|
8008382: d8e4 bhi.n 800834e <__multiply+0xaa>
|
|
8008384: 9b01 ldr r3, [sp, #4]
|
|
8008386: 50e7 str r7, [r4, r3]
|
|
8008388: 9b03 ldr r3, [sp, #12]
|
|
800838a: f8b3 9002 ldrh.w r9, [r3, #2]
|
|
800838e: 3104 adds r1, #4
|
|
8008390: f1b9 0f00 cmp.w r9, #0
|
|
8008394: d020 beq.n 80083d8 <__multiply+0x134>
|
|
8008396: 6823 ldr r3, [r4, #0]
|
|
8008398: 4647 mov r7, r8
|
|
800839a: 46a4 mov ip, r4
|
|
800839c: f04f 0a00 mov.w sl, #0
|
|
80083a0: f8b7 b000 ldrh.w fp, [r7]
|
|
80083a4: f8bc 2002 ldrh.w r2, [ip, #2]
|
|
80083a8: fb09 220b mla r2, r9, fp, r2
|
|
80083ac: 4452 add r2, sl
|
|
80083ae: b29b uxth r3, r3
|
|
80083b0: ea43 4302 orr.w r3, r3, r2, lsl #16
|
|
80083b4: f84c 3b04 str.w r3, [ip], #4
|
|
80083b8: f857 3b04 ldr.w r3, [r7], #4
|
|
80083bc: ea4f 4a13 mov.w sl, r3, lsr #16
|
|
80083c0: f8bc 3000 ldrh.w r3, [ip]
|
|
80083c4: fb09 330a mla r3, r9, sl, r3
|
|
80083c8: eb03 4312 add.w r3, r3, r2, lsr #16
|
|
80083cc: 42bd cmp r5, r7
|
|
80083ce: ea4f 4a13 mov.w sl, r3, lsr #16
|
|
80083d2: d8e5 bhi.n 80083a0 <__multiply+0xfc>
|
|
80083d4: 9a01 ldr r2, [sp, #4]
|
|
80083d6: 50a3 str r3, [r4, r2]
|
|
80083d8: 3404 adds r4, #4
|
|
80083da: e79f b.n 800831c <__multiply+0x78>
|
|
80083dc: 3e01 subs r6, #1
|
|
80083de: e7a1 b.n 8008324 <__multiply+0x80>
|
|
80083e0: 080093f0 .word 0x080093f0
|
|
80083e4: 08009401 .word 0x08009401
|
|
|
|
080083e8 <__pow5mult>:
|
|
80083e8: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr}
|
|
80083ec: 4615 mov r5, r2
|
|
80083ee: f012 0203 ands.w r2, r2, #3
|
|
80083f2: 4607 mov r7, r0
|
|
80083f4: 460e mov r6, r1
|
|
80083f6: d007 beq.n 8008408 <__pow5mult+0x20>
|
|
80083f8: 4c25 ldr r4, [pc, #148] @ (8008490 <__pow5mult+0xa8>)
|
|
80083fa: 3a01 subs r2, #1
|
|
80083fc: 2300 movs r3, #0
|
|
80083fe: f854 2022 ldr.w r2, [r4, r2, lsl #2]
|
|
8008402: f7ff fea7 bl 8008154 <__multadd>
|
|
8008406: 4606 mov r6, r0
|
|
8008408: 10ad asrs r5, r5, #2
|
|
800840a: d03d beq.n 8008488 <__pow5mult+0xa0>
|
|
800840c: 69fc ldr r4, [r7, #28]
|
|
800840e: b97c cbnz r4, 8008430 <__pow5mult+0x48>
|
|
8008410: 2010 movs r0, #16
|
|
8008412: f7ff fd87 bl 8007f24 <malloc>
|
|
8008416: 4602 mov r2, r0
|
|
8008418: 61f8 str r0, [r7, #28]
|
|
800841a: b928 cbnz r0, 8008428 <__pow5mult+0x40>
|
|
800841c: 4b1d ldr r3, [pc, #116] @ (8008494 <__pow5mult+0xac>)
|
|
800841e: 481e ldr r0, [pc, #120] @ (8008498 <__pow5mult+0xb0>)
|
|
8008420: f240 11b3 movw r1, #435 @ 0x1b3
|
|
8008424: f000 fdc0 bl 8008fa8 <__assert_func>
|
|
8008428: e9c0 4401 strd r4, r4, [r0, #4]
|
|
800842c: 6004 str r4, [r0, #0]
|
|
800842e: 60c4 str r4, [r0, #12]
|
|
8008430: f8d7 801c ldr.w r8, [r7, #28]
|
|
8008434: f8d8 4008 ldr.w r4, [r8, #8]
|
|
8008438: b94c cbnz r4, 800844e <__pow5mult+0x66>
|
|
800843a: f240 2171 movw r1, #625 @ 0x271
|
|
800843e: 4638 mov r0, r7
|
|
8008440: f7ff ff1a bl 8008278 <__i2b>
|
|
8008444: 2300 movs r3, #0
|
|
8008446: f8c8 0008 str.w r0, [r8, #8]
|
|
800844a: 4604 mov r4, r0
|
|
800844c: 6003 str r3, [r0, #0]
|
|
800844e: f04f 0900 mov.w r9, #0
|
|
8008452: 07eb lsls r3, r5, #31
|
|
8008454: d50a bpl.n 800846c <__pow5mult+0x84>
|
|
8008456: 4631 mov r1, r6
|
|
8008458: 4622 mov r2, r4
|
|
800845a: 4638 mov r0, r7
|
|
800845c: f7ff ff22 bl 80082a4 <__multiply>
|
|
8008460: 4631 mov r1, r6
|
|
8008462: 4680 mov r8, r0
|
|
8008464: 4638 mov r0, r7
|
|
8008466: f7ff fe53 bl 8008110 <_Bfree>
|
|
800846a: 4646 mov r6, r8
|
|
800846c: 106d asrs r5, r5, #1
|
|
800846e: d00b beq.n 8008488 <__pow5mult+0xa0>
|
|
8008470: 6820 ldr r0, [r4, #0]
|
|
8008472: b938 cbnz r0, 8008484 <__pow5mult+0x9c>
|
|
8008474: 4622 mov r2, r4
|
|
8008476: 4621 mov r1, r4
|
|
8008478: 4638 mov r0, r7
|
|
800847a: f7ff ff13 bl 80082a4 <__multiply>
|
|
800847e: 6020 str r0, [r4, #0]
|
|
8008480: f8c0 9000 str.w r9, [r0]
|
|
8008484: 4604 mov r4, r0
|
|
8008486: e7e4 b.n 8008452 <__pow5mult+0x6a>
|
|
8008488: 4630 mov r0, r6
|
|
800848a: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc}
|
|
800848e: bf00 nop
|
|
8008490: 080094b4 .word 0x080094b4
|
|
8008494: 08009381 .word 0x08009381
|
|
8008498: 08009401 .word 0x08009401
|
|
|
|
0800849c <__lshift>:
|
|
800849c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
80084a0: 460c mov r4, r1
|
|
80084a2: 6849 ldr r1, [r1, #4]
|
|
80084a4: 6923 ldr r3, [r4, #16]
|
|
80084a6: eb03 1862 add.w r8, r3, r2, asr #5
|
|
80084aa: 68a3 ldr r3, [r4, #8]
|
|
80084ac: 4607 mov r7, r0
|
|
80084ae: 4691 mov r9, r2
|
|
80084b0: ea4f 1a62 mov.w sl, r2, asr #5
|
|
80084b4: f108 0601 add.w r6, r8, #1
|
|
80084b8: 42b3 cmp r3, r6
|
|
80084ba: db0b blt.n 80084d4 <__lshift+0x38>
|
|
80084bc: 4638 mov r0, r7
|
|
80084be: f7ff fde7 bl 8008090 <_Balloc>
|
|
80084c2: 4605 mov r5, r0
|
|
80084c4: b948 cbnz r0, 80084da <__lshift+0x3e>
|
|
80084c6: 4602 mov r2, r0
|
|
80084c8: 4b28 ldr r3, [pc, #160] @ (800856c <__lshift+0xd0>)
|
|
80084ca: 4829 ldr r0, [pc, #164] @ (8008570 <__lshift+0xd4>)
|
|
80084cc: f44f 71ef mov.w r1, #478 @ 0x1de
|
|
80084d0: f000 fd6a bl 8008fa8 <__assert_func>
|
|
80084d4: 3101 adds r1, #1
|
|
80084d6: 005b lsls r3, r3, #1
|
|
80084d8: e7ee b.n 80084b8 <__lshift+0x1c>
|
|
80084da: 2300 movs r3, #0
|
|
80084dc: f100 0114 add.w r1, r0, #20
|
|
80084e0: f100 0210 add.w r2, r0, #16
|
|
80084e4: 4618 mov r0, r3
|
|
80084e6: 4553 cmp r3, sl
|
|
80084e8: db33 blt.n 8008552 <__lshift+0xb6>
|
|
80084ea: 6920 ldr r0, [r4, #16]
|
|
80084ec: ea2a 7aea bic.w sl, sl, sl, asr #31
|
|
80084f0: f104 0314 add.w r3, r4, #20
|
|
80084f4: f019 091f ands.w r9, r9, #31
|
|
80084f8: eb01 018a add.w r1, r1, sl, lsl #2
|
|
80084fc: eb03 0c80 add.w ip, r3, r0, lsl #2
|
|
8008500: d02b beq.n 800855a <__lshift+0xbe>
|
|
8008502: f1c9 0e20 rsb lr, r9, #32
|
|
8008506: 468a mov sl, r1
|
|
8008508: 2200 movs r2, #0
|
|
800850a: 6818 ldr r0, [r3, #0]
|
|
800850c: fa00 f009 lsl.w r0, r0, r9
|
|
8008510: 4310 orrs r0, r2
|
|
8008512: f84a 0b04 str.w r0, [sl], #4
|
|
8008516: f853 2b04 ldr.w r2, [r3], #4
|
|
800851a: 459c cmp ip, r3
|
|
800851c: fa22 f20e lsr.w r2, r2, lr
|
|
8008520: d8f3 bhi.n 800850a <__lshift+0x6e>
|
|
8008522: ebac 0304 sub.w r3, ip, r4
|
|
8008526: 3b15 subs r3, #21
|
|
8008528: f023 0303 bic.w r3, r3, #3
|
|
800852c: 3304 adds r3, #4
|
|
800852e: f104 0015 add.w r0, r4, #21
|
|
8008532: 4560 cmp r0, ip
|
|
8008534: bf88 it hi
|
|
8008536: 2304 movhi r3, #4
|
|
8008538: 50ca str r2, [r1, r3]
|
|
800853a: b10a cbz r2, 8008540 <__lshift+0xa4>
|
|
800853c: f108 0602 add.w r6, r8, #2
|
|
8008540: 3e01 subs r6, #1
|
|
8008542: 4638 mov r0, r7
|
|
8008544: 612e str r6, [r5, #16]
|
|
8008546: 4621 mov r1, r4
|
|
8008548: f7ff fde2 bl 8008110 <_Bfree>
|
|
800854c: 4628 mov r0, r5
|
|
800854e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
8008552: f842 0f04 str.w r0, [r2, #4]!
|
|
8008556: 3301 adds r3, #1
|
|
8008558: e7c5 b.n 80084e6 <__lshift+0x4a>
|
|
800855a: 3904 subs r1, #4
|
|
800855c: f853 2b04 ldr.w r2, [r3], #4
|
|
8008560: f841 2f04 str.w r2, [r1, #4]!
|
|
8008564: 459c cmp ip, r3
|
|
8008566: d8f9 bhi.n 800855c <__lshift+0xc0>
|
|
8008568: e7ea b.n 8008540 <__lshift+0xa4>
|
|
800856a: bf00 nop
|
|
800856c: 080093f0 .word 0x080093f0
|
|
8008570: 08009401 .word 0x08009401
|
|
|
|
08008574 <__mcmp>:
|
|
8008574: 690a ldr r2, [r1, #16]
|
|
8008576: 4603 mov r3, r0
|
|
8008578: 6900 ldr r0, [r0, #16]
|
|
800857a: 1a80 subs r0, r0, r2
|
|
800857c: b530 push {r4, r5, lr}
|
|
800857e: d10e bne.n 800859e <__mcmp+0x2a>
|
|
8008580: 3314 adds r3, #20
|
|
8008582: 3114 adds r1, #20
|
|
8008584: eb03 0482 add.w r4, r3, r2, lsl #2
|
|
8008588: eb01 0182 add.w r1, r1, r2, lsl #2
|
|
800858c: f854 5d04 ldr.w r5, [r4, #-4]!
|
|
8008590: f851 2d04 ldr.w r2, [r1, #-4]!
|
|
8008594: 4295 cmp r5, r2
|
|
8008596: d003 beq.n 80085a0 <__mcmp+0x2c>
|
|
8008598: d205 bcs.n 80085a6 <__mcmp+0x32>
|
|
800859a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
800859e: bd30 pop {r4, r5, pc}
|
|
80085a0: 42a3 cmp r3, r4
|
|
80085a2: d3f3 bcc.n 800858c <__mcmp+0x18>
|
|
80085a4: e7fb b.n 800859e <__mcmp+0x2a>
|
|
80085a6: 2001 movs r0, #1
|
|
80085a8: e7f9 b.n 800859e <__mcmp+0x2a>
|
|
...
|
|
|
|
080085ac <__mdiff>:
|
|
80085ac: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
80085b0: 4689 mov r9, r1
|
|
80085b2: 4606 mov r6, r0
|
|
80085b4: 4611 mov r1, r2
|
|
80085b6: 4648 mov r0, r9
|
|
80085b8: 4614 mov r4, r2
|
|
80085ba: f7ff ffdb bl 8008574 <__mcmp>
|
|
80085be: 1e05 subs r5, r0, #0
|
|
80085c0: d112 bne.n 80085e8 <__mdiff+0x3c>
|
|
80085c2: 4629 mov r1, r5
|
|
80085c4: 4630 mov r0, r6
|
|
80085c6: f7ff fd63 bl 8008090 <_Balloc>
|
|
80085ca: 4602 mov r2, r0
|
|
80085cc: b928 cbnz r0, 80085da <__mdiff+0x2e>
|
|
80085ce: 4b3f ldr r3, [pc, #252] @ (80086cc <__mdiff+0x120>)
|
|
80085d0: f240 2137 movw r1, #567 @ 0x237
|
|
80085d4: 483e ldr r0, [pc, #248] @ (80086d0 <__mdiff+0x124>)
|
|
80085d6: f000 fce7 bl 8008fa8 <__assert_func>
|
|
80085da: 2301 movs r3, #1
|
|
80085dc: e9c0 3504 strd r3, r5, [r0, #16]
|
|
80085e0: 4610 mov r0, r2
|
|
80085e2: b003 add sp, #12
|
|
80085e4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
80085e8: bfbc itt lt
|
|
80085ea: 464b movlt r3, r9
|
|
80085ec: 46a1 movlt r9, r4
|
|
80085ee: 4630 mov r0, r6
|
|
80085f0: f8d9 1004 ldr.w r1, [r9, #4]
|
|
80085f4: bfba itte lt
|
|
80085f6: 461c movlt r4, r3
|
|
80085f8: 2501 movlt r5, #1
|
|
80085fa: 2500 movge r5, #0
|
|
80085fc: f7ff fd48 bl 8008090 <_Balloc>
|
|
8008600: 4602 mov r2, r0
|
|
8008602: b918 cbnz r0, 800860c <__mdiff+0x60>
|
|
8008604: 4b31 ldr r3, [pc, #196] @ (80086cc <__mdiff+0x120>)
|
|
8008606: f240 2145 movw r1, #581 @ 0x245
|
|
800860a: e7e3 b.n 80085d4 <__mdiff+0x28>
|
|
800860c: f8d9 7010 ldr.w r7, [r9, #16]
|
|
8008610: 6926 ldr r6, [r4, #16]
|
|
8008612: 60c5 str r5, [r0, #12]
|
|
8008614: f109 0310 add.w r3, r9, #16
|
|
8008618: f109 0514 add.w r5, r9, #20
|
|
800861c: f104 0e14 add.w lr, r4, #20
|
|
8008620: f100 0b14 add.w fp, r0, #20
|
|
8008624: eb05 0887 add.w r8, r5, r7, lsl #2
|
|
8008628: eb0e 0686 add.w r6, lr, r6, lsl #2
|
|
800862c: 9301 str r3, [sp, #4]
|
|
800862e: 46d9 mov r9, fp
|
|
8008630: f04f 0c00 mov.w ip, #0
|
|
8008634: 9b01 ldr r3, [sp, #4]
|
|
8008636: f85e 0b04 ldr.w r0, [lr], #4
|
|
800863a: f853 af04 ldr.w sl, [r3, #4]!
|
|
800863e: 9301 str r3, [sp, #4]
|
|
8008640: fa1f f38a uxth.w r3, sl
|
|
8008644: 4619 mov r1, r3
|
|
8008646: b283 uxth r3, r0
|
|
8008648: 1acb subs r3, r1, r3
|
|
800864a: 0c00 lsrs r0, r0, #16
|
|
800864c: 4463 add r3, ip
|
|
800864e: ebc0 401a rsb r0, r0, sl, lsr #16
|
|
8008652: eb00 4023 add.w r0, r0, r3, asr #16
|
|
8008656: b29b uxth r3, r3
|
|
8008658: ea43 4300 orr.w r3, r3, r0, lsl #16
|
|
800865c: 4576 cmp r6, lr
|
|
800865e: f849 3b04 str.w r3, [r9], #4
|
|
8008662: ea4f 4c20 mov.w ip, r0, asr #16
|
|
8008666: d8e5 bhi.n 8008634 <__mdiff+0x88>
|
|
8008668: 1b33 subs r3, r6, r4
|
|
800866a: 3b15 subs r3, #21
|
|
800866c: f023 0303 bic.w r3, r3, #3
|
|
8008670: 3415 adds r4, #21
|
|
8008672: 3304 adds r3, #4
|
|
8008674: 42a6 cmp r6, r4
|
|
8008676: bf38 it cc
|
|
8008678: 2304 movcc r3, #4
|
|
800867a: 441d add r5, r3
|
|
800867c: 445b add r3, fp
|
|
800867e: 461e mov r6, r3
|
|
8008680: 462c mov r4, r5
|
|
8008682: 4544 cmp r4, r8
|
|
8008684: d30e bcc.n 80086a4 <__mdiff+0xf8>
|
|
8008686: f108 0103 add.w r1, r8, #3
|
|
800868a: 1b49 subs r1, r1, r5
|
|
800868c: f021 0103 bic.w r1, r1, #3
|
|
8008690: 3d03 subs r5, #3
|
|
8008692: 45a8 cmp r8, r5
|
|
8008694: bf38 it cc
|
|
8008696: 2100 movcc r1, #0
|
|
8008698: 440b add r3, r1
|
|
800869a: f853 1d04 ldr.w r1, [r3, #-4]!
|
|
800869e: b191 cbz r1, 80086c6 <__mdiff+0x11a>
|
|
80086a0: 6117 str r7, [r2, #16]
|
|
80086a2: e79d b.n 80085e0 <__mdiff+0x34>
|
|
80086a4: f854 1b04 ldr.w r1, [r4], #4
|
|
80086a8: 46e6 mov lr, ip
|
|
80086aa: 0c08 lsrs r0, r1, #16
|
|
80086ac: fa1c fc81 uxtah ip, ip, r1
|
|
80086b0: 4471 add r1, lr
|
|
80086b2: eb00 402c add.w r0, r0, ip, asr #16
|
|
80086b6: b289 uxth r1, r1
|
|
80086b8: ea41 4100 orr.w r1, r1, r0, lsl #16
|
|
80086bc: f846 1b04 str.w r1, [r6], #4
|
|
80086c0: ea4f 4c20 mov.w ip, r0, asr #16
|
|
80086c4: e7dd b.n 8008682 <__mdiff+0xd6>
|
|
80086c6: 3f01 subs r7, #1
|
|
80086c8: e7e7 b.n 800869a <__mdiff+0xee>
|
|
80086ca: bf00 nop
|
|
80086cc: 080093f0 .word 0x080093f0
|
|
80086d0: 08009401 .word 0x08009401
|
|
|
|
080086d4 <__d2b>:
|
|
80086d4: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr}
|
|
80086d8: 460f mov r7, r1
|
|
80086da: 2101 movs r1, #1
|
|
80086dc: ec59 8b10 vmov r8, r9, d0
|
|
80086e0: 4616 mov r6, r2
|
|
80086e2: f7ff fcd5 bl 8008090 <_Balloc>
|
|
80086e6: 4604 mov r4, r0
|
|
80086e8: b930 cbnz r0, 80086f8 <__d2b+0x24>
|
|
80086ea: 4602 mov r2, r0
|
|
80086ec: 4b23 ldr r3, [pc, #140] @ (800877c <__d2b+0xa8>)
|
|
80086ee: 4824 ldr r0, [pc, #144] @ (8008780 <__d2b+0xac>)
|
|
80086f0: f240 310f movw r1, #783 @ 0x30f
|
|
80086f4: f000 fc58 bl 8008fa8 <__assert_func>
|
|
80086f8: f3c9 550a ubfx r5, r9, #20, #11
|
|
80086fc: f3c9 0313 ubfx r3, r9, #0, #20
|
|
8008700: b10d cbz r5, 8008706 <__d2b+0x32>
|
|
8008702: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
|
|
8008706: 9301 str r3, [sp, #4]
|
|
8008708: f1b8 0300 subs.w r3, r8, #0
|
|
800870c: d023 beq.n 8008756 <__d2b+0x82>
|
|
800870e: 4668 mov r0, sp
|
|
8008710: 9300 str r3, [sp, #0]
|
|
8008712: f7ff fd84 bl 800821e <__lo0bits>
|
|
8008716: e9dd 1200 ldrd r1, r2, [sp]
|
|
800871a: b1d0 cbz r0, 8008752 <__d2b+0x7e>
|
|
800871c: f1c0 0320 rsb r3, r0, #32
|
|
8008720: fa02 f303 lsl.w r3, r2, r3
|
|
8008724: 430b orrs r3, r1
|
|
8008726: 40c2 lsrs r2, r0
|
|
8008728: 6163 str r3, [r4, #20]
|
|
800872a: 9201 str r2, [sp, #4]
|
|
800872c: 9b01 ldr r3, [sp, #4]
|
|
800872e: 61a3 str r3, [r4, #24]
|
|
8008730: 2b00 cmp r3, #0
|
|
8008732: bf0c ite eq
|
|
8008734: 2201 moveq r2, #1
|
|
8008736: 2202 movne r2, #2
|
|
8008738: 6122 str r2, [r4, #16]
|
|
800873a: b1a5 cbz r5, 8008766 <__d2b+0x92>
|
|
800873c: f2a5 4533 subw r5, r5, #1075 @ 0x433
|
|
8008740: 4405 add r5, r0
|
|
8008742: 603d str r5, [r7, #0]
|
|
8008744: f1c0 0035 rsb r0, r0, #53 @ 0x35
|
|
8008748: 6030 str r0, [r6, #0]
|
|
800874a: 4620 mov r0, r4
|
|
800874c: b003 add sp, #12
|
|
800874e: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc}
|
|
8008752: 6161 str r1, [r4, #20]
|
|
8008754: e7ea b.n 800872c <__d2b+0x58>
|
|
8008756: a801 add r0, sp, #4
|
|
8008758: f7ff fd61 bl 800821e <__lo0bits>
|
|
800875c: 9b01 ldr r3, [sp, #4]
|
|
800875e: 6163 str r3, [r4, #20]
|
|
8008760: 3020 adds r0, #32
|
|
8008762: 2201 movs r2, #1
|
|
8008764: e7e8 b.n 8008738 <__d2b+0x64>
|
|
8008766: eb04 0382 add.w r3, r4, r2, lsl #2
|
|
800876a: f2a0 4032 subw r0, r0, #1074 @ 0x432
|
|
800876e: 6038 str r0, [r7, #0]
|
|
8008770: 6918 ldr r0, [r3, #16]
|
|
8008772: f7ff fd35 bl 80081e0 <__hi0bits>
|
|
8008776: ebc0 1042 rsb r0, r0, r2, lsl #5
|
|
800877a: e7e5 b.n 8008748 <__d2b+0x74>
|
|
800877c: 080093f0 .word 0x080093f0
|
|
8008780: 08009401 .word 0x08009401
|
|
|
|
08008784 <__ssputs_r>:
|
|
8008784: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
|
|
8008788: 688e ldr r6, [r1, #8]
|
|
800878a: 461f mov r7, r3
|
|
800878c: 42be cmp r6, r7
|
|
800878e: 680b ldr r3, [r1, #0]
|
|
8008790: 4682 mov sl, r0
|
|
8008792: 460c mov r4, r1
|
|
8008794: 4690 mov r8, r2
|
|
8008796: d82d bhi.n 80087f4 <__ssputs_r+0x70>
|
|
8008798: f9b1 200c ldrsh.w r2, [r1, #12]
|
|
800879c: f412 6f90 tst.w r2, #1152 @ 0x480
|
|
80087a0: d026 beq.n 80087f0 <__ssputs_r+0x6c>
|
|
80087a2: 6965 ldr r5, [r4, #20]
|
|
80087a4: 6909 ldr r1, [r1, #16]
|
|
80087a6: eb05 0545 add.w r5, r5, r5, lsl #1
|
|
80087aa: eba3 0901 sub.w r9, r3, r1
|
|
80087ae: eb05 75d5 add.w r5, r5, r5, lsr #31
|
|
80087b2: 1c7b adds r3, r7, #1
|
|
80087b4: 444b add r3, r9
|
|
80087b6: 106d asrs r5, r5, #1
|
|
80087b8: 429d cmp r5, r3
|
|
80087ba: bf38 it cc
|
|
80087bc: 461d movcc r5, r3
|
|
80087be: 0553 lsls r3, r2, #21
|
|
80087c0: d527 bpl.n 8008812 <__ssputs_r+0x8e>
|
|
80087c2: 4629 mov r1, r5
|
|
80087c4: f7ff fbd8 bl 8007f78 <_malloc_r>
|
|
80087c8: 4606 mov r6, r0
|
|
80087ca: b360 cbz r0, 8008826 <__ssputs_r+0xa2>
|
|
80087cc: 6921 ldr r1, [r4, #16]
|
|
80087ce: 464a mov r2, r9
|
|
80087d0: f000 fbdc bl 8008f8c <memcpy>
|
|
80087d4: 89a3 ldrh r3, [r4, #12]
|
|
80087d6: f423 6390 bic.w r3, r3, #1152 @ 0x480
|
|
80087da: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
80087de: 81a3 strh r3, [r4, #12]
|
|
80087e0: 6126 str r6, [r4, #16]
|
|
80087e2: 6165 str r5, [r4, #20]
|
|
80087e4: 444e add r6, r9
|
|
80087e6: eba5 0509 sub.w r5, r5, r9
|
|
80087ea: 6026 str r6, [r4, #0]
|
|
80087ec: 60a5 str r5, [r4, #8]
|
|
80087ee: 463e mov r6, r7
|
|
80087f0: 42be cmp r6, r7
|
|
80087f2: d900 bls.n 80087f6 <__ssputs_r+0x72>
|
|
80087f4: 463e mov r6, r7
|
|
80087f6: 6820 ldr r0, [r4, #0]
|
|
80087f8: 4632 mov r2, r6
|
|
80087fa: 4641 mov r1, r8
|
|
80087fc: f000 fb9c bl 8008f38 <memmove>
|
|
8008800: 68a3 ldr r3, [r4, #8]
|
|
8008802: 1b9b subs r3, r3, r6
|
|
8008804: 60a3 str r3, [r4, #8]
|
|
8008806: 6823 ldr r3, [r4, #0]
|
|
8008808: 4433 add r3, r6
|
|
800880a: 6023 str r3, [r4, #0]
|
|
800880c: 2000 movs r0, #0
|
|
800880e: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
|
|
8008812: 462a mov r2, r5
|
|
8008814: f000 fc0c bl 8009030 <_realloc_r>
|
|
8008818: 4606 mov r6, r0
|
|
800881a: 2800 cmp r0, #0
|
|
800881c: d1e0 bne.n 80087e0 <__ssputs_r+0x5c>
|
|
800881e: 6921 ldr r1, [r4, #16]
|
|
8008820: 4650 mov r0, sl
|
|
8008822: f7ff fb35 bl 8007e90 <_free_r>
|
|
8008826: 230c movs r3, #12
|
|
8008828: f8ca 3000 str.w r3, [sl]
|
|
800882c: 89a3 ldrh r3, [r4, #12]
|
|
800882e: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
8008832: 81a3 strh r3, [r4, #12]
|
|
8008834: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8008838: e7e9 b.n 800880e <__ssputs_r+0x8a>
|
|
...
|
|
|
|
0800883c <_svfiprintf_r>:
|
|
800883c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
8008840: 4698 mov r8, r3
|
|
8008842: 898b ldrh r3, [r1, #12]
|
|
8008844: 061b lsls r3, r3, #24
|
|
8008846: b09d sub sp, #116 @ 0x74
|
|
8008848: 4607 mov r7, r0
|
|
800884a: 460d mov r5, r1
|
|
800884c: 4614 mov r4, r2
|
|
800884e: d510 bpl.n 8008872 <_svfiprintf_r+0x36>
|
|
8008850: 690b ldr r3, [r1, #16]
|
|
8008852: b973 cbnz r3, 8008872 <_svfiprintf_r+0x36>
|
|
8008854: 2140 movs r1, #64 @ 0x40
|
|
8008856: f7ff fb8f bl 8007f78 <_malloc_r>
|
|
800885a: 6028 str r0, [r5, #0]
|
|
800885c: 6128 str r0, [r5, #16]
|
|
800885e: b930 cbnz r0, 800886e <_svfiprintf_r+0x32>
|
|
8008860: 230c movs r3, #12
|
|
8008862: 603b str r3, [r7, #0]
|
|
8008864: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8008868: b01d add sp, #116 @ 0x74
|
|
800886a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
800886e: 2340 movs r3, #64 @ 0x40
|
|
8008870: 616b str r3, [r5, #20]
|
|
8008872: 2300 movs r3, #0
|
|
8008874: 9309 str r3, [sp, #36] @ 0x24
|
|
8008876: 2320 movs r3, #32
|
|
8008878: f88d 3029 strb.w r3, [sp, #41] @ 0x29
|
|
800887c: f8cd 800c str.w r8, [sp, #12]
|
|
8008880: 2330 movs r3, #48 @ 0x30
|
|
8008882: f8df 819c ldr.w r8, [pc, #412] @ 8008a20 <_svfiprintf_r+0x1e4>
|
|
8008886: f88d 302a strb.w r3, [sp, #42] @ 0x2a
|
|
800888a: f04f 0901 mov.w r9, #1
|
|
800888e: 4623 mov r3, r4
|
|
8008890: 469a mov sl, r3
|
|
8008892: f813 2b01 ldrb.w r2, [r3], #1
|
|
8008896: b10a cbz r2, 800889c <_svfiprintf_r+0x60>
|
|
8008898: 2a25 cmp r2, #37 @ 0x25
|
|
800889a: d1f9 bne.n 8008890 <_svfiprintf_r+0x54>
|
|
800889c: ebba 0b04 subs.w fp, sl, r4
|
|
80088a0: d00b beq.n 80088ba <_svfiprintf_r+0x7e>
|
|
80088a2: 465b mov r3, fp
|
|
80088a4: 4622 mov r2, r4
|
|
80088a6: 4629 mov r1, r5
|
|
80088a8: 4638 mov r0, r7
|
|
80088aa: f7ff ff6b bl 8008784 <__ssputs_r>
|
|
80088ae: 3001 adds r0, #1
|
|
80088b0: f000 80a7 beq.w 8008a02 <_svfiprintf_r+0x1c6>
|
|
80088b4: 9a09 ldr r2, [sp, #36] @ 0x24
|
|
80088b6: 445a add r2, fp
|
|
80088b8: 9209 str r2, [sp, #36] @ 0x24
|
|
80088ba: f89a 3000 ldrb.w r3, [sl]
|
|
80088be: 2b00 cmp r3, #0
|
|
80088c0: f000 809f beq.w 8008a02 <_svfiprintf_r+0x1c6>
|
|
80088c4: 2300 movs r3, #0
|
|
80088c6: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
80088ca: e9cd 2305 strd r2, r3, [sp, #20]
|
|
80088ce: f10a 0a01 add.w sl, sl, #1
|
|
80088d2: 9304 str r3, [sp, #16]
|
|
80088d4: 9307 str r3, [sp, #28]
|
|
80088d6: f88d 3053 strb.w r3, [sp, #83] @ 0x53
|
|
80088da: 931a str r3, [sp, #104] @ 0x68
|
|
80088dc: 4654 mov r4, sl
|
|
80088de: 2205 movs r2, #5
|
|
80088e0: f814 1b01 ldrb.w r1, [r4], #1
|
|
80088e4: 484e ldr r0, [pc, #312] @ (8008a20 <_svfiprintf_r+0x1e4>)
|
|
80088e6: f7f7 fc73 bl 80001d0 <memchr>
|
|
80088ea: 9a04 ldr r2, [sp, #16]
|
|
80088ec: b9d8 cbnz r0, 8008926 <_svfiprintf_r+0xea>
|
|
80088ee: 06d0 lsls r0, r2, #27
|
|
80088f0: bf44 itt mi
|
|
80088f2: 2320 movmi r3, #32
|
|
80088f4: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
|
|
80088f8: 0711 lsls r1, r2, #28
|
|
80088fa: bf44 itt mi
|
|
80088fc: 232b movmi r3, #43 @ 0x2b
|
|
80088fe: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
|
|
8008902: f89a 3000 ldrb.w r3, [sl]
|
|
8008906: 2b2a cmp r3, #42 @ 0x2a
|
|
8008908: d015 beq.n 8008936 <_svfiprintf_r+0xfa>
|
|
800890a: 9a07 ldr r2, [sp, #28]
|
|
800890c: 4654 mov r4, sl
|
|
800890e: 2000 movs r0, #0
|
|
8008910: f04f 0c0a mov.w ip, #10
|
|
8008914: 4621 mov r1, r4
|
|
8008916: f811 3b01 ldrb.w r3, [r1], #1
|
|
800891a: 3b30 subs r3, #48 @ 0x30
|
|
800891c: 2b09 cmp r3, #9
|
|
800891e: d94b bls.n 80089b8 <_svfiprintf_r+0x17c>
|
|
8008920: b1b0 cbz r0, 8008950 <_svfiprintf_r+0x114>
|
|
8008922: 9207 str r2, [sp, #28]
|
|
8008924: e014 b.n 8008950 <_svfiprintf_r+0x114>
|
|
8008926: eba0 0308 sub.w r3, r0, r8
|
|
800892a: fa09 f303 lsl.w r3, r9, r3
|
|
800892e: 4313 orrs r3, r2
|
|
8008930: 9304 str r3, [sp, #16]
|
|
8008932: 46a2 mov sl, r4
|
|
8008934: e7d2 b.n 80088dc <_svfiprintf_r+0xa0>
|
|
8008936: 9b03 ldr r3, [sp, #12]
|
|
8008938: 1d19 adds r1, r3, #4
|
|
800893a: 681b ldr r3, [r3, #0]
|
|
800893c: 9103 str r1, [sp, #12]
|
|
800893e: 2b00 cmp r3, #0
|
|
8008940: bfbb ittet lt
|
|
8008942: 425b neglt r3, r3
|
|
8008944: f042 0202 orrlt.w r2, r2, #2
|
|
8008948: 9307 strge r3, [sp, #28]
|
|
800894a: 9307 strlt r3, [sp, #28]
|
|
800894c: bfb8 it lt
|
|
800894e: 9204 strlt r2, [sp, #16]
|
|
8008950: 7823 ldrb r3, [r4, #0]
|
|
8008952: 2b2e cmp r3, #46 @ 0x2e
|
|
8008954: d10a bne.n 800896c <_svfiprintf_r+0x130>
|
|
8008956: 7863 ldrb r3, [r4, #1]
|
|
8008958: 2b2a cmp r3, #42 @ 0x2a
|
|
800895a: d132 bne.n 80089c2 <_svfiprintf_r+0x186>
|
|
800895c: 9b03 ldr r3, [sp, #12]
|
|
800895e: 1d1a adds r2, r3, #4
|
|
8008960: 681b ldr r3, [r3, #0]
|
|
8008962: 9203 str r2, [sp, #12]
|
|
8008964: ea43 73e3 orr.w r3, r3, r3, asr #31
|
|
8008968: 3402 adds r4, #2
|
|
800896a: 9305 str r3, [sp, #20]
|
|
800896c: f8df a0c0 ldr.w sl, [pc, #192] @ 8008a30 <_svfiprintf_r+0x1f4>
|
|
8008970: 7821 ldrb r1, [r4, #0]
|
|
8008972: 2203 movs r2, #3
|
|
8008974: 4650 mov r0, sl
|
|
8008976: f7f7 fc2b bl 80001d0 <memchr>
|
|
800897a: b138 cbz r0, 800898c <_svfiprintf_r+0x150>
|
|
800897c: 9b04 ldr r3, [sp, #16]
|
|
800897e: eba0 000a sub.w r0, r0, sl
|
|
8008982: 2240 movs r2, #64 @ 0x40
|
|
8008984: 4082 lsls r2, r0
|
|
8008986: 4313 orrs r3, r2
|
|
8008988: 3401 adds r4, #1
|
|
800898a: 9304 str r3, [sp, #16]
|
|
800898c: f814 1b01 ldrb.w r1, [r4], #1
|
|
8008990: 4824 ldr r0, [pc, #144] @ (8008a24 <_svfiprintf_r+0x1e8>)
|
|
8008992: f88d 1028 strb.w r1, [sp, #40] @ 0x28
|
|
8008996: 2206 movs r2, #6
|
|
8008998: f7f7 fc1a bl 80001d0 <memchr>
|
|
800899c: 2800 cmp r0, #0
|
|
800899e: d036 beq.n 8008a0e <_svfiprintf_r+0x1d2>
|
|
80089a0: 4b21 ldr r3, [pc, #132] @ (8008a28 <_svfiprintf_r+0x1ec>)
|
|
80089a2: bb1b cbnz r3, 80089ec <_svfiprintf_r+0x1b0>
|
|
80089a4: 9b03 ldr r3, [sp, #12]
|
|
80089a6: 3307 adds r3, #7
|
|
80089a8: f023 0307 bic.w r3, r3, #7
|
|
80089ac: 3308 adds r3, #8
|
|
80089ae: 9303 str r3, [sp, #12]
|
|
80089b0: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
80089b2: 4433 add r3, r6
|
|
80089b4: 9309 str r3, [sp, #36] @ 0x24
|
|
80089b6: e76a b.n 800888e <_svfiprintf_r+0x52>
|
|
80089b8: fb0c 3202 mla r2, ip, r2, r3
|
|
80089bc: 460c mov r4, r1
|
|
80089be: 2001 movs r0, #1
|
|
80089c0: e7a8 b.n 8008914 <_svfiprintf_r+0xd8>
|
|
80089c2: 2300 movs r3, #0
|
|
80089c4: 3401 adds r4, #1
|
|
80089c6: 9305 str r3, [sp, #20]
|
|
80089c8: 4619 mov r1, r3
|
|
80089ca: f04f 0c0a mov.w ip, #10
|
|
80089ce: 4620 mov r0, r4
|
|
80089d0: f810 2b01 ldrb.w r2, [r0], #1
|
|
80089d4: 3a30 subs r2, #48 @ 0x30
|
|
80089d6: 2a09 cmp r2, #9
|
|
80089d8: d903 bls.n 80089e2 <_svfiprintf_r+0x1a6>
|
|
80089da: 2b00 cmp r3, #0
|
|
80089dc: d0c6 beq.n 800896c <_svfiprintf_r+0x130>
|
|
80089de: 9105 str r1, [sp, #20]
|
|
80089e0: e7c4 b.n 800896c <_svfiprintf_r+0x130>
|
|
80089e2: fb0c 2101 mla r1, ip, r1, r2
|
|
80089e6: 4604 mov r4, r0
|
|
80089e8: 2301 movs r3, #1
|
|
80089ea: e7f0 b.n 80089ce <_svfiprintf_r+0x192>
|
|
80089ec: ab03 add r3, sp, #12
|
|
80089ee: 9300 str r3, [sp, #0]
|
|
80089f0: 462a mov r2, r5
|
|
80089f2: 4b0e ldr r3, [pc, #56] @ (8008a2c <_svfiprintf_r+0x1f0>)
|
|
80089f4: a904 add r1, sp, #16
|
|
80089f6: 4638 mov r0, r7
|
|
80089f8: f7fd fe80 bl 80066fc <_printf_float>
|
|
80089fc: 1c42 adds r2, r0, #1
|
|
80089fe: 4606 mov r6, r0
|
|
8008a00: d1d6 bne.n 80089b0 <_svfiprintf_r+0x174>
|
|
8008a02: 89ab ldrh r3, [r5, #12]
|
|
8008a04: 065b lsls r3, r3, #25
|
|
8008a06: f53f af2d bmi.w 8008864 <_svfiprintf_r+0x28>
|
|
8008a0a: 9809 ldr r0, [sp, #36] @ 0x24
|
|
8008a0c: e72c b.n 8008868 <_svfiprintf_r+0x2c>
|
|
8008a0e: ab03 add r3, sp, #12
|
|
8008a10: 9300 str r3, [sp, #0]
|
|
8008a12: 462a mov r2, r5
|
|
8008a14: 4b05 ldr r3, [pc, #20] @ (8008a2c <_svfiprintf_r+0x1f0>)
|
|
8008a16: a904 add r1, sp, #16
|
|
8008a18: 4638 mov r0, r7
|
|
8008a1a: f7fe f907 bl 8006c2c <_printf_i>
|
|
8008a1e: e7ed b.n 80089fc <_svfiprintf_r+0x1c0>
|
|
8008a20: 0800945a .word 0x0800945a
|
|
8008a24: 08009464 .word 0x08009464
|
|
8008a28: 080066fd .word 0x080066fd
|
|
8008a2c: 08008785 .word 0x08008785
|
|
8008a30: 08009460 .word 0x08009460
|
|
|
|
08008a34 <__sfputc_r>:
|
|
8008a34: 6893 ldr r3, [r2, #8]
|
|
8008a36: 3b01 subs r3, #1
|
|
8008a38: 2b00 cmp r3, #0
|
|
8008a3a: b410 push {r4}
|
|
8008a3c: 6093 str r3, [r2, #8]
|
|
8008a3e: da08 bge.n 8008a52 <__sfputc_r+0x1e>
|
|
8008a40: 6994 ldr r4, [r2, #24]
|
|
8008a42: 42a3 cmp r3, r4
|
|
8008a44: db01 blt.n 8008a4a <__sfputc_r+0x16>
|
|
8008a46: 290a cmp r1, #10
|
|
8008a48: d103 bne.n 8008a52 <__sfputc_r+0x1e>
|
|
8008a4a: f85d 4b04 ldr.w r4, [sp], #4
|
|
8008a4e: f000 b9df b.w 8008e10 <__swbuf_r>
|
|
8008a52: 6813 ldr r3, [r2, #0]
|
|
8008a54: 1c58 adds r0, r3, #1
|
|
8008a56: 6010 str r0, [r2, #0]
|
|
8008a58: 7019 strb r1, [r3, #0]
|
|
8008a5a: 4608 mov r0, r1
|
|
8008a5c: f85d 4b04 ldr.w r4, [sp], #4
|
|
8008a60: 4770 bx lr
|
|
|
|
08008a62 <__sfputs_r>:
|
|
8008a62: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8008a64: 4606 mov r6, r0
|
|
8008a66: 460f mov r7, r1
|
|
8008a68: 4614 mov r4, r2
|
|
8008a6a: 18d5 adds r5, r2, r3
|
|
8008a6c: 42ac cmp r4, r5
|
|
8008a6e: d101 bne.n 8008a74 <__sfputs_r+0x12>
|
|
8008a70: 2000 movs r0, #0
|
|
8008a72: e007 b.n 8008a84 <__sfputs_r+0x22>
|
|
8008a74: f814 1b01 ldrb.w r1, [r4], #1
|
|
8008a78: 463a mov r2, r7
|
|
8008a7a: 4630 mov r0, r6
|
|
8008a7c: f7ff ffda bl 8008a34 <__sfputc_r>
|
|
8008a80: 1c43 adds r3, r0, #1
|
|
8008a82: d1f3 bne.n 8008a6c <__sfputs_r+0xa>
|
|
8008a84: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
...
|
|
|
|
08008a88 <_vfiprintf_r>:
|
|
8008a88: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr}
|
|
8008a8c: 460d mov r5, r1
|
|
8008a8e: b09d sub sp, #116 @ 0x74
|
|
8008a90: 4614 mov r4, r2
|
|
8008a92: 4698 mov r8, r3
|
|
8008a94: 4606 mov r6, r0
|
|
8008a96: b118 cbz r0, 8008aa0 <_vfiprintf_r+0x18>
|
|
8008a98: 6a03 ldr r3, [r0, #32]
|
|
8008a9a: b90b cbnz r3, 8008aa0 <_vfiprintf_r+0x18>
|
|
8008a9c: f7fe fa70 bl 8006f80 <__sinit>
|
|
8008aa0: 6e6b ldr r3, [r5, #100] @ 0x64
|
|
8008aa2: 07d9 lsls r1, r3, #31
|
|
8008aa4: d405 bmi.n 8008ab2 <_vfiprintf_r+0x2a>
|
|
8008aa6: 89ab ldrh r3, [r5, #12]
|
|
8008aa8: 059a lsls r2, r3, #22
|
|
8008aaa: d402 bmi.n 8008ab2 <_vfiprintf_r+0x2a>
|
|
8008aac: 6da8 ldr r0, [r5, #88] @ 0x58
|
|
8008aae: f7fe fb92 bl 80071d6 <__retarget_lock_acquire_recursive>
|
|
8008ab2: 89ab ldrh r3, [r5, #12]
|
|
8008ab4: 071b lsls r3, r3, #28
|
|
8008ab6: d501 bpl.n 8008abc <_vfiprintf_r+0x34>
|
|
8008ab8: 692b ldr r3, [r5, #16]
|
|
8008aba: b99b cbnz r3, 8008ae4 <_vfiprintf_r+0x5c>
|
|
8008abc: 4629 mov r1, r5
|
|
8008abe: 4630 mov r0, r6
|
|
8008ac0: f000 f9e4 bl 8008e8c <__swsetup_r>
|
|
8008ac4: b170 cbz r0, 8008ae4 <_vfiprintf_r+0x5c>
|
|
8008ac6: 6e6b ldr r3, [r5, #100] @ 0x64
|
|
8008ac8: 07dc lsls r4, r3, #31
|
|
8008aca: d504 bpl.n 8008ad6 <_vfiprintf_r+0x4e>
|
|
8008acc: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8008ad0: b01d add sp, #116 @ 0x74
|
|
8008ad2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc}
|
|
8008ad6: 89ab ldrh r3, [r5, #12]
|
|
8008ad8: 0598 lsls r0, r3, #22
|
|
8008ada: d4f7 bmi.n 8008acc <_vfiprintf_r+0x44>
|
|
8008adc: 6da8 ldr r0, [r5, #88] @ 0x58
|
|
8008ade: f7fe fb7b bl 80071d8 <__retarget_lock_release_recursive>
|
|
8008ae2: e7f3 b.n 8008acc <_vfiprintf_r+0x44>
|
|
8008ae4: 2300 movs r3, #0
|
|
8008ae6: 9309 str r3, [sp, #36] @ 0x24
|
|
8008ae8: 2320 movs r3, #32
|
|
8008aea: f88d 3029 strb.w r3, [sp, #41] @ 0x29
|
|
8008aee: f8cd 800c str.w r8, [sp, #12]
|
|
8008af2: 2330 movs r3, #48 @ 0x30
|
|
8008af4: f8df 81ac ldr.w r8, [pc, #428] @ 8008ca4 <_vfiprintf_r+0x21c>
|
|
8008af8: f88d 302a strb.w r3, [sp, #42] @ 0x2a
|
|
8008afc: f04f 0901 mov.w r9, #1
|
|
8008b00: 4623 mov r3, r4
|
|
8008b02: 469a mov sl, r3
|
|
8008b04: f813 2b01 ldrb.w r2, [r3], #1
|
|
8008b08: b10a cbz r2, 8008b0e <_vfiprintf_r+0x86>
|
|
8008b0a: 2a25 cmp r2, #37 @ 0x25
|
|
8008b0c: d1f9 bne.n 8008b02 <_vfiprintf_r+0x7a>
|
|
8008b0e: ebba 0b04 subs.w fp, sl, r4
|
|
8008b12: d00b beq.n 8008b2c <_vfiprintf_r+0xa4>
|
|
8008b14: 465b mov r3, fp
|
|
8008b16: 4622 mov r2, r4
|
|
8008b18: 4629 mov r1, r5
|
|
8008b1a: 4630 mov r0, r6
|
|
8008b1c: f7ff ffa1 bl 8008a62 <__sfputs_r>
|
|
8008b20: 3001 adds r0, #1
|
|
8008b22: f000 80a7 beq.w 8008c74 <_vfiprintf_r+0x1ec>
|
|
8008b26: 9a09 ldr r2, [sp, #36] @ 0x24
|
|
8008b28: 445a add r2, fp
|
|
8008b2a: 9209 str r2, [sp, #36] @ 0x24
|
|
8008b2c: f89a 3000 ldrb.w r3, [sl]
|
|
8008b30: 2b00 cmp r3, #0
|
|
8008b32: f000 809f beq.w 8008c74 <_vfiprintf_r+0x1ec>
|
|
8008b36: 2300 movs r3, #0
|
|
8008b38: f04f 32ff mov.w r2, #4294967295 @ 0xffffffff
|
|
8008b3c: e9cd 2305 strd r2, r3, [sp, #20]
|
|
8008b40: f10a 0a01 add.w sl, sl, #1
|
|
8008b44: 9304 str r3, [sp, #16]
|
|
8008b46: 9307 str r3, [sp, #28]
|
|
8008b48: f88d 3053 strb.w r3, [sp, #83] @ 0x53
|
|
8008b4c: 931a str r3, [sp, #104] @ 0x68
|
|
8008b4e: 4654 mov r4, sl
|
|
8008b50: 2205 movs r2, #5
|
|
8008b52: f814 1b01 ldrb.w r1, [r4], #1
|
|
8008b56: 4853 ldr r0, [pc, #332] @ (8008ca4 <_vfiprintf_r+0x21c>)
|
|
8008b58: f7f7 fb3a bl 80001d0 <memchr>
|
|
8008b5c: 9a04 ldr r2, [sp, #16]
|
|
8008b5e: b9d8 cbnz r0, 8008b98 <_vfiprintf_r+0x110>
|
|
8008b60: 06d1 lsls r1, r2, #27
|
|
8008b62: bf44 itt mi
|
|
8008b64: 2320 movmi r3, #32
|
|
8008b66: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
|
|
8008b6a: 0713 lsls r3, r2, #28
|
|
8008b6c: bf44 itt mi
|
|
8008b6e: 232b movmi r3, #43 @ 0x2b
|
|
8008b70: f88d 3053 strbmi.w r3, [sp, #83] @ 0x53
|
|
8008b74: f89a 3000 ldrb.w r3, [sl]
|
|
8008b78: 2b2a cmp r3, #42 @ 0x2a
|
|
8008b7a: d015 beq.n 8008ba8 <_vfiprintf_r+0x120>
|
|
8008b7c: 9a07 ldr r2, [sp, #28]
|
|
8008b7e: 4654 mov r4, sl
|
|
8008b80: 2000 movs r0, #0
|
|
8008b82: f04f 0c0a mov.w ip, #10
|
|
8008b86: 4621 mov r1, r4
|
|
8008b88: f811 3b01 ldrb.w r3, [r1], #1
|
|
8008b8c: 3b30 subs r3, #48 @ 0x30
|
|
8008b8e: 2b09 cmp r3, #9
|
|
8008b90: d94b bls.n 8008c2a <_vfiprintf_r+0x1a2>
|
|
8008b92: b1b0 cbz r0, 8008bc2 <_vfiprintf_r+0x13a>
|
|
8008b94: 9207 str r2, [sp, #28]
|
|
8008b96: e014 b.n 8008bc2 <_vfiprintf_r+0x13a>
|
|
8008b98: eba0 0308 sub.w r3, r0, r8
|
|
8008b9c: fa09 f303 lsl.w r3, r9, r3
|
|
8008ba0: 4313 orrs r3, r2
|
|
8008ba2: 9304 str r3, [sp, #16]
|
|
8008ba4: 46a2 mov sl, r4
|
|
8008ba6: e7d2 b.n 8008b4e <_vfiprintf_r+0xc6>
|
|
8008ba8: 9b03 ldr r3, [sp, #12]
|
|
8008baa: 1d19 adds r1, r3, #4
|
|
8008bac: 681b ldr r3, [r3, #0]
|
|
8008bae: 9103 str r1, [sp, #12]
|
|
8008bb0: 2b00 cmp r3, #0
|
|
8008bb2: bfbb ittet lt
|
|
8008bb4: 425b neglt r3, r3
|
|
8008bb6: f042 0202 orrlt.w r2, r2, #2
|
|
8008bba: 9307 strge r3, [sp, #28]
|
|
8008bbc: 9307 strlt r3, [sp, #28]
|
|
8008bbe: bfb8 it lt
|
|
8008bc0: 9204 strlt r2, [sp, #16]
|
|
8008bc2: 7823 ldrb r3, [r4, #0]
|
|
8008bc4: 2b2e cmp r3, #46 @ 0x2e
|
|
8008bc6: d10a bne.n 8008bde <_vfiprintf_r+0x156>
|
|
8008bc8: 7863 ldrb r3, [r4, #1]
|
|
8008bca: 2b2a cmp r3, #42 @ 0x2a
|
|
8008bcc: d132 bne.n 8008c34 <_vfiprintf_r+0x1ac>
|
|
8008bce: 9b03 ldr r3, [sp, #12]
|
|
8008bd0: 1d1a adds r2, r3, #4
|
|
8008bd2: 681b ldr r3, [r3, #0]
|
|
8008bd4: 9203 str r2, [sp, #12]
|
|
8008bd6: ea43 73e3 orr.w r3, r3, r3, asr #31
|
|
8008bda: 3402 adds r4, #2
|
|
8008bdc: 9305 str r3, [sp, #20]
|
|
8008bde: f8df a0d4 ldr.w sl, [pc, #212] @ 8008cb4 <_vfiprintf_r+0x22c>
|
|
8008be2: 7821 ldrb r1, [r4, #0]
|
|
8008be4: 2203 movs r2, #3
|
|
8008be6: 4650 mov r0, sl
|
|
8008be8: f7f7 faf2 bl 80001d0 <memchr>
|
|
8008bec: b138 cbz r0, 8008bfe <_vfiprintf_r+0x176>
|
|
8008bee: 9b04 ldr r3, [sp, #16]
|
|
8008bf0: eba0 000a sub.w r0, r0, sl
|
|
8008bf4: 2240 movs r2, #64 @ 0x40
|
|
8008bf6: 4082 lsls r2, r0
|
|
8008bf8: 4313 orrs r3, r2
|
|
8008bfa: 3401 adds r4, #1
|
|
8008bfc: 9304 str r3, [sp, #16]
|
|
8008bfe: f814 1b01 ldrb.w r1, [r4], #1
|
|
8008c02: 4829 ldr r0, [pc, #164] @ (8008ca8 <_vfiprintf_r+0x220>)
|
|
8008c04: f88d 1028 strb.w r1, [sp, #40] @ 0x28
|
|
8008c08: 2206 movs r2, #6
|
|
8008c0a: f7f7 fae1 bl 80001d0 <memchr>
|
|
8008c0e: 2800 cmp r0, #0
|
|
8008c10: d03f beq.n 8008c92 <_vfiprintf_r+0x20a>
|
|
8008c12: 4b26 ldr r3, [pc, #152] @ (8008cac <_vfiprintf_r+0x224>)
|
|
8008c14: bb1b cbnz r3, 8008c5e <_vfiprintf_r+0x1d6>
|
|
8008c16: 9b03 ldr r3, [sp, #12]
|
|
8008c18: 3307 adds r3, #7
|
|
8008c1a: f023 0307 bic.w r3, r3, #7
|
|
8008c1e: 3308 adds r3, #8
|
|
8008c20: 9303 str r3, [sp, #12]
|
|
8008c22: 9b09 ldr r3, [sp, #36] @ 0x24
|
|
8008c24: 443b add r3, r7
|
|
8008c26: 9309 str r3, [sp, #36] @ 0x24
|
|
8008c28: e76a b.n 8008b00 <_vfiprintf_r+0x78>
|
|
8008c2a: fb0c 3202 mla r2, ip, r2, r3
|
|
8008c2e: 460c mov r4, r1
|
|
8008c30: 2001 movs r0, #1
|
|
8008c32: e7a8 b.n 8008b86 <_vfiprintf_r+0xfe>
|
|
8008c34: 2300 movs r3, #0
|
|
8008c36: 3401 adds r4, #1
|
|
8008c38: 9305 str r3, [sp, #20]
|
|
8008c3a: 4619 mov r1, r3
|
|
8008c3c: f04f 0c0a mov.w ip, #10
|
|
8008c40: 4620 mov r0, r4
|
|
8008c42: f810 2b01 ldrb.w r2, [r0], #1
|
|
8008c46: 3a30 subs r2, #48 @ 0x30
|
|
8008c48: 2a09 cmp r2, #9
|
|
8008c4a: d903 bls.n 8008c54 <_vfiprintf_r+0x1cc>
|
|
8008c4c: 2b00 cmp r3, #0
|
|
8008c4e: d0c6 beq.n 8008bde <_vfiprintf_r+0x156>
|
|
8008c50: 9105 str r1, [sp, #20]
|
|
8008c52: e7c4 b.n 8008bde <_vfiprintf_r+0x156>
|
|
8008c54: fb0c 2101 mla r1, ip, r1, r2
|
|
8008c58: 4604 mov r4, r0
|
|
8008c5a: 2301 movs r3, #1
|
|
8008c5c: e7f0 b.n 8008c40 <_vfiprintf_r+0x1b8>
|
|
8008c5e: ab03 add r3, sp, #12
|
|
8008c60: 9300 str r3, [sp, #0]
|
|
8008c62: 462a mov r2, r5
|
|
8008c64: 4b12 ldr r3, [pc, #72] @ (8008cb0 <_vfiprintf_r+0x228>)
|
|
8008c66: a904 add r1, sp, #16
|
|
8008c68: 4630 mov r0, r6
|
|
8008c6a: f7fd fd47 bl 80066fc <_printf_float>
|
|
8008c6e: 4607 mov r7, r0
|
|
8008c70: 1c78 adds r0, r7, #1
|
|
8008c72: d1d6 bne.n 8008c22 <_vfiprintf_r+0x19a>
|
|
8008c74: 6e6b ldr r3, [r5, #100] @ 0x64
|
|
8008c76: 07d9 lsls r1, r3, #31
|
|
8008c78: d405 bmi.n 8008c86 <_vfiprintf_r+0x1fe>
|
|
8008c7a: 89ab ldrh r3, [r5, #12]
|
|
8008c7c: 059a lsls r2, r3, #22
|
|
8008c7e: d402 bmi.n 8008c86 <_vfiprintf_r+0x1fe>
|
|
8008c80: 6da8 ldr r0, [r5, #88] @ 0x58
|
|
8008c82: f7fe faa9 bl 80071d8 <__retarget_lock_release_recursive>
|
|
8008c86: 89ab ldrh r3, [r5, #12]
|
|
8008c88: 065b lsls r3, r3, #25
|
|
8008c8a: f53f af1f bmi.w 8008acc <_vfiprintf_r+0x44>
|
|
8008c8e: 9809 ldr r0, [sp, #36] @ 0x24
|
|
8008c90: e71e b.n 8008ad0 <_vfiprintf_r+0x48>
|
|
8008c92: ab03 add r3, sp, #12
|
|
8008c94: 9300 str r3, [sp, #0]
|
|
8008c96: 462a mov r2, r5
|
|
8008c98: 4b05 ldr r3, [pc, #20] @ (8008cb0 <_vfiprintf_r+0x228>)
|
|
8008c9a: a904 add r1, sp, #16
|
|
8008c9c: 4630 mov r0, r6
|
|
8008c9e: f7fd ffc5 bl 8006c2c <_printf_i>
|
|
8008ca2: e7e4 b.n 8008c6e <_vfiprintf_r+0x1e6>
|
|
8008ca4: 0800945a .word 0x0800945a
|
|
8008ca8: 08009464 .word 0x08009464
|
|
8008cac: 080066fd .word 0x080066fd
|
|
8008cb0: 08008a63 .word 0x08008a63
|
|
8008cb4: 08009460 .word 0x08009460
|
|
|
|
08008cb8 <__sflush_r>:
|
|
8008cb8: f9b1 200c ldrsh.w r2, [r1, #12]
|
|
8008cbc: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
8008cc0: 0716 lsls r6, r2, #28
|
|
8008cc2: 4605 mov r5, r0
|
|
8008cc4: 460c mov r4, r1
|
|
8008cc6: d454 bmi.n 8008d72 <__sflush_r+0xba>
|
|
8008cc8: 684b ldr r3, [r1, #4]
|
|
8008cca: 2b00 cmp r3, #0
|
|
8008ccc: dc02 bgt.n 8008cd4 <__sflush_r+0x1c>
|
|
8008cce: 6c0b ldr r3, [r1, #64] @ 0x40
|
|
8008cd0: 2b00 cmp r3, #0
|
|
8008cd2: dd48 ble.n 8008d66 <__sflush_r+0xae>
|
|
8008cd4: 6ae6 ldr r6, [r4, #44] @ 0x2c
|
|
8008cd6: 2e00 cmp r6, #0
|
|
8008cd8: d045 beq.n 8008d66 <__sflush_r+0xae>
|
|
8008cda: 2300 movs r3, #0
|
|
8008cdc: f412 5280 ands.w r2, r2, #4096 @ 0x1000
|
|
8008ce0: 682f ldr r7, [r5, #0]
|
|
8008ce2: 6a21 ldr r1, [r4, #32]
|
|
8008ce4: 602b str r3, [r5, #0]
|
|
8008ce6: d030 beq.n 8008d4a <__sflush_r+0x92>
|
|
8008ce8: 6d62 ldr r2, [r4, #84] @ 0x54
|
|
8008cea: 89a3 ldrh r3, [r4, #12]
|
|
8008cec: 0759 lsls r1, r3, #29
|
|
8008cee: d505 bpl.n 8008cfc <__sflush_r+0x44>
|
|
8008cf0: 6863 ldr r3, [r4, #4]
|
|
8008cf2: 1ad2 subs r2, r2, r3
|
|
8008cf4: 6b63 ldr r3, [r4, #52] @ 0x34
|
|
8008cf6: b10b cbz r3, 8008cfc <__sflush_r+0x44>
|
|
8008cf8: 6c23 ldr r3, [r4, #64] @ 0x40
|
|
8008cfa: 1ad2 subs r2, r2, r3
|
|
8008cfc: 2300 movs r3, #0
|
|
8008cfe: 6ae6 ldr r6, [r4, #44] @ 0x2c
|
|
8008d00: 6a21 ldr r1, [r4, #32]
|
|
8008d02: 4628 mov r0, r5
|
|
8008d04: 47b0 blx r6
|
|
8008d06: 1c43 adds r3, r0, #1
|
|
8008d08: 89a3 ldrh r3, [r4, #12]
|
|
8008d0a: d106 bne.n 8008d1a <__sflush_r+0x62>
|
|
8008d0c: 6829 ldr r1, [r5, #0]
|
|
8008d0e: 291d cmp r1, #29
|
|
8008d10: d82b bhi.n 8008d6a <__sflush_r+0xb2>
|
|
8008d12: 4a2a ldr r2, [pc, #168] @ (8008dbc <__sflush_r+0x104>)
|
|
8008d14: 40ca lsrs r2, r1
|
|
8008d16: 07d6 lsls r6, r2, #31
|
|
8008d18: d527 bpl.n 8008d6a <__sflush_r+0xb2>
|
|
8008d1a: 2200 movs r2, #0
|
|
8008d1c: 6062 str r2, [r4, #4]
|
|
8008d1e: 04d9 lsls r1, r3, #19
|
|
8008d20: 6922 ldr r2, [r4, #16]
|
|
8008d22: 6022 str r2, [r4, #0]
|
|
8008d24: d504 bpl.n 8008d30 <__sflush_r+0x78>
|
|
8008d26: 1c42 adds r2, r0, #1
|
|
8008d28: d101 bne.n 8008d2e <__sflush_r+0x76>
|
|
8008d2a: 682b ldr r3, [r5, #0]
|
|
8008d2c: b903 cbnz r3, 8008d30 <__sflush_r+0x78>
|
|
8008d2e: 6560 str r0, [r4, #84] @ 0x54
|
|
8008d30: 6b61 ldr r1, [r4, #52] @ 0x34
|
|
8008d32: 602f str r7, [r5, #0]
|
|
8008d34: b1b9 cbz r1, 8008d66 <__sflush_r+0xae>
|
|
8008d36: f104 0344 add.w r3, r4, #68 @ 0x44
|
|
8008d3a: 4299 cmp r1, r3
|
|
8008d3c: d002 beq.n 8008d44 <__sflush_r+0x8c>
|
|
8008d3e: 4628 mov r0, r5
|
|
8008d40: f7ff f8a6 bl 8007e90 <_free_r>
|
|
8008d44: 2300 movs r3, #0
|
|
8008d46: 6363 str r3, [r4, #52] @ 0x34
|
|
8008d48: e00d b.n 8008d66 <__sflush_r+0xae>
|
|
8008d4a: 2301 movs r3, #1
|
|
8008d4c: 4628 mov r0, r5
|
|
8008d4e: 47b0 blx r6
|
|
8008d50: 4602 mov r2, r0
|
|
8008d52: 1c50 adds r0, r2, #1
|
|
8008d54: d1c9 bne.n 8008cea <__sflush_r+0x32>
|
|
8008d56: 682b ldr r3, [r5, #0]
|
|
8008d58: 2b00 cmp r3, #0
|
|
8008d5a: d0c6 beq.n 8008cea <__sflush_r+0x32>
|
|
8008d5c: 2b1d cmp r3, #29
|
|
8008d5e: d001 beq.n 8008d64 <__sflush_r+0xac>
|
|
8008d60: 2b16 cmp r3, #22
|
|
8008d62: d11e bne.n 8008da2 <__sflush_r+0xea>
|
|
8008d64: 602f str r7, [r5, #0]
|
|
8008d66: 2000 movs r0, #0
|
|
8008d68: e022 b.n 8008db0 <__sflush_r+0xf8>
|
|
8008d6a: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
8008d6e: b21b sxth r3, r3
|
|
8008d70: e01b b.n 8008daa <__sflush_r+0xf2>
|
|
8008d72: 690f ldr r7, [r1, #16]
|
|
8008d74: 2f00 cmp r7, #0
|
|
8008d76: d0f6 beq.n 8008d66 <__sflush_r+0xae>
|
|
8008d78: 0793 lsls r3, r2, #30
|
|
8008d7a: 680e ldr r6, [r1, #0]
|
|
8008d7c: bf08 it eq
|
|
8008d7e: 694b ldreq r3, [r1, #20]
|
|
8008d80: 600f str r7, [r1, #0]
|
|
8008d82: bf18 it ne
|
|
8008d84: 2300 movne r3, #0
|
|
8008d86: eba6 0807 sub.w r8, r6, r7
|
|
8008d8a: 608b str r3, [r1, #8]
|
|
8008d8c: f1b8 0f00 cmp.w r8, #0
|
|
8008d90: dde9 ble.n 8008d66 <__sflush_r+0xae>
|
|
8008d92: 6a21 ldr r1, [r4, #32]
|
|
8008d94: 6aa6 ldr r6, [r4, #40] @ 0x28
|
|
8008d96: 4643 mov r3, r8
|
|
8008d98: 463a mov r2, r7
|
|
8008d9a: 4628 mov r0, r5
|
|
8008d9c: 47b0 blx r6
|
|
8008d9e: 2800 cmp r0, #0
|
|
8008da0: dc08 bgt.n 8008db4 <__sflush_r+0xfc>
|
|
8008da2: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
8008da6: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
8008daa: 81a3 strh r3, [r4, #12]
|
|
8008dac: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8008db0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
|
8008db4: 4407 add r7, r0
|
|
8008db6: eba8 0800 sub.w r8, r8, r0
|
|
8008dba: e7e7 b.n 8008d8c <__sflush_r+0xd4>
|
|
8008dbc: 20400001 .word 0x20400001
|
|
|
|
08008dc0 <_fflush_r>:
|
|
8008dc0: b538 push {r3, r4, r5, lr}
|
|
8008dc2: 690b ldr r3, [r1, #16]
|
|
8008dc4: 4605 mov r5, r0
|
|
8008dc6: 460c mov r4, r1
|
|
8008dc8: b913 cbnz r3, 8008dd0 <_fflush_r+0x10>
|
|
8008dca: 2500 movs r5, #0
|
|
8008dcc: 4628 mov r0, r5
|
|
8008dce: bd38 pop {r3, r4, r5, pc}
|
|
8008dd0: b118 cbz r0, 8008dda <_fflush_r+0x1a>
|
|
8008dd2: 6a03 ldr r3, [r0, #32]
|
|
8008dd4: b90b cbnz r3, 8008dda <_fflush_r+0x1a>
|
|
8008dd6: f7fe f8d3 bl 8006f80 <__sinit>
|
|
8008dda: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
8008dde: 2b00 cmp r3, #0
|
|
8008de0: d0f3 beq.n 8008dca <_fflush_r+0xa>
|
|
8008de2: 6e62 ldr r2, [r4, #100] @ 0x64
|
|
8008de4: 07d0 lsls r0, r2, #31
|
|
8008de6: d404 bmi.n 8008df2 <_fflush_r+0x32>
|
|
8008de8: 0599 lsls r1, r3, #22
|
|
8008dea: d402 bmi.n 8008df2 <_fflush_r+0x32>
|
|
8008dec: 6da0 ldr r0, [r4, #88] @ 0x58
|
|
8008dee: f7fe f9f2 bl 80071d6 <__retarget_lock_acquire_recursive>
|
|
8008df2: 4628 mov r0, r5
|
|
8008df4: 4621 mov r1, r4
|
|
8008df6: f7ff ff5f bl 8008cb8 <__sflush_r>
|
|
8008dfa: 6e63 ldr r3, [r4, #100] @ 0x64
|
|
8008dfc: 07da lsls r2, r3, #31
|
|
8008dfe: 4605 mov r5, r0
|
|
8008e00: d4e4 bmi.n 8008dcc <_fflush_r+0xc>
|
|
8008e02: 89a3 ldrh r3, [r4, #12]
|
|
8008e04: 059b lsls r3, r3, #22
|
|
8008e06: d4e1 bmi.n 8008dcc <_fflush_r+0xc>
|
|
8008e08: 6da0 ldr r0, [r4, #88] @ 0x58
|
|
8008e0a: f7fe f9e5 bl 80071d8 <__retarget_lock_release_recursive>
|
|
8008e0e: e7dd b.n 8008dcc <_fflush_r+0xc>
|
|
|
|
08008e10 <__swbuf_r>:
|
|
8008e10: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8008e12: 460e mov r6, r1
|
|
8008e14: 4614 mov r4, r2
|
|
8008e16: 4605 mov r5, r0
|
|
8008e18: b118 cbz r0, 8008e22 <__swbuf_r+0x12>
|
|
8008e1a: 6a03 ldr r3, [r0, #32]
|
|
8008e1c: b90b cbnz r3, 8008e22 <__swbuf_r+0x12>
|
|
8008e1e: f7fe f8af bl 8006f80 <__sinit>
|
|
8008e22: 69a3 ldr r3, [r4, #24]
|
|
8008e24: 60a3 str r3, [r4, #8]
|
|
8008e26: 89a3 ldrh r3, [r4, #12]
|
|
8008e28: 071a lsls r2, r3, #28
|
|
8008e2a: d501 bpl.n 8008e30 <__swbuf_r+0x20>
|
|
8008e2c: 6923 ldr r3, [r4, #16]
|
|
8008e2e: b943 cbnz r3, 8008e42 <__swbuf_r+0x32>
|
|
8008e30: 4621 mov r1, r4
|
|
8008e32: 4628 mov r0, r5
|
|
8008e34: f000 f82a bl 8008e8c <__swsetup_r>
|
|
8008e38: b118 cbz r0, 8008e42 <__swbuf_r+0x32>
|
|
8008e3a: f04f 37ff mov.w r7, #4294967295 @ 0xffffffff
|
|
8008e3e: 4638 mov r0, r7
|
|
8008e40: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
8008e42: 6823 ldr r3, [r4, #0]
|
|
8008e44: 6922 ldr r2, [r4, #16]
|
|
8008e46: 1a98 subs r0, r3, r2
|
|
8008e48: 6963 ldr r3, [r4, #20]
|
|
8008e4a: b2f6 uxtb r6, r6
|
|
8008e4c: 4283 cmp r3, r0
|
|
8008e4e: 4637 mov r7, r6
|
|
8008e50: dc05 bgt.n 8008e5e <__swbuf_r+0x4e>
|
|
8008e52: 4621 mov r1, r4
|
|
8008e54: 4628 mov r0, r5
|
|
8008e56: f7ff ffb3 bl 8008dc0 <_fflush_r>
|
|
8008e5a: 2800 cmp r0, #0
|
|
8008e5c: d1ed bne.n 8008e3a <__swbuf_r+0x2a>
|
|
8008e5e: 68a3 ldr r3, [r4, #8]
|
|
8008e60: 3b01 subs r3, #1
|
|
8008e62: 60a3 str r3, [r4, #8]
|
|
8008e64: 6823 ldr r3, [r4, #0]
|
|
8008e66: 1c5a adds r2, r3, #1
|
|
8008e68: 6022 str r2, [r4, #0]
|
|
8008e6a: 701e strb r6, [r3, #0]
|
|
8008e6c: 6962 ldr r2, [r4, #20]
|
|
8008e6e: 1c43 adds r3, r0, #1
|
|
8008e70: 429a cmp r2, r3
|
|
8008e72: d004 beq.n 8008e7e <__swbuf_r+0x6e>
|
|
8008e74: 89a3 ldrh r3, [r4, #12]
|
|
8008e76: 07db lsls r3, r3, #31
|
|
8008e78: d5e1 bpl.n 8008e3e <__swbuf_r+0x2e>
|
|
8008e7a: 2e0a cmp r6, #10
|
|
8008e7c: d1df bne.n 8008e3e <__swbuf_r+0x2e>
|
|
8008e7e: 4621 mov r1, r4
|
|
8008e80: 4628 mov r0, r5
|
|
8008e82: f7ff ff9d bl 8008dc0 <_fflush_r>
|
|
8008e86: 2800 cmp r0, #0
|
|
8008e88: d0d9 beq.n 8008e3e <__swbuf_r+0x2e>
|
|
8008e8a: e7d6 b.n 8008e3a <__swbuf_r+0x2a>
|
|
|
|
08008e8c <__swsetup_r>:
|
|
8008e8c: b538 push {r3, r4, r5, lr}
|
|
8008e8e: 4b29 ldr r3, [pc, #164] @ (8008f34 <__swsetup_r+0xa8>)
|
|
8008e90: 4605 mov r5, r0
|
|
8008e92: 6818 ldr r0, [r3, #0]
|
|
8008e94: 460c mov r4, r1
|
|
8008e96: b118 cbz r0, 8008ea0 <__swsetup_r+0x14>
|
|
8008e98: 6a03 ldr r3, [r0, #32]
|
|
8008e9a: b90b cbnz r3, 8008ea0 <__swsetup_r+0x14>
|
|
8008e9c: f7fe f870 bl 8006f80 <__sinit>
|
|
8008ea0: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
8008ea4: 0719 lsls r1, r3, #28
|
|
8008ea6: d422 bmi.n 8008eee <__swsetup_r+0x62>
|
|
8008ea8: 06da lsls r2, r3, #27
|
|
8008eaa: d407 bmi.n 8008ebc <__swsetup_r+0x30>
|
|
8008eac: 2209 movs r2, #9
|
|
8008eae: 602a str r2, [r5, #0]
|
|
8008eb0: f043 0340 orr.w r3, r3, #64 @ 0x40
|
|
8008eb4: 81a3 strh r3, [r4, #12]
|
|
8008eb6: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8008eba: e033 b.n 8008f24 <__swsetup_r+0x98>
|
|
8008ebc: 0758 lsls r0, r3, #29
|
|
8008ebe: d512 bpl.n 8008ee6 <__swsetup_r+0x5a>
|
|
8008ec0: 6b61 ldr r1, [r4, #52] @ 0x34
|
|
8008ec2: b141 cbz r1, 8008ed6 <__swsetup_r+0x4a>
|
|
8008ec4: f104 0344 add.w r3, r4, #68 @ 0x44
|
|
8008ec8: 4299 cmp r1, r3
|
|
8008eca: d002 beq.n 8008ed2 <__swsetup_r+0x46>
|
|
8008ecc: 4628 mov r0, r5
|
|
8008ece: f7fe ffdf bl 8007e90 <_free_r>
|
|
8008ed2: 2300 movs r3, #0
|
|
8008ed4: 6363 str r3, [r4, #52] @ 0x34
|
|
8008ed6: 89a3 ldrh r3, [r4, #12]
|
|
8008ed8: f023 0324 bic.w r3, r3, #36 @ 0x24
|
|
8008edc: 81a3 strh r3, [r4, #12]
|
|
8008ede: 2300 movs r3, #0
|
|
8008ee0: 6063 str r3, [r4, #4]
|
|
8008ee2: 6923 ldr r3, [r4, #16]
|
|
8008ee4: 6023 str r3, [r4, #0]
|
|
8008ee6: 89a3 ldrh r3, [r4, #12]
|
|
8008ee8: f043 0308 orr.w r3, r3, #8
|
|
8008eec: 81a3 strh r3, [r4, #12]
|
|
8008eee: 6923 ldr r3, [r4, #16]
|
|
8008ef0: b94b cbnz r3, 8008f06 <__swsetup_r+0x7a>
|
|
8008ef2: 89a3 ldrh r3, [r4, #12]
|
|
8008ef4: f403 7320 and.w r3, r3, #640 @ 0x280
|
|
8008ef8: f5b3 7f00 cmp.w r3, #512 @ 0x200
|
|
8008efc: d003 beq.n 8008f06 <__swsetup_r+0x7a>
|
|
8008efe: 4621 mov r1, r4
|
|
8008f00: 4628 mov r0, r5
|
|
8008f02: f000 f909 bl 8009118 <__smakebuf_r>
|
|
8008f06: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
8008f0a: f013 0201 ands.w r2, r3, #1
|
|
8008f0e: d00a beq.n 8008f26 <__swsetup_r+0x9a>
|
|
8008f10: 2200 movs r2, #0
|
|
8008f12: 60a2 str r2, [r4, #8]
|
|
8008f14: 6962 ldr r2, [r4, #20]
|
|
8008f16: 4252 negs r2, r2
|
|
8008f18: 61a2 str r2, [r4, #24]
|
|
8008f1a: 6922 ldr r2, [r4, #16]
|
|
8008f1c: b942 cbnz r2, 8008f30 <__swsetup_r+0xa4>
|
|
8008f1e: f013 0080 ands.w r0, r3, #128 @ 0x80
|
|
8008f22: d1c5 bne.n 8008eb0 <__swsetup_r+0x24>
|
|
8008f24: bd38 pop {r3, r4, r5, pc}
|
|
8008f26: 0799 lsls r1, r3, #30
|
|
8008f28: bf58 it pl
|
|
8008f2a: 6962 ldrpl r2, [r4, #20]
|
|
8008f2c: 60a2 str r2, [r4, #8]
|
|
8008f2e: e7f4 b.n 8008f1a <__swsetup_r+0x8e>
|
|
8008f30: 2000 movs r0, #0
|
|
8008f32: e7f7 b.n 8008f24 <__swsetup_r+0x98>
|
|
8008f34: 2000002c .word 0x2000002c
|
|
|
|
08008f38 <memmove>:
|
|
8008f38: 4288 cmp r0, r1
|
|
8008f3a: b510 push {r4, lr}
|
|
8008f3c: eb01 0402 add.w r4, r1, r2
|
|
8008f40: d902 bls.n 8008f48 <memmove+0x10>
|
|
8008f42: 4284 cmp r4, r0
|
|
8008f44: 4623 mov r3, r4
|
|
8008f46: d807 bhi.n 8008f58 <memmove+0x20>
|
|
8008f48: 1e43 subs r3, r0, #1
|
|
8008f4a: 42a1 cmp r1, r4
|
|
8008f4c: d008 beq.n 8008f60 <memmove+0x28>
|
|
8008f4e: f811 2b01 ldrb.w r2, [r1], #1
|
|
8008f52: f803 2f01 strb.w r2, [r3, #1]!
|
|
8008f56: e7f8 b.n 8008f4a <memmove+0x12>
|
|
8008f58: 4402 add r2, r0
|
|
8008f5a: 4601 mov r1, r0
|
|
8008f5c: 428a cmp r2, r1
|
|
8008f5e: d100 bne.n 8008f62 <memmove+0x2a>
|
|
8008f60: bd10 pop {r4, pc}
|
|
8008f62: f813 4d01 ldrb.w r4, [r3, #-1]!
|
|
8008f66: f802 4d01 strb.w r4, [r2, #-1]!
|
|
8008f6a: e7f7 b.n 8008f5c <memmove+0x24>
|
|
|
|
08008f6c <_sbrk_r>:
|
|
8008f6c: b538 push {r3, r4, r5, lr}
|
|
8008f6e: 4d06 ldr r5, [pc, #24] @ (8008f88 <_sbrk_r+0x1c>)
|
|
8008f70: 2300 movs r3, #0
|
|
8008f72: 4604 mov r4, r0
|
|
8008f74: 4608 mov r0, r1
|
|
8008f76: 602b str r3, [r5, #0]
|
|
8008f78: f7f9 f996 bl 80022a8 <_sbrk>
|
|
8008f7c: 1c43 adds r3, r0, #1
|
|
8008f7e: d102 bne.n 8008f86 <_sbrk_r+0x1a>
|
|
8008f80: 682b ldr r3, [r5, #0]
|
|
8008f82: b103 cbz r3, 8008f86 <_sbrk_r+0x1a>
|
|
8008f84: 6023 str r3, [r4, #0]
|
|
8008f86: bd38 pop {r3, r4, r5, pc}
|
|
8008f88: 20000468 .word 0x20000468
|
|
|
|
08008f8c <memcpy>:
|
|
8008f8c: 440a add r2, r1
|
|
8008f8e: 4291 cmp r1, r2
|
|
8008f90: f100 33ff add.w r3, r0, #4294967295 @ 0xffffffff
|
|
8008f94: d100 bne.n 8008f98 <memcpy+0xc>
|
|
8008f96: 4770 bx lr
|
|
8008f98: b510 push {r4, lr}
|
|
8008f9a: f811 4b01 ldrb.w r4, [r1], #1
|
|
8008f9e: f803 4f01 strb.w r4, [r3, #1]!
|
|
8008fa2: 4291 cmp r1, r2
|
|
8008fa4: d1f9 bne.n 8008f9a <memcpy+0xe>
|
|
8008fa6: bd10 pop {r4, pc}
|
|
|
|
08008fa8 <__assert_func>:
|
|
8008fa8: b51f push {r0, r1, r2, r3, r4, lr}
|
|
8008faa: 4614 mov r4, r2
|
|
8008fac: 461a mov r2, r3
|
|
8008fae: 4b09 ldr r3, [pc, #36] @ (8008fd4 <__assert_func+0x2c>)
|
|
8008fb0: 681b ldr r3, [r3, #0]
|
|
8008fb2: 4605 mov r5, r0
|
|
8008fb4: 68d8 ldr r0, [r3, #12]
|
|
8008fb6: b14c cbz r4, 8008fcc <__assert_func+0x24>
|
|
8008fb8: 4b07 ldr r3, [pc, #28] @ (8008fd8 <__assert_func+0x30>)
|
|
8008fba: 9100 str r1, [sp, #0]
|
|
8008fbc: e9cd 3401 strd r3, r4, [sp, #4]
|
|
8008fc0: 4906 ldr r1, [pc, #24] @ (8008fdc <__assert_func+0x34>)
|
|
8008fc2: 462b mov r3, r5
|
|
8008fc4: f000 f870 bl 80090a8 <fiprintf>
|
|
8008fc8: f000 f904 bl 80091d4 <abort>
|
|
8008fcc: 4b04 ldr r3, [pc, #16] @ (8008fe0 <__assert_func+0x38>)
|
|
8008fce: 461c mov r4, r3
|
|
8008fd0: e7f3 b.n 8008fba <__assert_func+0x12>
|
|
8008fd2: bf00 nop
|
|
8008fd4: 2000002c .word 0x2000002c
|
|
8008fd8: 08009475 .word 0x08009475
|
|
8008fdc: 08009482 .word 0x08009482
|
|
8008fe0: 080094b0 .word 0x080094b0
|
|
|
|
08008fe4 <_calloc_r>:
|
|
8008fe4: b570 push {r4, r5, r6, lr}
|
|
8008fe6: fba1 5402 umull r5, r4, r1, r2
|
|
8008fea: b934 cbnz r4, 8008ffa <_calloc_r+0x16>
|
|
8008fec: 4629 mov r1, r5
|
|
8008fee: f7fe ffc3 bl 8007f78 <_malloc_r>
|
|
8008ff2: 4606 mov r6, r0
|
|
8008ff4: b928 cbnz r0, 8009002 <_calloc_r+0x1e>
|
|
8008ff6: 4630 mov r0, r6
|
|
8008ff8: bd70 pop {r4, r5, r6, pc}
|
|
8008ffa: 220c movs r2, #12
|
|
8008ffc: 6002 str r2, [r0, #0]
|
|
8008ffe: 2600 movs r6, #0
|
|
8009000: e7f9 b.n 8008ff6 <_calloc_r+0x12>
|
|
8009002: 462a mov r2, r5
|
|
8009004: 4621 mov r1, r4
|
|
8009006: f7fe f868 bl 80070da <memset>
|
|
800900a: e7f4 b.n 8008ff6 <_calloc_r+0x12>
|
|
|
|
0800900c <__ascii_mbtowc>:
|
|
800900c: b082 sub sp, #8
|
|
800900e: b901 cbnz r1, 8009012 <__ascii_mbtowc+0x6>
|
|
8009010: a901 add r1, sp, #4
|
|
8009012: b142 cbz r2, 8009026 <__ascii_mbtowc+0x1a>
|
|
8009014: b14b cbz r3, 800902a <__ascii_mbtowc+0x1e>
|
|
8009016: 7813 ldrb r3, [r2, #0]
|
|
8009018: 600b str r3, [r1, #0]
|
|
800901a: 7812 ldrb r2, [r2, #0]
|
|
800901c: 1e10 subs r0, r2, #0
|
|
800901e: bf18 it ne
|
|
8009020: 2001 movne r0, #1
|
|
8009022: b002 add sp, #8
|
|
8009024: 4770 bx lr
|
|
8009026: 4610 mov r0, r2
|
|
8009028: e7fb b.n 8009022 <__ascii_mbtowc+0x16>
|
|
800902a: f06f 0001 mvn.w r0, #1
|
|
800902e: e7f8 b.n 8009022 <__ascii_mbtowc+0x16>
|
|
|
|
08009030 <_realloc_r>:
|
|
8009030: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr}
|
|
8009034: 4607 mov r7, r0
|
|
8009036: 4614 mov r4, r2
|
|
8009038: 460d mov r5, r1
|
|
800903a: b921 cbnz r1, 8009046 <_realloc_r+0x16>
|
|
800903c: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr}
|
|
8009040: 4611 mov r1, r2
|
|
8009042: f7fe bf99 b.w 8007f78 <_malloc_r>
|
|
8009046: b92a cbnz r2, 8009054 <_realloc_r+0x24>
|
|
8009048: f7fe ff22 bl 8007e90 <_free_r>
|
|
800904c: 4625 mov r5, r4
|
|
800904e: 4628 mov r0, r5
|
|
8009050: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc}
|
|
8009054: f000 f8c5 bl 80091e2 <_malloc_usable_size_r>
|
|
8009058: 4284 cmp r4, r0
|
|
800905a: 4606 mov r6, r0
|
|
800905c: d802 bhi.n 8009064 <_realloc_r+0x34>
|
|
800905e: ebb4 0f50 cmp.w r4, r0, lsr #1
|
|
8009062: d8f4 bhi.n 800904e <_realloc_r+0x1e>
|
|
8009064: 4621 mov r1, r4
|
|
8009066: 4638 mov r0, r7
|
|
8009068: f7fe ff86 bl 8007f78 <_malloc_r>
|
|
800906c: 4680 mov r8, r0
|
|
800906e: b908 cbnz r0, 8009074 <_realloc_r+0x44>
|
|
8009070: 4645 mov r5, r8
|
|
8009072: e7ec b.n 800904e <_realloc_r+0x1e>
|
|
8009074: 42b4 cmp r4, r6
|
|
8009076: 4622 mov r2, r4
|
|
8009078: 4629 mov r1, r5
|
|
800907a: bf28 it cs
|
|
800907c: 4632 movcs r2, r6
|
|
800907e: f7ff ff85 bl 8008f8c <memcpy>
|
|
8009082: 4629 mov r1, r5
|
|
8009084: 4638 mov r0, r7
|
|
8009086: f7fe ff03 bl 8007e90 <_free_r>
|
|
800908a: e7f1 b.n 8009070 <_realloc_r+0x40>
|
|
|
|
0800908c <__ascii_wctomb>:
|
|
800908c: 4603 mov r3, r0
|
|
800908e: 4608 mov r0, r1
|
|
8009090: b141 cbz r1, 80090a4 <__ascii_wctomb+0x18>
|
|
8009092: 2aff cmp r2, #255 @ 0xff
|
|
8009094: d904 bls.n 80090a0 <__ascii_wctomb+0x14>
|
|
8009096: 228a movs r2, #138 @ 0x8a
|
|
8009098: 601a str r2, [r3, #0]
|
|
800909a: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
800909e: 4770 bx lr
|
|
80090a0: 700a strb r2, [r1, #0]
|
|
80090a2: 2001 movs r0, #1
|
|
80090a4: 4770 bx lr
|
|
...
|
|
|
|
080090a8 <fiprintf>:
|
|
80090a8: b40e push {r1, r2, r3}
|
|
80090aa: b503 push {r0, r1, lr}
|
|
80090ac: 4601 mov r1, r0
|
|
80090ae: ab03 add r3, sp, #12
|
|
80090b0: 4805 ldr r0, [pc, #20] @ (80090c8 <fiprintf+0x20>)
|
|
80090b2: f853 2b04 ldr.w r2, [r3], #4
|
|
80090b6: 6800 ldr r0, [r0, #0]
|
|
80090b8: 9301 str r3, [sp, #4]
|
|
80090ba: f7ff fce5 bl 8008a88 <_vfiprintf_r>
|
|
80090be: b002 add sp, #8
|
|
80090c0: f85d eb04 ldr.w lr, [sp], #4
|
|
80090c4: b003 add sp, #12
|
|
80090c6: 4770 bx lr
|
|
80090c8: 2000002c .word 0x2000002c
|
|
|
|
080090cc <__swhatbuf_r>:
|
|
80090cc: b570 push {r4, r5, r6, lr}
|
|
80090ce: 460c mov r4, r1
|
|
80090d0: f9b1 100e ldrsh.w r1, [r1, #14]
|
|
80090d4: 2900 cmp r1, #0
|
|
80090d6: b096 sub sp, #88 @ 0x58
|
|
80090d8: 4615 mov r5, r2
|
|
80090da: 461e mov r6, r3
|
|
80090dc: da0d bge.n 80090fa <__swhatbuf_r+0x2e>
|
|
80090de: 89a3 ldrh r3, [r4, #12]
|
|
80090e0: f013 0f80 tst.w r3, #128 @ 0x80
|
|
80090e4: f04f 0100 mov.w r1, #0
|
|
80090e8: bf14 ite ne
|
|
80090ea: 2340 movne r3, #64 @ 0x40
|
|
80090ec: f44f 6380 moveq.w r3, #1024 @ 0x400
|
|
80090f0: 2000 movs r0, #0
|
|
80090f2: 6031 str r1, [r6, #0]
|
|
80090f4: 602b str r3, [r5, #0]
|
|
80090f6: b016 add sp, #88 @ 0x58
|
|
80090f8: bd70 pop {r4, r5, r6, pc}
|
|
80090fa: 466a mov r2, sp
|
|
80090fc: f000 f848 bl 8009190 <_fstat_r>
|
|
8009100: 2800 cmp r0, #0
|
|
8009102: dbec blt.n 80090de <__swhatbuf_r+0x12>
|
|
8009104: 9901 ldr r1, [sp, #4]
|
|
8009106: f401 4170 and.w r1, r1, #61440 @ 0xf000
|
|
800910a: f5a1 5300 sub.w r3, r1, #8192 @ 0x2000
|
|
800910e: 4259 negs r1, r3
|
|
8009110: 4159 adcs r1, r3
|
|
8009112: f44f 6380 mov.w r3, #1024 @ 0x400
|
|
8009116: e7eb b.n 80090f0 <__swhatbuf_r+0x24>
|
|
|
|
08009118 <__smakebuf_r>:
|
|
8009118: 898b ldrh r3, [r1, #12]
|
|
800911a: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
|
|
800911c: 079d lsls r5, r3, #30
|
|
800911e: 4606 mov r6, r0
|
|
8009120: 460c mov r4, r1
|
|
8009122: d507 bpl.n 8009134 <__smakebuf_r+0x1c>
|
|
8009124: f104 0347 add.w r3, r4, #71 @ 0x47
|
|
8009128: 6023 str r3, [r4, #0]
|
|
800912a: 6123 str r3, [r4, #16]
|
|
800912c: 2301 movs r3, #1
|
|
800912e: 6163 str r3, [r4, #20]
|
|
8009130: b003 add sp, #12
|
|
8009132: bdf0 pop {r4, r5, r6, r7, pc}
|
|
8009134: ab01 add r3, sp, #4
|
|
8009136: 466a mov r2, sp
|
|
8009138: f7ff ffc8 bl 80090cc <__swhatbuf_r>
|
|
800913c: 9f00 ldr r7, [sp, #0]
|
|
800913e: 4605 mov r5, r0
|
|
8009140: 4639 mov r1, r7
|
|
8009142: 4630 mov r0, r6
|
|
8009144: f7fe ff18 bl 8007f78 <_malloc_r>
|
|
8009148: b948 cbnz r0, 800915e <__smakebuf_r+0x46>
|
|
800914a: f9b4 300c ldrsh.w r3, [r4, #12]
|
|
800914e: 059a lsls r2, r3, #22
|
|
8009150: d4ee bmi.n 8009130 <__smakebuf_r+0x18>
|
|
8009152: f023 0303 bic.w r3, r3, #3
|
|
8009156: f043 0302 orr.w r3, r3, #2
|
|
800915a: 81a3 strh r3, [r4, #12]
|
|
800915c: e7e2 b.n 8009124 <__smakebuf_r+0xc>
|
|
800915e: 89a3 ldrh r3, [r4, #12]
|
|
8009160: 6020 str r0, [r4, #0]
|
|
8009162: f043 0380 orr.w r3, r3, #128 @ 0x80
|
|
8009166: 81a3 strh r3, [r4, #12]
|
|
8009168: 9b01 ldr r3, [sp, #4]
|
|
800916a: e9c4 0704 strd r0, r7, [r4, #16]
|
|
800916e: b15b cbz r3, 8009188 <__smakebuf_r+0x70>
|
|
8009170: f9b4 100e ldrsh.w r1, [r4, #14]
|
|
8009174: 4630 mov r0, r6
|
|
8009176: f000 f81d bl 80091b4 <_isatty_r>
|
|
800917a: b128 cbz r0, 8009188 <__smakebuf_r+0x70>
|
|
800917c: 89a3 ldrh r3, [r4, #12]
|
|
800917e: f023 0303 bic.w r3, r3, #3
|
|
8009182: f043 0301 orr.w r3, r3, #1
|
|
8009186: 81a3 strh r3, [r4, #12]
|
|
8009188: 89a3 ldrh r3, [r4, #12]
|
|
800918a: 431d orrs r5, r3
|
|
800918c: 81a5 strh r5, [r4, #12]
|
|
800918e: e7cf b.n 8009130 <__smakebuf_r+0x18>
|
|
|
|
08009190 <_fstat_r>:
|
|
8009190: b538 push {r3, r4, r5, lr}
|
|
8009192: 4d07 ldr r5, [pc, #28] @ (80091b0 <_fstat_r+0x20>)
|
|
8009194: 2300 movs r3, #0
|
|
8009196: 4604 mov r4, r0
|
|
8009198: 4608 mov r0, r1
|
|
800919a: 4611 mov r1, r2
|
|
800919c: 602b str r3, [r5, #0]
|
|
800919e: f7f9 f85b bl 8002258 <_fstat>
|
|
80091a2: 1c43 adds r3, r0, #1
|
|
80091a4: d102 bne.n 80091ac <_fstat_r+0x1c>
|
|
80091a6: 682b ldr r3, [r5, #0]
|
|
80091a8: b103 cbz r3, 80091ac <_fstat_r+0x1c>
|
|
80091aa: 6023 str r3, [r4, #0]
|
|
80091ac: bd38 pop {r3, r4, r5, pc}
|
|
80091ae: bf00 nop
|
|
80091b0: 20000468 .word 0x20000468
|
|
|
|
080091b4 <_isatty_r>:
|
|
80091b4: b538 push {r3, r4, r5, lr}
|
|
80091b6: 4d06 ldr r5, [pc, #24] @ (80091d0 <_isatty_r+0x1c>)
|
|
80091b8: 2300 movs r3, #0
|
|
80091ba: 4604 mov r4, r0
|
|
80091bc: 4608 mov r0, r1
|
|
80091be: 602b str r3, [r5, #0]
|
|
80091c0: f7f9 f85a bl 8002278 <_isatty>
|
|
80091c4: 1c43 adds r3, r0, #1
|
|
80091c6: d102 bne.n 80091ce <_isatty_r+0x1a>
|
|
80091c8: 682b ldr r3, [r5, #0]
|
|
80091ca: b103 cbz r3, 80091ce <_isatty_r+0x1a>
|
|
80091cc: 6023 str r3, [r4, #0]
|
|
80091ce: bd38 pop {r3, r4, r5, pc}
|
|
80091d0: 20000468 .word 0x20000468
|
|
|
|
080091d4 <abort>:
|
|
80091d4: b508 push {r3, lr}
|
|
80091d6: 2006 movs r0, #6
|
|
80091d8: f000 f834 bl 8009244 <raise>
|
|
80091dc: 2001 movs r0, #1
|
|
80091de: f7f8 ffeb bl 80021b8 <_exit>
|
|
|
|
080091e2 <_malloc_usable_size_r>:
|
|
80091e2: f851 3c04 ldr.w r3, [r1, #-4]
|
|
80091e6: 1f18 subs r0, r3, #4
|
|
80091e8: 2b00 cmp r3, #0
|
|
80091ea: bfbc itt lt
|
|
80091ec: 580b ldrlt r3, [r1, r0]
|
|
80091ee: 18c0 addlt r0, r0, r3
|
|
80091f0: 4770 bx lr
|
|
|
|
080091f2 <_raise_r>:
|
|
80091f2: 291f cmp r1, #31
|
|
80091f4: b538 push {r3, r4, r5, lr}
|
|
80091f6: 4605 mov r5, r0
|
|
80091f8: 460c mov r4, r1
|
|
80091fa: d904 bls.n 8009206 <_raise_r+0x14>
|
|
80091fc: 2316 movs r3, #22
|
|
80091fe: 6003 str r3, [r0, #0]
|
|
8009200: f04f 30ff mov.w r0, #4294967295 @ 0xffffffff
|
|
8009204: bd38 pop {r3, r4, r5, pc}
|
|
8009206: 6bc2 ldr r2, [r0, #60] @ 0x3c
|
|
8009208: b112 cbz r2, 8009210 <_raise_r+0x1e>
|
|
800920a: f852 3021 ldr.w r3, [r2, r1, lsl #2]
|
|
800920e: b94b cbnz r3, 8009224 <_raise_r+0x32>
|
|
8009210: 4628 mov r0, r5
|
|
8009212: f000 f831 bl 8009278 <_getpid_r>
|
|
8009216: 4622 mov r2, r4
|
|
8009218: 4601 mov r1, r0
|
|
800921a: 4628 mov r0, r5
|
|
800921c: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr}
|
|
8009220: f000 b818 b.w 8009254 <_kill_r>
|
|
8009224: 2b01 cmp r3, #1
|
|
8009226: d00a beq.n 800923e <_raise_r+0x4c>
|
|
8009228: 1c59 adds r1, r3, #1
|
|
800922a: d103 bne.n 8009234 <_raise_r+0x42>
|
|
800922c: 2316 movs r3, #22
|
|
800922e: 6003 str r3, [r0, #0]
|
|
8009230: 2001 movs r0, #1
|
|
8009232: e7e7 b.n 8009204 <_raise_r+0x12>
|
|
8009234: 2100 movs r1, #0
|
|
8009236: f842 1024 str.w r1, [r2, r4, lsl #2]
|
|
800923a: 4620 mov r0, r4
|
|
800923c: 4798 blx r3
|
|
800923e: 2000 movs r0, #0
|
|
8009240: e7e0 b.n 8009204 <_raise_r+0x12>
|
|
...
|
|
|
|
08009244 <raise>:
|
|
8009244: 4b02 ldr r3, [pc, #8] @ (8009250 <raise+0xc>)
|
|
8009246: 4601 mov r1, r0
|
|
8009248: 6818 ldr r0, [r3, #0]
|
|
800924a: f7ff bfd2 b.w 80091f2 <_raise_r>
|
|
800924e: bf00 nop
|
|
8009250: 2000002c .word 0x2000002c
|
|
|
|
08009254 <_kill_r>:
|
|
8009254: b538 push {r3, r4, r5, lr}
|
|
8009256: 4d07 ldr r5, [pc, #28] @ (8009274 <_kill_r+0x20>)
|
|
8009258: 2300 movs r3, #0
|
|
800925a: 4604 mov r4, r0
|
|
800925c: 4608 mov r0, r1
|
|
800925e: 4611 mov r1, r2
|
|
8009260: 602b str r3, [r5, #0]
|
|
8009262: f7f8 ff99 bl 8002198 <_kill>
|
|
8009266: 1c43 adds r3, r0, #1
|
|
8009268: d102 bne.n 8009270 <_kill_r+0x1c>
|
|
800926a: 682b ldr r3, [r5, #0]
|
|
800926c: b103 cbz r3, 8009270 <_kill_r+0x1c>
|
|
800926e: 6023 str r3, [r4, #0]
|
|
8009270: bd38 pop {r3, r4, r5, pc}
|
|
8009272: bf00 nop
|
|
8009274: 20000468 .word 0x20000468
|
|
|
|
08009278 <_getpid_r>:
|
|
8009278: f7f8 bf86 b.w 8002188 <_getpid>
|
|
|
|
0800927c <_init>:
|
|
800927c: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
800927e: bf00 nop
|
|
8009280: bcf8 pop {r3, r4, r5, r6, r7}
|
|
8009282: bc08 pop {r3}
|
|
8009284: 469e mov lr, r3
|
|
8009286: 4770 bx lr
|
|
|
|
08009288 <_fini>:
|
|
8009288: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
800928a: bf00 nop
|
|
800928c: bcf8 pop {r3, r4, r5, r6, r7}
|
|
800928e: bc08 pop {r3}
|
|
8009290: 469e mov lr, r3
|
|
8009292: 4770 bx lr
|