225 lines
11 KiB
Plaintext
225 lines
11 KiB
Plaintext
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
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| Date : Tue Mar 3 03:57:20 2026
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| Host : odin running 64-bit Arch Linux
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| Command : report_utilization -file riscv_utilization_placed.rpt -pb riscv_utilization_placed.pb
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| Design : riscv
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| Device : xc7a35tcpg236-1
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| Speed File : -1
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| Design State : Fully Placed
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Utilization Design Information
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Table of Contents
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-----------------
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1. Slice Logic
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1.1 Summary of Registers by Type
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2. Slice Logic Distribution
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3. Memory
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4. DSP
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5. IO and GT Specific
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6. Clocking
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7. Specific Feature
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8. Primitives
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9. Black Boxes
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10. Instantiated Netlists
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1. Slice Logic
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--------------
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+----------------------------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+----------------------------+------+-------+------------+-----------+-------+
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| Slice LUTs | 1172 | 0 | 0 | 20800 | 5.63 |
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| LUT as Logic | 1128 | 0 | 0 | 20800 | 5.42 |
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| LUT as Memory | 44 | 0 | 0 | 9600 | 0.46 |
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| LUT as Distributed RAM | 44 | 0 | | | |
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| LUT as Shift Register | 0 | 0 | | | |
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| Slice Registers | 547 | 0 | 0 | 41600 | 1.31 |
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| Register as Flip Flop | 547 | 0 | 0 | 41600 | 1.31 |
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| Register as Latch | 0 | 0 | 0 | 41600 | 0.00 |
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| F7 Muxes | 0 | 0 | 0 | 16300 | 0.00 |
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| F8 Muxes | 0 | 0 | 0 | 8150 | 0.00 |
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| Unique Control Sets | 19 | | 0 | 8150 | 0.23 |
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+----------------------------+------+-------+------------+-----------+-------+
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* Warning! LUT value is adjusted to account for LUT combining.
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** Note: Available Control Sets calculated as Slice * 1, Review the Control Sets Report for more information regarding control sets.
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1.1 Summary of Registers by Type
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--------------------------------
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+-------+--------------+-------------+--------------+
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| Total | Clock Enable | Synchronous | Asynchronous |
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+-------+--------------+-------------+--------------+
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| 0 | _ | - | - |
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| 0 | _ | - | Set |
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| 0 | _ | - | Reset |
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| 0 | _ | Set | - |
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| 0 | _ | Reset | - |
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| 0 | Yes | - | - |
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| 0 | Yes | - | Set |
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| 419 | Yes | - | Reset |
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| 0 | Yes | Set | - |
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| 128 | Yes | Reset | - |
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+-------+--------------+-------------+--------------+
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2. Slice Logic Distribution
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---------------------------
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+--------------------------------------------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+--------------------------------------------+------+-------+------------+-----------+-------+
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| Slice | 357 | 0 | 0 | 8150 | 4.38 |
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| SLICEL | 271 | 0 | | | |
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| SLICEM | 86 | 0 | | | |
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| LUT as Logic | 1128 | 0 | 0 | 20800 | 5.42 |
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| using O5 output only | 0 | | | | |
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| using O6 output only | 859 | | | | |
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| using O5 and O6 | 269 | | | | |
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| LUT as Memory | 44 | 0 | 0 | 9600 | 0.46 |
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| LUT as Distributed RAM | 44 | 0 | | | |
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| using O5 output only | 0 | | | | |
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| using O6 output only | 0 | | | | |
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| using O5 and O6 | 44 | | | | |
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| LUT as Shift Register | 0 | 0 | | | |
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| using O5 output only | 0 | | | | |
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| using O6 output only | 0 | | | | |
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| using O5 and O6 | 0 | | | | |
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| Slice Registers | 547 | 0 | 0 | 41600 | 1.31 |
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| Register driven from within the Slice | 389 | | | | |
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| Register driven from outside the Slice | 158 | | | | |
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| LUT in front of the register is unused | 57 | | | | |
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| LUT in front of the register is used | 101 | | | | |
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+--------------------------------------------+------+-------+------------+-----------+-------+
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3. Memory
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---------
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+-------------------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+-------------------+------+-------+------------+-----------+-------+
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| Block RAM Tile | 1 | 0 | 0 | 50 | 2.00 |
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| RAMB36/FIFO* | 0 | 0 | 0 | 50 | 0.00 |
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| RAMB18 | 2 | 0 | 0 | 100 | 2.00 |
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| RAMB18E1 only | 2 | | | | |
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+-------------------+------+-------+------------+-----------+-------+
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* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
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4. DSP
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------
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+-----------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+-----------+------+-------+------------+-----------+-------+
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| DSPs | 0 | 0 | 0 | 90 | 0.00 |
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+-----------+------+-------+------------+-----------+-------+
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5. IO and GT Specific
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---------------------
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+-----------------------------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+-----------------------------+------+-------+------------+-----------+-------+
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| Bonded IOB | 6 | 6 | 0 | 106 | 5.66 |
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| IOB Master Pads | 3 | | | | |
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| IOB Slave Pads | 3 | | | | |
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| Bonded IPADs | 0 | 0 | 0 | 10 | 0.00 |
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| Bonded OPADs | 0 | 0 | 0 | 4 | 0.00 |
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| PHY_CONTROL | 0 | 0 | 0 | 5 | 0.00 |
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| PHASER_REF | 0 | 0 | 0 | 5 | 0.00 |
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| OUT_FIFO | 0 | 0 | 0 | 20 | 0.00 |
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| IN_FIFO | 0 | 0 | 0 | 20 | 0.00 |
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| IDELAYCTRL | 0 | 0 | 0 | 5 | 0.00 |
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| IBUFDS | 0 | 0 | 0 | 104 | 0.00 |
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| GTPE2_CHANNEL | 0 | 0 | 0 | 2 | 0.00 |
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| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 0 | 20 | 0.00 |
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| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 0 | 20 | 0.00 |
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| IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 0 | 250 | 0.00 |
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| IBUFDS_GTE2 | 0 | 0 | 0 | 2 | 0.00 |
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| ILOGIC | 0 | 0 | 0 | 106 | 0.00 |
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| OLOGIC | 0 | 0 | 0 | 106 | 0.00 |
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+-----------------------------+------+-------+------------+-----------+-------+
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6. Clocking
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-----------
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+------------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+------------+------+-------+------------+-----------+-------+
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| BUFGCTRL | 1 | 0 | 0 | 32 | 3.13 |
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| BUFIO | 0 | 0 | 0 | 20 | 0.00 |
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| MMCME2_ADV | 0 | 0 | 0 | 5 | 0.00 |
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| PLLE2_ADV | 0 | 0 | 0 | 5 | 0.00 |
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| BUFMRCE | 0 | 0 | 0 | 10 | 0.00 |
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| BUFHCE | 0 | 0 | 0 | 72 | 0.00 |
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| BUFR | 0 | 0 | 0 | 20 | 0.00 |
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+------------+------+-------+------------+-----------+-------+
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7. Specific Feature
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-------------------
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+-------------+------+-------+------------+-----------+-------+
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| Site Type | Used | Fixed | Prohibited | Available | Util% |
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+-------------+------+-------+------------+-----------+-------+
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| BSCANE2 | 0 | 0 | 0 | 4 | 0.00 |
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| CAPTUREE2 | 0 | 0 | 0 | 1 | 0.00 |
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| DNA_PORT | 0 | 0 | 0 | 1 | 0.00 |
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| EFUSE_USR | 0 | 0 | 0 | 1 | 0.00 |
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| FRAME_ECCE2 | 0 | 0 | 0 | 1 | 0.00 |
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| ICAPE2 | 0 | 0 | 0 | 2 | 0.00 |
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| PCIE_2_1 | 0 | 0 | 0 | 1 | 0.00 |
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| STARTUPE2 | 0 | 0 | 0 | 1 | 0.00 |
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| XADC | 0 | 0 | 0 | 1 | 0.00 |
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+-------------+------+-------+------------+-----------+-------+
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8. Primitives
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-------------
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+----------+------+---------------------+
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| Ref Name | Used | Functional Category |
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+----------+------+---------------------+
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| LUT6 | 484 | LUT |
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| FDCE | 419 | Flop & Latch |
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| LUT5 | 295 | LUT |
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| LUT2 | 229 | LUT |
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| LUT3 | 207 | LUT |
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| LUT4 | 179 | LUT |
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| FDRE | 128 | Flop & Latch |
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| RAMD32 | 68 | Distributed Memory |
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| CARRY4 | 59 | CarryLogic |
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| RAMS32 | 20 | Distributed Memory |
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| OBUF | 3 | IO |
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| LUT1 | 3 | LUT |
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| IBUF | 3 | IO |
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| RAMB18E1 | 2 | Block Memory |
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| BUFG | 1 | Clock |
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+----------+------+---------------------+
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9. Black Boxes
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--------------
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+----------+------+
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| Ref Name | Used |
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+----------+------+
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10. Instantiated Netlists
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-------------------------
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+----------+------+
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| Ref Name | Used |
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+----------+------+
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