42 lines
1.2 KiB
Verilog
42 lines
1.2 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: nope
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// Engineer: Jose
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//
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// Create Date: 02/20/2026 09:21:52 AM
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// Design Name: EX/ME register
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// Module Name: ex_me
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// Project Name: riscv-ac
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// Target Devices: Artix 7
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// Tool Versions: 2025.2
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// Description: Register between EX/ME stages
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//
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// Dependencies:
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//
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// Revision: 1.0
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module ex_me (
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input clk, rst,
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input we_reg_in, we_mem_in, mem_to_reg_in,
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output reg we_reg_out, we_mem_out, mem_to_reg_out,
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input [31:0] alu_in, regB_in, pc4_in,
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input [4:0] rd_in,
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output reg [31:0] alu_out, regB_out, pc4_out,
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output reg [4:0] rd_out
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);
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always @(posedge clk or posedge rst) begin
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if (rst) begin
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we_reg_out <= 0; we_mem_out <= 0; mem_to_reg_out <= 0;
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alu_out <= 0; regB_out <= 0; pc4_out <= 0; rd_out <= 0;
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end else begin
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we_reg_out <= we_reg_in; we_mem_out <= we_mem_in; mem_to_reg_out <= mem_to_reg_in;
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alu_out <= alu_in; regB_out <= regB_in; pc4_out <= pc4_in; rd_out <= rd_in;
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end
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end
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endmodule |