103 lines
2.7 KiB
Verilog
103 lines
2.7 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: nope
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// Engineer: Jose
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//
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// Create Date: 02/20/2026 09:21:52 AM
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// Design Name: RISCV AC Processor Simulation
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// Module Name: tb_top
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// Project Name: riscv-ac
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// Target Devices: Artix 7
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// Tool Versions: 2025.2
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// Description: Testbench for simulation + MMIO
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//
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// Dependencies:
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//
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// Revision: 2.0 - MMIO
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// Revision: 1.0 - Basic structure
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// Revision: 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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module tb_top();
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reg clk;
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reg rst;
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wire [1:0] leds;
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wire [7:0] uart_tx_data;
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wire uart_tx_en;
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reg rx;
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wire tx;
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top uut (
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.clk(clk),
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.rst(rst),
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.rx(rx),
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.tx(tx),
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.leds(leds),
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.uart_tx_data(uart_tx_data),
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.uart_tx_en(uart_tx_en)
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);
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// T_CLK = 10ns
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always #5 clk = ~clk;
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task send_uart_byte;
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input [7:0] data;
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integer i;
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begin
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// 1. Bit de Start (bajamos a 0)
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rx = 0;
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#(868 * 10); // Esperamos los ciclos de 1 bit (104 ciclos * 10ns)
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// 2. Mandamos los 8 bits de datos (LSB primero, de derecha a izquierda)
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for (i = 0; i < 8; i = i + 1) begin
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rx = data[i];
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#(868 * 10);
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end
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// 3. Bit de Stop (subimos a 1)
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rx = 1;
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#(868 * 10);
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end
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endtask
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initial begin
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// inicializamos señales
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clk = 0;
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rst = 1;
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rx = 1;
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// (SOLO SIMULACION) cargamos programa
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//$readmemh("/home/jomaa/git/riscv-ac/riscv-ac.srcs/sim_1/new/program.mem", uut.u_imem.memory);
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// activamos reset 20ns
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#20;
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rst = 0;
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// mandamos instrucciones
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#100;
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// 1. addi x5, x0, 65 (04100293) -> cargamos 'A' (65) en x5
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send_uart_byte(8'h93); send_uart_byte(8'h02); send_uart_byte(8'h10); send_uart_byte(8'h04);
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// 2. addi x6, x0, -4 (ffc00313) -> cargamos la dirección de la UART mapeada (0xFFFFFFFC) en x6
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send_uart_byte(8'h13); send_uart_byte(8'h03); send_uart_byte(8'hC0); send_uart_byte(8'hFF);
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// 3. sw x5, 0(x6) (00532023) -> alla que va pa la UART
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send_uart_byte(8'h23); send_uart_byte(8'h20); send_uart_byte(8'h53); send_uart_byte(8'h00);
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// 4. jal x0, 0 (0000006f) -> fin
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send_uart_byte(8'h6F); send_uart_byte(8'h00); send_uart_byte(8'h00); send_uart_byte(8'h00);
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#(55000 * 10)
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#2000;
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$finish;
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end
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endmodule |