57 lines
1.2 KiB
Verilog
57 lines
1.2 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: nope
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// Engineer: Jose
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//
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// Create Date: 02/20/2026 09:21:52 AM
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// Design Name: Instruction Memory
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// Module Name: imem
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// Project Name: riscv-ac
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// Target Devices: Artix 7
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// Tool Versions: 2025.2
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// Description: Stores instructions
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//
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// Dependencies:
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//
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// Revision: 2.0 - Dual port for UART programming
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// Revision: 1.0 - Basic structure
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// Revision: 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module imem(
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input clk,
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// puerto 1
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input [31:0] read_addr,
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output [31:0] inst_out,
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// puerto 2
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input we_ext,
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input [31:0] write_addr_ext,
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input [31:0] write_data_ext
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);
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reg [31:0] memory[0:255];
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reg [31:0] inst_reg;
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integer i;
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initial begin
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for (i = 0; i < 256; i = i + 1) begin
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memory[i] = 32'b0;
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end
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end
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always @(posedge clk) begin
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if(we_ext) begin
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memory[write_addr_ext[9:2]] <= write_data_ext;
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end
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inst_reg <= memory[read_addr[9:2]];
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end
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assign inst_out = inst_reg;
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endmodule
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