Jose 534cb00c42 fixed: uart module and simulation-only signals handling

2026-03-07 21:53:09 +01:00

..

xsim.dir

fixed: uart module and simulation-only signals handling

2026-03-07 21:53:09 +01:00

compile.sh

fixed: uart module and simulation-only signals handling

2026-03-07 21:53:09 +01:00

elaborate.sh

fixed: uart module and simulation-only signals handling

2026-03-07 21:53:09 +01:00

glbl.v

prototype works

2026-03-02 23:20:54 +01:00

program.mem

add: dual port imem and uart

2026-03-03 01:44:27 +01:00

simulate.sh

fixed: uart module and simulation-only signals handling

2026-03-07 21:53:09 +01:00

tb_riscv_behav.wdb

fixed: uart module and simulation-only signals handling

2026-03-07 21:53:09 +01:00

tb_riscv_vlog.prj

refactor: renamed top.v to riscv.v

2026-03-03 04:05:49 +01:00

tb_riscv.tcl

refactor: renamed top.v to riscv.v

2026-03-03 04:05:49 +01:00

tb_top_behav.wdb

refactor: renamed top.v to riscv.v

2026-03-03 04:05:49 +01:00

tb_top.tcl

prototype works

2026-03-02 23:20:54 +01:00

tb_top.vcd

prototype works

2026-03-02 23:20:54 +01:00

xsim.ini

prototype works

2026-03-02 23:20:54 +01:00