57 lines
1.9 KiB
Verilog
57 lines
1.9 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: nope
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// Engineer: Jose
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//
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// Create Date: 02/20/2026 09:21:52 AM
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// Design Name: ID/EX register
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// Module Name: id_ex
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// Project Name: riscv-ac
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// Target Devices: Artix 7
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// Tool Versions: 2025.2
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// Description: Register between ID/EX stages
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//
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// Dependencies:
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//
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// Revision: 1.0
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module id_ex (
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input clk, rst, clr,
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// señales de la UC y ALU
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input we_reg_in, we_mem_in, mem_to_reg_in, alu_src_in, branch_in, jump_in,
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input [3:0] alu_op_in,
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output reg we_reg_out, we_mem_out, mem_to_reg_out, alu_src_out, branch_out, jump_out,
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output reg [3:0] alu_op_out,
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// PC4, A, B, Inmediato, Regs
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input [31:0] pc4_in, regA_in, regB_in, regC_in,
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input [4:0] rs1_in, rs2_in, rd_in,
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output reg [31:0] pc4_out, regA_out, regB_out, regC_out,
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output reg [4:0] rs1_out, rs2_out, rd_out
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);
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always @(posedge clk or posedge rst) begin
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if (rst || clr) begin
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we_reg_out <= 0; we_mem_out <= 0; mem_to_reg_out <= 0;
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alu_src_out <= 0; branch_out <= 0; jump_out <= 0; alu_op_out <= 4'b0;
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pc4_out <= 0; regA_out <= 0; regB_out <= 0; regC_out <= 0;
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rs1_out <= 0; rs2_out <= 0; rd_out <= 0;
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end
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else begin
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we_reg_out <= we_reg_in; we_mem_out <= we_mem_in;
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mem_to_reg_out <= mem_to_reg_in; alu_src_out <= alu_src_in;
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branch_out <= branch_in; jump_out <= jump_in; alu_op_out <= alu_op_in;
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pc4_out <= pc4_in;
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regA_out <= regA_in; regB_out <= regB_in; regC_out <= regC_in;
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rs1_out <= rs1_in; rs2_out <= rs2_in; rd_out <= rd_in;
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end
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end
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endmodule |