70 lines
2.0 KiB
Verilog
70 lines
2.0 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company: nope
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// Engineer: Jose
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//
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// Create Date: 02/20/2026 09:21:52 AM
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// Design Name: Forwarding
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// Module Name: forwarding
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// Project Name: riscv-ac
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// Target Devices: Artix 7
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// Tool Versions: 2025.2
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// Description: Manages forwarding MUXes selection inputs
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//
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// Dependencies:
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//
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// Revision: 1.0
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module forwarding (
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input [4:0] ID_EX_Rs1,
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input [4:0] ID_EX_Rs2,
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input [4:0] IF_ID_Rs1,
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input [4:0] IF_ID_Rs2,
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input [4:0] EX_ME_Rd,
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input EX_ME_RegWrite,
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input [4:0] ME_WB_Rd,
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input ME_WB_RegWrite,
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output reg [1:0] EX_ForwardA,
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output reg [1:0] EX_ForwardB,
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output reg [1:0] ID_ForwardA,
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output reg [1:0] ID_ForwardB
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);
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always @(*) begin
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EX_ForwardA = 2'b00;
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EX_ForwardB = 2'b00;
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ID_ForwardA = 2'b00;
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ID_ForwardB = 2'b00;
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// Bypass A (EX)
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if (EX_ME_RegWrite && (EX_ME_Rd != 0) && (EX_ME_Rd == ID_EX_Rs1))
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EX_ForwardA = 2'b10;
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else if (ME_WB_RegWrite && (ME_WB_Rd != 0) && (ME_WB_Rd == ID_EX_Rs1))
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EX_ForwardA = 2'b01;
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// Bypass B (EX)
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if (EX_ME_RegWrite && (EX_ME_Rd != 0) && (EX_ME_Rd == ID_EX_Rs2))
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EX_ForwardB = 2'b10;
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else if (ME_WB_RegWrite && (ME_WB_Rd != 0) && (ME_WB_Rd == ID_EX_Rs2))
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EX_ForwardB = 2'b01;
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// Bypass A (ID)
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if (EX_ME_RegWrite && (EX_ME_Rd != 0) && (EX_ME_Rd == IF_ID_Rs1))
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ID_ForwardA = 2'b10;
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else if (ME_WB_RegWrite && (ME_WB_Rd != 0) && (ME_WB_Rd == IF_ID_Rs1))
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ID_ForwardA = 2'b01;
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// Bypass B (ID)
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if (EX_ME_RegWrite && (EX_ME_Rd != 0) && (EX_ME_Rd == IF_ID_Rs2))
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ID_ForwardB = 2'b10;
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else if (ME_WB_RegWrite && (ME_WB_Rd != 0) && (ME_WB_Rd == IF_ID_Rs2))
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ID_ForwardB = 2'b01;
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end
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endmodule
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