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Gallardo7761/riscv-ac

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History

Jose 534cb00c42 fixed: uart module and simulation-only signals handling

2026-03-07 21:53:09 +01:00

..

fixed: uart module and simulation-only signals handling

2026-03-07 21:53:09 +01:00

Compile_Options.txt

refactor: renamed top.v to riscv.v

2026-03-03 04:05:49 +01:00

TempBreakPointFile.txt

refactor: renamed top.v to riscv.v

2026-03-03 04:05:49 +01:00

xsim.dbg

fixed: uart module and simulation-only signals handling

2026-03-07 21:53:09 +01:00

xsim.mem

fixed: uart module and simulation-only signals handling

2026-03-07 21:53:09 +01:00

xsim.reloc

fixed: uart module and simulation-only signals handling

2026-03-07 21:53:09 +01:00

xsim.rlx

fixed: uart module and simulation-only signals handling

2026-03-07 21:53:09 +01:00

xsim.rtti

fixed: uart module and simulation-only signals handling

2026-03-07 21:53:09 +01:00

xsim.svtype

refactor: renamed top.v to riscv.v

2026-03-03 04:05:49 +01:00

xsim.type

refactor: renamed top.v to riscv.v

2026-03-03 04:05:49 +01:00

xsim.version

refactor: renamed top.v to riscv.v

2026-03-03 04:05:49 +01:00

xsim.xdbg

fixed: uart module and simulation-only signals handling

2026-03-07 21:53:09 +01:00

xsimk

fixed: uart module and simulation-only signals handling

2026-03-07 21:53:09 +01:00

xsimSettings.ini

fixed: uart module and simulation-only signals handling

2026-03-07 21:53:09 +01:00