6 Commits

Author	SHA1	Message	Date
Jose	d7e166ca6f	refactor: renamed top.v to riscv.v	2026-03-03 04:05:49 +01:00
Jose	a4b158d6a8	add: uart_tx module	2026-03-03 03:41:56 +01:00
Jose	a890b031a7	add: dual port imem and uart	2026-03-03 01:44:27 +01:00
Jose	98f948ab18	refactor: renamed all signals for consistency	2026-03-02 23:34:31 +01:00
Jose	e7cd451e7e	prototype works	2026-03-02 23:20:54 +01:00
Jose	8f2b31259c	Initial commit	2026-02-20 11:33:05 +01:00