prototype works

riscv-ac.sim/sim_1/behav/xsim/compile.sh

@@ -0,0 +1,28 @@
+#!/bin/bash -f
+# ****************************************************************************
+# Vivado (TM) v2025.2 (64-bit)
+#
+# Filename    : compile.sh
+# Simulator   : AMD Vivado Simulator
+# Description : Script for compiling the simulation design source files
+#
+# Generated by Vivado on Mon Mar 02 22:22:56 CET 2026
+# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: compile.sh
+#
+# ****************************************************************************
+export SIM_VER_XSIM=2025.2
+export GCC_VER_XSIM=9.3.0
+
+# catch pipeline exit status
+set -Eeuo pipefail
+# compile Verilog/System Verilog design sources
+echo "xvlog --incr --relax -prj tb_top_vlog.prj"
+xvlog --incr --relax -prj tb_top_vlog.prj 2>&1 | tee compile.log
+
+echo "Waiting for jobs to finish..."
+echo "No pending jobs, compilation finished."

riscv-ac.sim/sim_1/behav/xsim/elaborate.sh

@@ -0,0 +1,26 @@
+#!/bin/bash -f
+# ****************************************************************************
+# Vivado (TM) v2025.2 (64-bit)
+#
+# Filename    : elaborate.sh
+# Simulator   : AMD Vivado Simulator
+# Description : Script for elaborating the compiled design
+#
+# Generated by Vivado on Mon Mar 02 22:22:58 CET 2026
+# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: elaborate.sh
+#
+# ****************************************************************************
+export SIM_VER_XSIM=2025.2
+export GCC_VER_XSIM=9.3.0
+
+# catch pipeline exit status
+set -Eeuo pipefail
+# elaborate design
+echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_top_behav xil_defaultlib.tb_top xil_defaultlib.glbl -log elaborate.log"
+xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_top_behav xil_defaultlib.tb_top xil_defaultlib.glbl -log elaborate.log
+

riscv-ac.sim/sim_1/behav/xsim/glbl.v

@@ -0,0 +1,84 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
+`ifndef GLBL
+`define GLBL
+`timescale  1 ps / 1 ps
+
+module glbl ();
+
+    parameter ROC_WIDTH = 100000;
+    parameter TOC_WIDTH = 0;
+    parameter GRES_WIDTH = 10000;
+    parameter GRES_START = 10000;
+
+//--------   STARTUP Globals --------------
+    wire GSR;
+    wire GTS;
+    wire GWE;
+    wire PRLD;
+    wire GRESTORE;
+    tri1 p_up_tmp;
+    tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
+
+    wire PROGB_GLBL;
+    wire CCLKO_GLBL;
+    wire FCSBO_GLBL;
+    wire [3:0] DO_GLBL;
+    wire [3:0] DI_GLBL;
+   
+    reg GSR_int;
+    reg GTS_int;
+    reg PRLD_int;
+    reg GRESTORE_int;
+
+//--------   JTAG Globals --------------
+    wire JTAG_TDO_GLBL;
+    wire JTAG_TCK_GLBL;
+    wire JTAG_TDI_GLBL;
+    wire JTAG_TMS_GLBL;
+    wire JTAG_TRST_GLBL;
+
+    reg JTAG_CAPTURE_GLBL;
+    reg JTAG_RESET_GLBL;
+    reg JTAG_SHIFT_GLBL;
+    reg JTAG_UPDATE_GLBL;
+    reg JTAG_RUNTEST_GLBL;
+
+    reg JTAG_SEL1_GLBL = 0;
+    reg JTAG_SEL2_GLBL = 0 ;
+    reg JTAG_SEL3_GLBL = 0;
+    reg JTAG_SEL4_GLBL = 0;
+
+    reg JTAG_USER_TDO1_GLBL = 1'bz;
+    reg JTAG_USER_TDO2_GLBL = 1'bz;
+    reg JTAG_USER_TDO3_GLBL = 1'bz;
+    reg JTAG_USER_TDO4_GLBL = 1'bz;
+
+    assign (strong1, weak0) GSR = GSR_int;
+    assign (strong1, weak0) GTS = GTS_int;
+    assign (weak1, weak0) PRLD = PRLD_int;
+    assign (strong1, weak0) GRESTORE = GRESTORE_int;
+
+    initial begin
+	GSR_int = 1'b1;
+	PRLD_int = 1'b1;
+	#(ROC_WIDTH)
+	GSR_int = 1'b0;
+	PRLD_int = 1'b0;
+    end
+
+    initial begin
+	GTS_int = 1'b1;
+	#(TOC_WIDTH)
+	GTS_int = 1'b0;
+    end
+
+    initial begin 
+	GRESTORE_int = 1'b0;
+	#(GRES_START);
+	GRESTORE_int = 1'b1;
+	#(GRES_WIDTH);
+	GRESTORE_int = 1'b0;
+    end
+
+endmodule
+`endif

riscv-ac.sim/sim_1/behav/xsim/program.mem

@@ -0,0 +1,3 @@
+000000B3
+00810113
+002080B3

riscv-ac.sim/sim_1/behav/xsim/simulate.sh

@@ -0,0 +1,26 @@
+#!/bin/bash -f
+# ****************************************************************************
+# Vivado (TM) v2025.2 (64-bit)
+#
+# Filename    : simulate.sh
+# Simulator   : AMD Vivado Simulator
+# Description : Script for simulating the design by launching the simulator
+#
+# Generated by Vivado on Mon Mar 02 22:16:52 CET 2026
+# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025
+#
+# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
+# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
+#
+# usage: simulate.sh
+#
+# ****************************************************************************
+export SIM_VER_XSIM=2025.2
+export GCC_VER_XSIM=9.3.0
+
+# catch pipeline exit status
+set -Eeuo pipefail
+# simulate design
+echo "xsim tb_top_behav -key {Behavioral:sim_1:Functional:tb_top} -tclbatch tb_top.tcl -log simulate.log"
+xsim tb_top_behav -key {Behavioral:sim_1:Functional:tb_top} -tclbatch tb_top.tcl -log simulate.log
+

riscv-ac.sim/sim_1/behav/xsim/tb_top.tcl

@@ -0,0 +1,11 @@
+set curr_wave [current_wave_config]
+if { [string length $curr_wave] == 0 } {
+  if { [llength [get_objects]] > 0} {
+    add_wave /
+    set_property needs_save false [current_wave_config]
+  } else {
+     send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
+  }
+}
+
+run 1000ns

riscv-ac.sim/sim_1/behav/xsim/tb_top_vlog.prj

@@ -0,0 +1,23 @@
+# compile verilog/system verilog design source files
+verilog xil_defaultlib  --include "../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef" \
+"../../../../riscv-ac.srcs/sources_1/new/alu.v" \
+"../../../../riscv-ac.srcs/sources_1/new/control.v" \
+"../../../../riscv-ac.srcs/sources_1/new/dmem.v" \
+"../../../../riscv-ac.srcs/sources_1/new/ex_me.v" \
+"../../../../riscv-ac.srcs/sources_1/new/forwarding.v" \
+"../../../../riscv-ac.srcs/sources_1/new/hazard.v" \
+"../../../../riscv-ac.srcs/sources_1/new/id_ex.v" \
+"../../../../riscv-ac.srcs/sources_1/new/if_id.v" \
+"../../../../riscv-ac.srcs/sources_1/new/imem.v" \
+"../../../../riscv-ac.srcs/sources_1/new/imm_gen.v" \
+"../../../../riscv-ac.srcs/sources_1/new/me_wb.v" \
+"../../../../riscv-ac.srcs/sources_1/new/pc.v" \
+"../../../../riscv-ac.srcs/sources_1/new/regfile.v" \
+"../../../../riscv-ac.srcs/sources_1/new/top.v" \
+"../../../../riscv-ac.srcs/sim_1/new/tb_top.v" \
+
+# compile glbl module
+verilog xil_defaultlib "glbl.v"
+
+# Do not sort compile order
+nosort

riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/Compile_Options.txt

@@ -0,0 +1 @@
+--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "tb_top_behav" "xil_defaultlib.tb_top" "xil_defaultlib.glbl" -log "elaborate.log" 

riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/TempBreakPointFile.txt

@@ -0,0 +1 @@
+Breakpoint File Version 1.0

riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.rlx

@@ -0,0 +1,12 @@
+
+{ 
+    crc :  1048859293793588504  , 
+    ccp_crc :  0  , 
+    cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_top_behav xil_defaultlib.tb_top xil_defaultlib.glbl" , 
+    buildDate : "Nov 14 2025" , 
+    buildTime : "12:36:23" , 
+    linkCmd : "/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/g++ -Wa,-W  -O -fPIC  -m64  -Wl,--no-as-needed  -Wl,--unresolved-symbols=ignore-all  -o \"xsim.dir/tb_top_behav/xsimk\"   \"xsim.dir/tb_top_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/tb_top_behav/obj/xsim_1.lnx64.o\" -L\"/opt/Xilinx/2025.2/Vivado/lib/lnx64.o\" -lxv_simulator_kernel    -L/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lxv_simbridge_kernel" , 
+    aggregate_nets : 
+    [ 
+    ] 
+} 

riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.version

@@ -0,0 +1 @@
+hjhoth

riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsimSettings.ini

@@ -0,0 +1,50 @@
+[General]
+ARRAY_DISPLAY_LIMIT=512
+RADIX=hex
+TIME_UNIT=ns
+TRACE_LIMIT=2147483647
+VHDL_ENTITY_SCOPE_FILTER=true
+VHDL_PACKAGE_SCOPE_FILTER=false
+VHDL_BLOCK_SCOPE_FILTER=true
+VHDL_PROCESS_SCOPE_FILTER=false
+VHDL_PROCEDURE_SCOPE_FILTER=false
+VERILOG_MODULE_SCOPE_FILTER=true
+VERILOG_PACKAGE_SCOPE_FILTER=false
+VERILOG_BLOCK_SCOPE_FILTER=false
+VERILOG_TASK_SCOPE_FILTER=false
+VERILOG_PROCESS_SCOPE_FILTER=false
+INPUT_OBJECT_FILTER=true
+OUTPUT_OBJECT_FILTER=true
+INOUT_OBJECT_FILTER=true
+INTERNAL_OBJECT_FILTER=true
+CONSTANT_OBJECT_FILTER=true
+VARIABLE_OBJECT_FILTER=true
+INPUT_PROTOINST_FILTER=true
+OUTPUT_PROTOINST_FILTER=true
+INOUT_PROTOINST_FILTER=true
+INTERNAL_PROTOINST_FILTER=true
+CONSTANT_PROTOINST_FILTER=true
+VARIABLE_PROTOINST_FILTER=true
+SCOPE_NAME_COLUMN_WIDTH=93
+SCOPE_DESIGN_UNIT_COLUMN_WIDTH=83
+SCOPE_BLOCK_TYPE_COLUMN_WIDTH=103
+OBJECT_NAME_COLUMN_WIDTH=121
+OBJECT_VALUE_COLUMN_WIDTH=72
+OBJECT_DATA_TYPE_COLUMN_WIDTH=75
+PROCESS_NAME_COLUMN_WIDTH=75
+PROCESS_TYPE_COLUMN_WIDTH=75
+FRAME_INDEX_COLUMN_WIDTH=75
+FRAME_NAME_COLUMN_WIDTH=75
+FRAME_FILE_NAME_COLUMN_WIDTH=75
+FRAME_LINE_NUM_COLUMN_WIDTH=75
+LOCAL_NAME_COLUMN_WIDTH=75
+LOCAL_VALUE_COLUMN_WIDTH=75
+LOCAL_DATA_TYPE_COLUMN_WIDTH=0
+PROTO_NAME_COLUMN_WIDTH=0
+PROTO_VALUE_COLUMN_WIDTH=0
+INPUT_LOCAL_FILTER=1
+OUTPUT_LOCAL_FILTER=1
+INOUT_LOCAL_FILTER=1
+INTERNAL_LOCAL_FILTER=1
+CONSTANT_LOCAL_FILTER=1
+VARIABLE_LOCAL_FILTER=1

riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx

@@ -0,0 +1,20 @@
+0.7
+2020.2
+Nov 14 2025
+12:36:23
+/home/jomaa/git/riscv-ac/riscv-ac.sim/sim_1/behav/xsim/glbl.v,1756381829,verilog,,,,glbl,,,,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sim_1/new/tb_top.v,1772486573,verilog,,,,tb_top,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/alu.v,1772483312,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/control.v,,alu,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/control.v,1772483371,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/dmem.v,,control,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/dmem.v,1772485582,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/ex_me.v,,dmem,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/ex_me.v,1772468735,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/forwarding.v,,ex_me,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/forwarding.v,1772467332,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/hazard.v,,forwarding,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/hazard.v,1772467244,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/id_ex.v,,hazard,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/id_ex.v,1772472446,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/if_id.v,,id_ex,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/if_id.v,1772468688,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imem.v,,if_id,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imem.v,1772485445,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imm_gen.v,,imem,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imm_gen.v,1772470571,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/me_wb.v,,imm_gen,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/me_wb.v,1772468767,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/pc.v,,me_wb,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/pc.v,1772289140,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/regfile.v,,pc,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/regfile.v,1772483280,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/top.v,,regfile,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,
+/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/top.v,1772486142,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sim_1/new/tb_top.v,,top,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,,

riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xsim.version

@@ -0,0 +1 @@
+hjhoth

riscv-ac.sim/sim_1/behav/xsim/xsim.ini

@@ -0,0 +1 @@
+xil_defaultlib=xsim.dir/xil_defaultlib

riscv-ac.srcs/constrs_1/new/CmodA7_Master.xdc

@@ -0,0 +1,139 @@
+## This file is a general .xdc for the CmodA7 rev. B
+## To use it in a project:
+## - uncomment the lines corresponding to used pins
+## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project
+
+# Clock signal 12 MHz
+set_property -dict { PACKAGE_PIN L17   IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_14 Sch=gclk
+create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports {clk}];
+
+
+## LEDs
+set_property -dict { PACKAGE_PIN A17   IOSTANDARD LVCMOS33 } [get_ports { leds[0] }]; #IO_L12N_T1_MRCC_16 Sch=led[1]
+set_property -dict { PACKAGE_PIN C16   IOSTANDARD LVCMOS33 } [get_ports { leds[1] }]; #IO_L13P_T2_MRCC_16 Sch=led[2]
+
+#set_property -dict { PACKAGE_PIN B17   IOSTANDARD LVCMOS33 } [get_ports { led_b}]; #IO_L14N_T2_SRCC_16 Sch=led0_b
+#set_property -dict { PACKAGE_PIN B16   IOSTANDARD LVCMOS33 } [get_ports { led_g }]; #IO_L13N_T2_MRCC_16 Sch=led0_g
+#set_property -dict { PACKAGE_PIN C17   IOSTANDARD LVCMOS33 } [get_ports { led }]; #IO_L14P_T2_SRCC_16 Sch=led0_r
+
+
+# Buttons
+set_property -dict { PACKAGE_PIN A18   IOSTANDARD LVCMOS33 } [get_ports { rst }]; #IO_L19N_T3_VREF_16 Sch=btn[0]
+#set_property -dict { PACKAGE_PIN B18   IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L19P_T3_16 Sch=btn[1]
+
+
+## Pmod Header JA
+#set_property -dict { PACKAGE_PIN G17   IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L5N_T0_D07_14 Sch=ja[1]
+#set_property -dict { PACKAGE_PIN G19   IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4N_T0_D05_14 Sch=ja[2]
+#set_property -dict { PACKAGE_PIN N18   IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L9P_T1_DQS_14 Sch=ja[3]
+#set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L8P_T1_D11_14 Sch=ja[4]
+#set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L5P_T0_D06_14 Sch=ja[7]
+#set_property -dict { PACKAGE_PIN H19   IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L4P_T0_D04_14 Sch=ja[8]
+#set_property -dict { PACKAGE_PIN J19   IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L6N_T0_D08_VREF_14 Sch=ja[9]
+#set_property -dict { PACKAGE_PIN K18   IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L8N_T1_D12_14 Sch=ja[10]
+
+
+# Analog XADC Pins
+# Only declare these if you want to use pins 15 and 16 as single ended analog inputs. pin 15 -> vaux4, pin16 -> vaux12
+#set_property -dict { PACKAGE_PIN G2    IOSTANDARD LVCMOS33 } [get_ports { xa_n[0] }]; #IO_L1N_T0_AD4N_35 Sch=ain_n[15]
+#set_property -dict { PACKAGE_PIN G3    IOSTANDARD LVCMOS33 } [get_ports { xa_p[0] }]; #IO_L1P_T0_AD4P_35 Sch=ain_p[15]
+#set_property -dict { PACKAGE_PIN J2    IOSTANDARD LVCMOS33 } [get_ports { xa_n[1] }]; #IO_L2N_T0_AD12N_35 Sch=ain_n[16]
+#set_property -dict { PACKAGE_PIN H2    IOSTANDARD LVCMOS33 } [get_ports { xa_p[1] }]; #IO_L2P_T0_AD12P_35 Sch=ain_p[16]
+
+
+## GPIO Pins
+## Pins 15 and 16 should remain commented if using them as analog inputs
+set_property -dict { PACKAGE_PIN M3    IOSTANDARD LVCMOS33 } [get_ports { debug[0] }]; #IO_L8N_T1_AD14N_35 Sch=pio[01]
+set_property -dict { PACKAGE_PIN L3    IOSTANDARD LVCMOS33 } [get_ports { debug[1] }]; #IO_L8P_T1_AD14P_35 Sch=pio[02]
+set_property -dict { PACKAGE_PIN A16   IOSTANDARD LVCMOS33 } [get_ports { debug[2] }]; #IO_L12P_T1_MRCC_16 Sch=pio[03]
+set_property -dict { PACKAGE_PIN K3    IOSTANDARD LVCMOS33 } [get_ports { debug[3] }]; #IO_L7N_T1_AD6N_35 Sch=pio[04]
+set_property -dict { PACKAGE_PIN C15   IOSTANDARD LVCMOS33 } [get_ports { debug[4] }]; #IO_L11P_T1_SRCC_16 Sch=pio[05]
+set_property -dict { PACKAGE_PIN H1    IOSTANDARD LVCMOS33 } [get_ports { debug[5] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=pio[06]
+set_property -dict { PACKAGE_PIN A15   IOSTANDARD LVCMOS33 } [get_ports { debug[6] }]; #IO_L6N_T0_VREF_16 Sch=pio[07]
+set_property -dict { PACKAGE_PIN B15   IOSTANDARD LVCMOS33 } [get_ports { debug[7] }]; #IO_L11N_T1_SRCC_16 Sch=pio[08]
+set_property -dict { PACKAGE_PIN A14   IOSTANDARD LVCMOS33 } [get_ports { debug[8] }]; #IO_L6P_T0_16 Sch=pio[09]
+set_property -dict { PACKAGE_PIN J3    IOSTANDARD LVCMOS33 } [get_ports { debug[9] }]; #IO_L7P_T1_AD6P_35 Sch=pio[10]
+set_property -dict { PACKAGE_PIN J1    IOSTANDARD LVCMOS33 } [get_ports { debug[10] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=pio[11]
+set_property -dict { PACKAGE_PIN K2    IOSTANDARD LVCMOS33 } [get_ports { debug[11] }]; #IO_L5P_T0_AD13P_35 Sch=pio[12]
+set_property -dict { PACKAGE_PIN L1    IOSTANDARD LVCMOS33 } [get_ports { debug[12] }]; #IO_L6N_T0_VREF_35 Sch=pio[13]
+set_property -dict { PACKAGE_PIN L2    IOSTANDARD LVCMOS33 } [get_ports { debug[13] }]; #IO_L5N_T0_AD13N_35 Sch=pio[14]
+set_property -dict { PACKAGE_PIN M1    IOSTANDARD LVCMOS33 } [get_ports { debug[14] }]; #IO_L9N_T1_DQS_AD7N_35 Sch=pio[17]
+set_property -dict { PACKAGE_PIN N3    IOSTANDARD LVCMOS33 } [get_ports { debug[15] }]; #IO_L12P_T1_MRCC_35 Sch=pio[18]
+set_property -dict { PACKAGE_PIN P3    IOSTANDARD LVCMOS33 } [get_ports { debug[16] }]; #IO_L12N_T1_MRCC_35 Sch=pio[19]
+set_property -dict { PACKAGE_PIN M2    IOSTANDARD LVCMOS33 } [get_ports { debug[17] }]; #IO_L9P_T1_DQS_AD7P_35 Sch=pio[20]
+set_property -dict { PACKAGE_PIN N1    IOSTANDARD LVCMOS33 } [get_ports { debug[18] }]; #IO_L10N_T1_AD15N_35 Sch=pio[21]
+set_property -dict { PACKAGE_PIN N2    IOSTANDARD LVCMOS33 } [get_ports { debug[19] }]; #IO_L10P_T1_AD15P_35 Sch=pio[22]
+set_property -dict { PACKAGE_PIN P1    IOSTANDARD LVCMOS33 } [get_ports { debug[20] }]; #IO_L19N_T3_VREF_35 Sch=pio[23]
+set_property -dict { PACKAGE_PIN R3    IOSTANDARD LVCMOS33 } [get_ports { debug[21] }]; #IO_L2P_T0_34 Sch=pio[26]
+set_property -dict { PACKAGE_PIN T3    IOSTANDARD LVCMOS33 } [get_ports { debug[22] }]; #IO_L2N_T0_34 Sch=pio[27]
+set_property -dict { PACKAGE_PIN R2    IOSTANDARD LVCMOS33 } [get_ports { debug[23] }]; #IO_L1P_T0_34 Sch=pio[28]
+set_property -dict { PACKAGE_PIN T1    IOSTANDARD LVCMOS33 } [get_ports { debug[24] }]; #IO_L3P_T0_DQS_34 Sch=pio[29]
+set_property -dict { PACKAGE_PIN T2    IOSTANDARD LVCMOS33 } [get_ports { debug[25] }]; #IO_L1N_T0_34 Sch=pio[30]
+set_property -dict { PACKAGE_PIN U1    IOSTANDARD LVCMOS33 } [get_ports { debug[26] }]; #IO_L3N_T0_DQS_34 Sch=pio[31]
+set_property -dict { PACKAGE_PIN W2    IOSTANDARD LVCMOS33 } [get_ports { debug[27] }]; #IO_L5N_T0_34 Sch=pio[32]
+set_property -dict { PACKAGE_PIN V2    IOSTANDARD LVCMOS33 } [get_ports { debug[28] }]; #IO_L5P_T0_34 Sch=pio[33]
+set_property -dict { PACKAGE_PIN W3    IOSTANDARD LVCMOS33 } [get_ports { debug[29] }]; #IO_L6N_T0_VREF_34 Sch=pio[34]
+set_property -dict { PACKAGE_PIN V3    IOSTANDARD LVCMOS33 } [get_ports { debug[30] }]; #IO_L6P_T0_34 Sch=pio[35]
+set_property -dict { PACKAGE_PIN W5    IOSTANDARD LVCMOS33 } [get_ports { debug[31] }]; #IO_L12P_T1_MRCC_34 Sch=pio[36]
+#set_property -dict { PACKAGE_PIN V4    IOSTANDARD LVCMOS33 } [get_ports { pio[37] }]; #IO_L11N_T1_SRCC_34 Sch=pio[37]
+#set_property -dict { PACKAGE_PIN U4    IOSTANDARD LVCMOS33 } [get_ports { pio[38] }]; #IO_L11P_T1_SRCC_34 Sch=pio[38]
+#set_property -dict { PACKAGE_PIN V5    IOSTANDARD LVCMOS33 } [get_ports { pio[39] }]; #IO_L16N_T2_34 Sch=pio[39]
+#set_property -dict { PACKAGE_PIN W4    IOSTANDARD LVCMOS33 } [get_ports { pio[40] }]; #IO_L12N_T1_MRCC_34 Sch=pio[40]
+#set_property -dict { PACKAGE_PIN U5    IOSTANDARD LVCMOS33 } [get_ports { pio[41] }]; #IO_L16P_T2_34 Sch=pio[41]
+#set_property -dict { PACKAGE_PIN U2    IOSTANDARD LVCMOS33 } [get_ports { pio[42] }]; #IO_L9N_T1_DQS_34 Sch=pio[42]
+#set_property -dict { PACKAGE_PIN W6    IOSTANDARD LVCMOS33 } [get_ports { pio[43] }]; #IO_L13N_T2_MRCC_34 Sch=pio[43]
+#set_property -dict { PACKAGE_PIN U3    IOSTANDARD LVCMOS33 } [get_ports { pio[44] }]; #IO_L9P_T1_DQS_34 Sch=pio[44]
+#set_property -dict { PACKAGE_PIN U7    IOSTANDARD LVCMOS33 } [get_ports { pio[45] }]; #IO_L19P_T3_34 Sch=pio[45]
+#set_property -dict { PACKAGE_PIN W7    IOSTANDARD LVCMOS33 } [get_ports { pio[46] }]; #IO_L13P_T2_MRCC_34 Sch=pio[46]
+#set_property -dict { PACKAGE_PIN U8    IOSTANDARD LVCMOS33 } [get_ports { pio[47] }]; #IO_L14P_T2_SRCC_34 Sch=pio[47]
+#set_property -dict { PACKAGE_PIN V8    IOSTANDARD LVCMOS33 } [get_ports { pio[48] }]; #IO_L14N_T2_SRCC_34 Sch=pio[48]
+
+
+## UART
+#set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L7N_T1_D10_14 Sch=uart_rxd_out
+#set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in  }]; #IO_L7P_T1_D09_14 Sch=uart_txd_in
+
+
+## Crypto 1 Wire Interface
+#set_property -dict { PACKAGE_PIN D17   IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_0_14 Sch=crypto_sda
+
+
+## QSPI
+#set_property -dict { PACKAGE_PIN K19   IOSTANDARD LVCMOS33 } [get_ports { qspi_cs    }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs
+#set_property -dict { PACKAGE_PIN D18   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0]
+#set_property -dict { PACKAGE_PIN D19   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1]
+#set_property -dict { PACKAGE_PIN G18   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2]
+#set_property -dict { PACKAGE_PIN F18   IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3]
+
+
+## Cellular RAM
+#set_property -dict { PACKAGE_PIN M18   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[0]  }]; #IO_L11P_T1_SRCC_14 Sch=sram- a[0]
+#set_property -dict { PACKAGE_PIN M19   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[1]  }]; #IO_L11N_T1_SRCC_14 Sch=sram- a[1]
+#set_property -dict { PACKAGE_PIN K17   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[2]  }]; #IO_L12N_T1_MRCC_14 Sch=sram- a[2]
+#set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[3]  }]; #IO_L13P_T2_MRCC_14 Sch=sram- a[3]
+#set_property -dict { PACKAGE_PIN P17   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[4]  }]; #IO_L13N_T2_MRCC_14 Sch=sram- a[4]
+#set_property -dict { PACKAGE_PIN P18   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[5]  }]; #IO_L14P_T2_SRCC_14 Sch=sram- a[5]
+#set_property -dict { PACKAGE_PIN R18   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[6]  }]; #IO_L14N_T2_SRCC_14 Sch=sram- a[6]
+#set_property -dict { PACKAGE_PIN W19   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[7]  }]; #IO_L16N_T2_A15_D31_14 Sch=sram- a[7]
+#set_property -dict { PACKAGE_PIN U19   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[8]  }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sram- a[8]
+#set_property -dict { PACKAGE_PIN V19   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[9]  }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=sram- a[9]
+#set_property -dict { PACKAGE_PIN W18   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[10] }]; #IO_L16P_T2_CSI_B_14 Sch=sram- a[10]
+#set_property -dict { PACKAGE_PIN T17   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[11] }]; #IO_L17P_T2_A14_D30_14 Sch=sram- a[11]
+#set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[12] }]; #IO_L17N_T2_A13_D29_14 Sch=sram- a[12]
+#set_property -dict { PACKAGE_PIN U17   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[13] }]; #IO_L18P_T2_A12_D28_14 Sch=sram- a[13]
+#set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[14] }]; #IO_L18N_T2_A11_D27_14 Sch=sram- a[14]
+#set_property -dict { PACKAGE_PIN V16   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[15] }]; #IO_L19P_T3_A10_D26_14 Sch=sram- a[15]
+#set_property -dict { PACKAGE_PIN W16   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[16] }]; #IO_L20P_T3_A08_D24_14 Sch=sram- a[16]
+#set_property -dict { PACKAGE_PIN W17   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[17] }]; #IO_L20N_T3_A07_D23_14 Sch=sram- a[17]
+#set_property -dict { PACKAGE_PIN V15   IOSTANDARD LVCMOS33 } [get_ports { MemAdr[18] }]; #IO_L21P_T3_DQS_14 Sch=sram- a[18]
+#set_property -dict { PACKAGE_PIN W15   IOSTANDARD LVCMOS33 } [get_ports { MemDB[0]   }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=sram-dq[0]
+#set_property -dict { PACKAGE_PIN W13   IOSTANDARD LVCMOS33 } [get_ports { MemDB[1]   }]; #IO_L22P_T3_A05_D21_14 Sch=sram-dq[1]
+#set_property -dict { PACKAGE_PIN W14   IOSTANDARD LVCMOS33 } [get_ports { MemDB[2]   }]; #IO_L22N_T3_A04_D20_14 Sch=sram-dq[2]
+#set_property -dict { PACKAGE_PIN U15   IOSTANDARD LVCMOS33 } [get_ports { MemDB[3]   }]; #IO_L23P_T3_A03_D19_14 Sch=sram-dq[3]
+#set_property -dict { PACKAGE_PIN U16   IOSTANDARD LVCMOS33 } [get_ports { MemDB[4]   }]; #IO_L23N_T3_A02_D18_14 Sch=sram-dq[4]
+#set_property -dict { PACKAGE_PIN V13   IOSTANDARD LVCMOS33 } [get_ports { MemDB[5]   }]; #IO_L24P_T3_A01_D17_14 Sch=sram-dq[5]
+#set_property -dict { PACKAGE_PIN V14   IOSTANDARD LVCMOS33 } [get_ports { MemDB[6]   }]; #IO_L24N_T3_A00_D16_14 Sch=sram-dq[6]
+#set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33 } [get_ports { MemDB[7]   }]; #IO_25_14 Sch=sram-dq[7]
+#set_property -dict { PACKAGE_PIN P19   IOSTANDARD LVCMOS33 } [get_ports { RamOEn     }]; #IO_L10P_T1_D14_14 Sch=sram-oe
+#set_property -dict { PACKAGE_PIN R19   IOSTANDARD LVCMOS33 } [get_ports { RamWEn     }]; #IO_L10N_T1_D15_14 Sch=sram-we
+#set_property -dict { PACKAGE_PIN N19   IOSTANDARD LVCMOS33 } [get_ports { RamCEn     }]; #IO_L9N_T1_DQS_D13_14 Sch=sram-ce

riscv-ac.srcs/sim_1/new/program.mem

@@ -0,0 +1,3 @@
+000000B3
+00810113
+002080B3

riscv-ac.srcs/sim_1/new/tb_top.v

@@ -0,0 +1,58 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer: 
+// 
+// Create Date: 03/01/2026 07:26:34 PM
+// Design Name: 
+// Module Name: tb_top
+// Project Name: 
+// Target Devices: 
+// Tool Versions: 
+// Description: 
+// 
+// Dependencies: 
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+`timescale 1ns / 1ps
+
+module tb_top();
+    reg clk;
+    reg rst;
+    wire [1:0] leds;
+    wire [31:0] debug;
+
+    top uut (
+        .clk(clk),
+        .rst(rst),
+        .leds(leds),
+        .debug(debug)
+    );
+    
+    // T_CLK = 10ns
+    always #5 clk = ~clk;
+
+    initial begin
+        // inicializamos señales
+        clk = 0;
+        rst = 1;
+
+        // cargamos programa
+        $readmemh("/home/jomaa/git/riscv-ac/riscv-ac.srcs/sim_1/new/program.mem", uut.u_imem.memory);
+
+        // activamos reset 20ns
+        #20;
+        rst = 0;
+
+        // ejecución de 100 ciclos
+        #150;
+
+        $finish;
+    end
+endmodule

riscv-ac.srcs/sources_1/new/alu.v

@@ -1,19 +1,19 @@
 `timescale 1ns / 1ps
 //////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
+// Company: nope
+// Engineer: Jose
 // 
 // Create Date: 02/20/2026 09:21:52 AM
-// Design Name: 
+// Design Name: Arithmetic-Logic Unit
 // Module Name: alu
-// Project Name: 
-// Target Devices: 
-// Tool Versions: 
-// Description: 
+// Project Name: riscv-ac
+// Target Devices: Artix 7
+// Tool Versions: 2025.2
+// Description: Main functional unit of the EX stage
 // 
 // Dependencies: 
 // 
-// Revision:
+// Revision: 1.0
 // Revision 0.01 - File Created
 // Additional Comments:
 // 
@@ -29,18 +29,18 @@ module alu(
 
 always @(*) begin
     case(sel)
-        4'b0000: R <= A + B;               // add
-        4'b0001: R <= A - B;               // sub
-        4'b0010: R <= A & B;               // and
-        4'b0011: R <= A | B;               // or
-        4'b0100: R <= A ^ B;               // xor
-        4'b0101: R <= A << B[4:0];         // sll (shamt = 5 bits)
-        4'b0110: R <= A >> B[4:0];         // srl (logical)
-        4'b0111: R <= ($signed(A) < $signed(B)) ? 1 : 0; // slt signed
-        4'b1000: R <= (A < B) ? 1 : 0;     // sltu unsigned
-        4'b1001: R <= $signed(A) >>> B[4:0]; // sra arithmetic right
-        4'b1010: R <= 32'b0;               // default / nop opcional
-        default: R <= 32'b0;
+        4'b0000: R = A + B;                             // add
+        4'b0001: R = A - B;                             // sub
+        4'b0010: R = A & B;                             // and
+        4'b0011: R = A | B;                             // or
+        4'b0100: R = A ^ B;                             // xor
+        4'b0101: R = A << B[4:0];                       // sll
+        4'b0110: R = A >> B[4:0];                       // srl
+        4'b0111: R = ($signed(A) < $signed(B)) ? 1 : 0; // slt (shift if less than signed)
+        4'b1000: R = (A < B) ? 1 : 0;                   // sltu (shift if less than unsigned)
+        4'b1001: R = $signed(A) >>> B[4:0];             // sra (shift right arithmetic)
+        4'b1010: R = 32'b0;                             // nop
+        default: R = 32'b0;                             // default: nop
     endcase
 end
 

riscv-ac.srcs/sources_1/new/control.v

@@ -1,19 +1,19 @@
 `timescale 1ns / 1ps
 //////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
+// Company: nope
+// Engineer: Jose
 // 
 // Create Date: 02/20/2026 09:21:52 AM
-// Design Name: 
+// Design Name: Control Unit
 // Module Name: control
-// Project Name: 
-// Target Devices: 
-// Tool Versions: 
-// Description: 
+// Project Name: riscv-ac
+// Target Devices: Artix 7
+// Tool Versions: 2025.2
+// Description: Manages the logic in the ID stage
 // 
 // Dependencies: 
 // 
-// Revision:
+// Revision: 1.0
 // Revision 0.01 - File Created
 // Additional Comments:
 // 
@@ -22,22 +22,25 @@
 
 module control(
     input [6:0] opcode,
-    input [2:0] funct3,
-    input [6:0] funct7,
+    input [2:0] aux,
+    input [6:0] func,
     output reg we_reg,
     output reg we_mem,
     output reg mem_to_reg,
     output reg alu_src,
     output reg [3:0] alu_op,
-    output reg branch
+    output reg branch,
+    output reg jump
 );
 
-localparam OP_R   = 7'b0110011;
-localparam OP_I   = 7'b0010011;
-localparam OP_LOAD= 7'b0000011;
-localparam OP_STORE=7'b0100011;
-localparam OP_BRANCH=7'b1100011;
-localparam OP_JAL = 7'b1101111;
+// formatos de instrucciones
+localparam ALU_R     = 7'b0110011;
+localparam ALU_I     = 7'b0010011;
+localparam OP_LOAD   = 7'b0000011;
+localparam OP_STORE  = 7'b0100011;
+localparam OP_BRANCH = 7'b1100011;
+localparam OP_JAL    = 7'b1101111;
+localparam OP_JALR   = 7'b1100111;
 
 always @(*) begin 
     we_reg = 0;
@@ -46,12 +49,13 @@ always @(*) begin
     alu_src = 0;
     alu_op = 4'b0000;
     branch = 0;
+    jump = 0; 
     
     case(opcode) 
-        OP_R: begin 
+        ALU_R: begin 
             we_reg = 1;
             alu_src = 0;
-            case({funct7,funct3}) 
+            case({func,aux}) 
                 10'b0000000000: alu_op = 4'b0000; // ADD
                 10'b0100000000: alu_op = 4'b0001; // SUB
                 10'b0000000111: alu_op = 4'b0010; // AND
@@ -65,16 +69,16 @@ always @(*) begin
             endcase
         end
         
-        OP_I: begin 
+        ALU_I: begin 
             we_reg = 1;
             alu_src = 1;
-            case(funct3) 
+            case(aux) 
                 3'b000: alu_op = 4'b0000; // ADDI
                 3'b111: alu_op = 4'b0010; // ANDI
                 3'b110: alu_op = 4'b0011; // ORI
                 3'b100: alu_op = 4'b0100; // XORI
                 3'b001: alu_op = 4'b0101; // SLLI
-                3'b101: alu_op = (funct7==7'b0000000)?4'b0110:4'b0111; // SRLI/SRAI
+                3'b101: alu_op = (func==7'b0000000)?4'b0110:4'b1001; // SRLI/SRAI
                 3'b010: alu_op = 4'b1000; // SLTI
                 3'b011: alu_op = 4'b1001; // SLTIU
             endcase
@@ -82,32 +86,32 @@ always @(*) begin
         
         OP_LOAD: begin
             we_reg = 1;
-            we_mem = 0;
             mem_to_reg = 1;
-            alu_src = 1; // addr = rs1 + immediate
-            alu_op = 4'b0000;
+            alu_src = 1; 
         end
 
         OP_STORE: begin
             we_mem = 1;
-            alu_src = 1; // addr = rs1 + immediate
-            alu_op = 4'b0000;
+            alu_src = 1; 
         end
 
         OP_BRANCH: begin
             branch = 1;
-            alu_src = 0;
             alu_op = 4'b0001;
         end
 
         OP_JAL: begin
-            we_reg = 1;        // rd <- PC+4
+            we_reg = 1; // para guardar la dirección de retorno
+            jump = 1;
+        end
+
+        OP_JALR: begin
+            we_reg = 1;
             alu_src = 1;
-            alu_op = 4'b0000;
+            jump = 1;
         end
         
         default: begin end
-        
     endcase
 end
 

riscv-ac.srcs/sources_1/new/dmem.v

@@ -1,19 +1,19 @@
 `timescale 1ns / 1ps
 //////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
+// Company: nope
+// Engineer: Jose
 // 
 // Create Date: 02/20/2026 09:21:52 AM
-// Design Name: 
+// Design Name: Data Memory
 // Module Name: dmem
-// Project Name: 
-// Target Devices: 
-// Tool Versions: 
-// Description: 
+// Project Name: riscv-ac
+// Target Devices: Artix 7
+// Tool Versions: 2025.2
+// Description: Stores data
 // 
 // Dependencies: 
 // 
-// Revision:
+// Revision: 1.0
 // Revision 0.01 - File Created
 // Additional Comments:
 // 
@@ -29,12 +29,21 @@ module dmem(
 );
 
 reg [31:0] memory[0:255];
+reg [31:0] data;
+
+integer i;
+initial begin
+    for (i = 0; i < 256; i = i + 1) begin
+        memory[i] = 32'b0;
+    end
+end
 
 always @(posedge clk) begin
     if (we)
         memory[address[9:2]] <= write_data;
+    data <= memory[address[9:2]];
 end
 
-assign read_data = memory[address[9:2]];
+assign read_data = data;
 
 endmodule

riscv-ac.srcs/sources_1/new/ex_me.v

@@ -0,0 +1,42 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: nope
+// Engineer: Jose
+// 
+// Create Date: 02/20/2026 09:21:52 AM
+// Design Name: EX/ME register
+// Module Name: ex_me
+// Project Name: riscv-ac
+// Target Devices: Artix 7
+// Tool Versions: 2025.2
+// Description: Register between EX/ME stages
+// 
+// Dependencies: 
+// 
+// Revision: 1.0
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module ex_me (
+    input clk, rst,
+    input we_reg_in, we_mem_in, mem_to_reg_in,
+    output reg we_reg_out, we_mem_out, mem_to_reg_out,
+    input [31:0] alu_in, regB_in, pc4_in,
+    input [4:0] rd_in,
+    output reg [31:0] alu_out, regB_out, pc4_out,
+    output reg [4:0] rd_out
+);
+
+    always @(posedge clk or posedge rst) begin
+        if (rst) begin
+            we_reg_out <= 0; we_mem_out <= 0; mem_to_reg_out <= 0;
+            alu_out <= 0; regB_out <= 0; pc4_out <= 0; rd_out <= 0;
+        end else begin
+            we_reg_out <= we_reg_in; we_mem_out <= we_mem_in; mem_to_reg_out <= mem_to_reg_in;
+            alu_out <= alu_in; regB_out <= regB_in; pc4_out <= pc4_in; rd_out <= rd_in;
+        end
+    end
+endmodule

riscv-ac.srcs/sources_1/new/forwarding.v

@@ -0,0 +1,69 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: nope
+// Engineer: Jose
+// 
+// Create Date: 02/20/2026 09:21:52 AM
+// Design Name: Forwarding
+// Module Name: forwarding
+// Project Name: riscv-ac
+// Target Devices: Artix 7
+// Tool Versions: 2025.2
+// Description: Manages forwarding MUXes selection inputs
+// 
+// Dependencies: 
+// 
+// Revision: 1.0
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module forwarding (
+    input  [4:0] ID_EX_Rs1,
+    input  [4:0] ID_EX_Rs2,
+    input  [4:0] IF_ID_Rs1,
+    input  [4:0] IF_ID_Rs2,
+    input  [4:0] EX_ME_Rd,
+    input        EX_ME_RegWrite,
+    input  [4:0] ME_WB_Rd,
+    input        ME_WB_RegWrite,
+    output reg [1:0] EX_ForwardA,
+    output reg [1:0] EX_ForwardB,
+    output reg [1:0] ID_ForwardA,
+    output reg [1:0] ID_ForwardB
+);
+
+    always @(*) begin
+        EX_ForwardA = 2'b00;
+        EX_ForwardB = 2'b00;
+        ID_ForwardA = 2'b00;
+        ID_ForwardB = 2'b00;
+
+        // Bypass A (EX)
+        if (EX_ME_RegWrite && (EX_ME_Rd != 0) && (EX_ME_Rd == ID_EX_Rs1))
+            EX_ForwardA = 2'b10;
+        else if (ME_WB_RegWrite && (ME_WB_Rd != 0) && (ME_WB_Rd == ID_EX_Rs1))
+            EX_ForwardA = 2'b01;
+
+        // Bypass B (EX)
+        if (EX_ME_RegWrite && (EX_ME_Rd != 0) && (EX_ME_Rd == ID_EX_Rs2))
+            EX_ForwardB = 2'b10;
+        else if (ME_WB_RegWrite && (ME_WB_Rd != 0) && (ME_WB_Rd == ID_EX_Rs2))
+            EX_ForwardB = 2'b01;
+
+        // Bypass A (ID)
+        if (EX_ME_RegWrite && (EX_ME_Rd != 0) && (EX_ME_Rd == IF_ID_Rs1))
+            ID_ForwardA = 2'b10; 
+        else if (ME_WB_RegWrite && (ME_WB_Rd != 0) && (ME_WB_Rd == IF_ID_Rs1))
+            ID_ForwardA = 2'b01; 
+
+        // Bypass B (ID)
+        if (EX_ME_RegWrite && (EX_ME_Rd != 0) && (EX_ME_Rd == IF_ID_Rs2))
+            ID_ForwardB = 2'b10; 
+        else if (ME_WB_RegWrite && (ME_WB_Rd != 0) && (ME_WB_Rd == IF_ID_Rs2))
+            ID_ForwardB = 2'b01; 
+    end
+
+endmodule

riscv-ac.srcs/sources_1/new/hazard.v

@@ -0,0 +1,62 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: nope
+// Engineer: Jose
+// 
+// Create Date: 02/20/2026 09:21:52 AM
+// Design Name: Hazard Unit
+// Module Name: hazard
+// Project Name: riscv-ac
+// Target Devices: Artix 7
+// Tool Versions: 2025.2
+// Description: Manages hazards between memory instructions and any other
+// 
+// Dependencies: 
+// 
+// Revision: 1.0
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module hazard (
+    input [4:0] IF_ID_Rs1,
+    input [4:0] IF_ID_Rs2,
+    input [4:0] ID_EX_Rd,
+    input       ID_EX_MemRead,
+    input       Branch_Taken,
+    output reg PC_En,
+    output reg IF_ID_En,
+    output reg IF_ID_Clr,
+    output reg ID_EX_Clr
+);
+
+    always @(*) begin
+        PC_En     = 1'b1;
+        IF_ID_En  = 1'b1;
+        IF_ID_Clr = 1'b0;
+        ID_EX_Clr = 1'b0;
+
+        // si:
+        // - se lee de memoria
+        // - el Rd no es x0
+        // - el Rd es Rs1 o Rs2
+        // entonces: 
+        //   bloqueamos para que el dato generado en ME lo pueda coger EX
+        if (ID_EX_MemRead && (ID_EX_Rd != 5'b0) && 
+           ((ID_EX_Rd == IF_ID_Rs1) || (ID_EX_Rd == IF_ID_Rs2))) begin
+            PC_En     = 1'b0;
+            IF_ID_En  = 1'b0;
+            ID_EX_Clr = 1'b1;
+        end
+        // si:
+        // - salto tomado
+        // entonces:
+        //   flush síncrono al reg IF/ID
+        else if (Branch_Taken) begin
+            IF_ID_Clr = 1'b1; 
+        end
+    end
+
+endmodule

riscv-ac.srcs/sources_1/new/id_ex.v

@@ -0,0 +1,57 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: nope
+// Engineer: Jose
+// 
+// Create Date: 02/20/2026 09:21:52 AM
+// Design Name: ID/EX register
+// Module Name: id_ex
+// Project Name: riscv-ac
+// Target Devices: Artix 7
+// Tool Versions: 2025.2
+// Description: Register between ID/EX stages
+// 
+// Dependencies: 
+// 
+// Revision: 1.0
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module id_ex (
+    input clk, rst, clr, 
+
+    // señales de la UC y ALU
+    input we_reg_in, we_mem_in, mem_to_reg_in, alu_src_in, branch_in, jump_in,
+    input [3:0] alu_op_in,
+    
+    output reg we_reg_out, we_mem_out, mem_to_reg_out, alu_src_out, branch_out, jump_out,
+    output reg [3:0] alu_op_out,
+
+    // PC4, A, B, C, Rd
+    input [31:0] pc4_in, regA_in, regB_in, regC_in,
+    input [4:0] rs1_in, rs2_in, rd_in,
+    
+    output reg [31:0] pc4_out, regA_out, regB_out, regC_out,
+    output reg [4:0] rs1_out, rs2_out, rd_out
+);
+
+    always @(posedge clk or posedge rst) begin
+        if (rst || clr) begin
+            we_reg_out <= 0; we_mem_out <= 0; mem_to_reg_out <= 0;
+            alu_src_out <= 0; branch_out <= 0; jump_out <= 0; alu_op_out <= 4'b0;
+            pc4_out <= 0; regA_out <= 0; regB_out <= 0; regC_out <= 0;
+            rs1_out <= 0; rs2_out <= 0; rd_out <= 0;
+        end 
+        else begin
+            we_reg_out <= we_reg_in; we_mem_out <= we_mem_in; 
+            mem_to_reg_out <= mem_to_reg_in; alu_src_out <= alu_src_in;
+            branch_out <= branch_in; jump_out <= jump_in; alu_op_out <= alu_op_in;
+            pc4_out <= pc4_in; 
+            regA_out <= regA_in; regB_out <= regB_in; regC_out <= regC_in;
+            rs1_out <= rs1_in; rs2_out <= rs2_in; rd_out <= rd_in;
+        end
+    end
+endmodule

riscv-ac.srcs/sources_1/new/if_id.v

@@ -0,0 +1,51 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: nope
+// Engineer: Jose
+// 
+// Create Date: 02/20/2026 09:21:52 AM
+// Design Name: IF/ID register
+// Module Name: if_id
+// Project Name: riscv-ac
+// Target Devices: Artix 7
+// Tool Versions: 2025.2
+// Description: Register between IF/ID stages
+// 
+// Dependencies: 
+// 
+// Revision: 1.0
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module if_id (
+    input clk,
+    input rst,
+    input en,
+    input clr,
+    input [31:0] npc_in,
+    input [31:0] pc4_in,
+    input [31:0] ir_in,
+    output reg [31:0] npc_out,
+    output reg [31:0] pc4_out,
+    output reg [31:0] ir_out
+);
+
+    always @(posedge clk or posedge rst) begin
+        if (rst) begin
+            npc_out <= 32'b0;
+            pc4_out <= 32'b0;
+            ir_out  <= 32'b0;
+        end else if (clr) begin
+            npc_out <= 32'b0;
+            pc4_out <= 32'b0;
+            ir_out  <= 32'b0; 
+        end else if (en) begin
+            npc_out <= npc_in;
+            pc4_out <= pc4_in;
+            ir_out  <= ir_in;
+        end
+    end
+endmodule

riscv-ac.srcs/sources_1/new/imem.v

@@ -1,19 +1,19 @@
 `timescale 1ns / 1ps
 //////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
+// Company: nope
+// Engineer: Jose
 // 
 // Create Date: 02/20/2026 09:21:52 AM
-// Design Name: 
+// Design Name: Instruction Memory
 // Module Name: imem
-// Project Name: 
-// Target Devices: 
-// Tool Versions: 
-// Description: 
+// Project Name: riscv-ac
+// Target Devices: Artix 7
+// Tool Versions: 2025.2
+// Description: Stores instructions
 // 
 // Dependencies: 
 // 
-// Revision:
+// Revision: 1.0
 // Revision 0.01 - File Created
 // Additional Comments:
 // 
@@ -29,12 +29,21 @@ module imem(
 );
 
 reg [31:0] memory[0:255];
+reg [31:0] ir;
+
+integer i;
+initial begin
+    for (i = 0; i < 256; i = i + 1) begin
+        memory[i] = 32'b0;
+    end
+end
 
 always @(posedge clk) begin
     if(we)
         memory[write_addr] <= write_data;
+    ir <= memory[address[9:2]];
 end
 
-assign instruction = memory[address[9:2]];
+assign instruction = ir;
 
 endmodule

riscv-ac.srcs/sources_1/new/imm_gen.v

@@ -1,37 +1,54 @@
 `timescale 1ns / 1ps
 //////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
+// Company: nope
+// Engineer: Jose
 // 
 // Create Date: 02/20/2026 09:21:52 AM
-// Design Name: 
+// Design Name: Immediate Generator
 // Module Name: imm_gen
-// Project Name: 
-// Target Devices: 
-// Tool Versions: 
-// Description: 
+// Project Name: riscv-ac
+// Target Devices: Artix 7
+// Tool Versions: 2025.2
+// Description: Retrieves the immediate from the instruction (uses verilog concat)
 // 
 // Dependencies: 
 // 
-// Revision:
+// Revision: 1.0
 // Revision 0.01 - File Created
 // Additional Comments:
 // 
 //////////////////////////////////////////////////////////////////////////////////
 
-
 module imm_gen(
-    input [31:0] instr,
+    input  [31:0] instr,
     output reg [31:0] imm_out
 );
 
 always @(*) begin 
     case(instr[6:0]) 
+        // Formato I
         7'b0010011, 
-        7'b0000011:
+        7'b0000011,
+        7'b1100111:
             imm_out = {{20{instr[31]}}, instr[31:20]};
+
+        // Formato S
+        7'b0100011:
+            imm_out = {{20{instr[31]}}, instr[31:25], instr[11:7]};
+
+        // Formato B
+        7'b1100011:
+            imm_out = {{19{instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0};
+
+        // Formato J
         7'b1101111:
             imm_out = {{11{instr[31]}}, instr[31], instr[19:12], instr[20], instr[30:21], 1'b0};
+
+        // Formato U
+        7'b0110111, 
+        7'b0010111:
+            imm_out = {instr[31:12], 12'b0};
+
         default:
             imm_out = 32'b0;
     endcase

riscv-ac.srcs/sources_1/new/me_wb.v

@@ -0,0 +1,42 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+// Company: nope
+// Engineer: Jose
+// 
+// Create Date: 02/20/2026 09:21:52 AM
+// Design Name: ME/WB register
+// Module Name: me_wb
+// Project Name: riscv-ac
+// Target Devices: Artix 7
+// Tool Versions: 2025.2
+// Description: Register between ME/WB stages
+// 
+// Dependencies: 
+// 
+// Revision: 1.0
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+//////////////////////////////////////////////////////////////////////////////////
+
+
+module me_wb (
+    input clk, rst,
+    input we_reg_in, mem_to_reg_in,
+    output reg we_reg_out, mem_to_reg_out,
+    input [31:0] alu_in, mem_data_in, pc4_in,
+    input [4:0] rd_in,
+    output reg [31:0] alu_out, mem_data_out, pc4_out,
+    output reg [4:0] rd_out
+);
+
+    always @(posedge clk or posedge rst) begin
+        if (rst) begin
+            we_reg_out <= 0; mem_to_reg_out <= 0;
+            alu_out <= 0; mem_data_out <= 0; pc4_out <= 0; rd_out <= 0;
+        end else begin
+            we_reg_out <= we_reg_in; mem_to_reg_out <= mem_to_reg_in;
+            alu_out <= alu_in; mem_data_out <= mem_data_in; pc4_out <= pc4_in; rd_out <= rd_in;
+        end
+    end
+endmodule

riscv-ac.srcs/sources_1/new/pc.v

@@ -1,19 +1,19 @@
 `timescale 1ns / 1ps
 //////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
+// Company: nope
+// Engineer: Jose
 // 
 // Create Date: 02/20/2026 09:21:52 AM
-// Design Name: 
+// Design Name: Program Counter
 // Module Name: pc
-// Project Name: 
-// Target Devices: 
-// Tool Versions: 
-// Description: 
+// Project Name: riscv-ac
+// Target Devices: Artix 7
+// Tool Versions: 2025.2
+// Description: Points to the next instruction
 // 
 // Dependencies: 
 // 
-// Revision:
+// Revision: 1.0
 // Revision 0.01 - File Created
 // Additional Comments:
 // 

riscv-ac.srcs/sources_1/new/regfile.v

@@ -1,19 +1,19 @@
 `timescale 1ns / 1ps
 //////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
+// Company: nope
+// Engineer: Jose
 // 
 // Create Date: 02/20/2026 09:21:52 AM
-// Design Name: 
+// Design Name: Register File
 // Module Name: regfile
-// Project Name: 
-// Target Devices: 
-// Tool Versions: 
-// Description: 
+// Project Name: riscv-ac
+// Target Devices: Artix 7
+// Tool Versions: 2025.2
+// Description: Stores temporal values
 // 
 // Dependencies: 
 // 
-// Revision:
+// Revision: 1.0
 // Revision 0.01 - File Created
 // Additional Comments:
 // 
@@ -29,6 +29,13 @@ module regfile(
 
 reg [31:0] regs[0:31];
 
+integer i;
+initial begin
+    for (i = 0; i < 32; i = i + 1) begin
+        regs[i] = 32'b0;
+    end
+end
+
 assign read_data_1 = (rs1 == 0) ? 0 : regs[rs1];
 assign read_data_2 = (rs2 == 0) ? 0 : regs[rs2];
 

riscv-ac.srcs/sources_1/new/top.v

@@ -1,135 +1,197 @@
 `timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
-// 
-// Create Date: 02/20/2026 09:21:52 AM
-// Design Name: 
-// Module Name: top
-// Project Name: 
-// Target Devices: 
-// Tool Versions: 
-// Description: 
-// 
-// Dependencies: 
-// 
-// Revision:
-// Revision 0.01 - File Created
-// Additional Comments:
-// 
-//////////////////////////////////////////////////////////////////////////////////
+`default_nettype none
 
-
-module top(
-    input clk, rst,
-    input [31:0] uart_data,
-    output [31:0] pc_out, alu_out, mem_data
+module top (
+    input clk,
+    input rst,
+    output [1:0] leds,
+    output [31:0] debug
 );
 
-// = PC ===================================
-wire [31:0] pc_next, pc;
-wire branch_taken;
+    // ==========================================
+    // ETAPA IF
+    // ==========================================
+    wire [31:0] npc_IF, pc4_IF, ir_IF, next_pc_IF, pc_stall;
+    wire PC_En, IF_ID_En, IF_ID_Clr; 
 
-pc pc_inst(
-    .clk(clk),
-    .rst(rst),
-    .next_pc(pc_next),
-    .imem_addr(pc_curr)
-);
+    assign next_pc_IF = (Branch_Taken) ? branch_target_ID : pc4_IF;
+    assign pc4_IF = npc_IF + 4;
+    assign pc_stall = (PC_En) ? next_pc_IF : npc_IF;
 
-assign pc_out = pc_curr;
-// ========================================
+    pc u_pc (
+        .clk(clk), 
+        .rst(rst),
+        .next_pc(pc_stall),
+        .imem_addr(npc_IF)
+    );
 
-// = IMEM =================================
-wire [31:0] instr;
+    imem u_imem (
+        .clk(clk), .address(npc_IF), .we(1'b0), 
+        .write_data(32'b0), .write_addr(8'b0), .instruction(ir_IF)
+    );
 
-imem imem_inst(
-    .address(pc_curr),
-    .instruction(instr)
-);
-// ========================================
+    // ==========================================
+    // REGISTRO IF/ID
+    // ==========================================
+    wire [31:0] npc_ID, pc4_ID, ir_ID;
 
-// = DECODE ===============================
-wire [6:0] opcode = instr[6:0];
-wire [4:0] rd     = instr[11:7];
-wire [2:0] funct3 = instr[14:12];
-wire [4:0] rs1    = instr[19:15];
-wire [4:0] rs2    = instr[24:20];
-wire [6:0] funct7 = instr[31:25];
-// ========================================
+    if_id u_if_id (
+        .clk(clk), .rst(rst), .en(IF_ID_En), .clr(IF_ID_Clr),
+        .npc_in(npc_IF), .pc4_in(pc4_IF), .ir_in(ir_IF),
+        .npc_out(npc_ID), .pc4_out(pc4_ID), .ir_out(ir_ID)
+    );
 
-// regfile mux
-wire [31:0] reg_write_data;
-assign reg_write_data = mem_to_reg ? dmem_read_data : alu_out;
+    // ==========================================
+    // ETAPA ID
+    // ==========================================
+    wire [4:0] rs1_ID = ir_ID[19:15];
+    wire [4:0] rs2_ID = ir_ID[24:20];
+    wire [4:0] rd_ID  = ir_ID[11:7];
+    wire [31:0] imm_ID, regA_ID, regB_ID;
     
-// = REGFILE ===============================
-wire [31:0] reg_r1, reg_r2;
-wire we_reg;
+    // Señales de Control
+    wire we_reg_ID, we_mem_ID, mem_to_reg_ID, alu_src_ID, branch_ID, jump_ID;
+    wire [3:0] alu_op_ID;
+    wire Branch_Taken;
+    wire [31:0] branch_target_ID;
 
-regfile regfile_inst(
-    .clk(clk),
-    .regwrite(we_reg),
-    .rs1(rs1),
-    .rs2(rs2),
-    .rd(rd),
-    .write_data(reg_write_data),
-    .read_data_1(reg_r1),
-    .read_data_2(reg_r2)
-);
-// ========================================
+    control u_control (
+        .opcode(ir_ID[6:0]), .aux(ir_ID[14:12]), .func(ir_ID[31:25]), 
+        .we_reg(we_reg_ID), .we_mem(we_mem_ID), .mem_to_reg(mem_to_reg_ID), 
+        .alu_src(alu_src_ID), .alu_op(alu_op_ID), .branch(branch_ID), .jump(jump_ID)
+    );
     
-// = IMMGEN ===============================
-wire [31:0] imm_out;
+    wire [31:0] write_data_WB;
 
-imm_gen imm_gen_inst(
-    .instr(instr),
-    .imm_out(imm_out)
-);
-// ========================================
+    regfile u_regfile (
+        .clk(~clk), 
+        .regwrite(we_reg_WB), .rs1(rs1_ID), .rs2(rs2_ID), .rd(rd_WB), 
+        .write_data(write_data_WB), .read_data_1(regA_ID), .read_data_2(regB_ID)
+    );
 
-// = CONTROL ===============================
-wire we_mem, mem_to_reg, alu_src;
-wire [3:0] alu_op;
+    imm_gen u_imm_gen (
+        .instr(ir_ID), .imm_out(imm_ID)
+    );
 
-control control_inst(
-    .opcode(opcode),
-    .funct3(funct3),
-    .funct7(funct7),
-    .we_reg(we_reg),
-    .we_mem(we_mem),
-    .mem_to_reg(mem_to_reg),
-    .alu_src(alu_src),
-    .alu_op(alu_op),
-    .branch(branch_taken)
-);
-// ========================================
+    wire [1:0] ID_ForwardA, ID_ForwardB;
+    wire [31:0] cmp_A = (ID_ForwardA == 2'b10) ? alu_res_ME : (ID_ForwardA == 2'b01) ? write_data_WB : regA_ID;
+    wire [31:0] cmp_B = (ID_ForwardB == 2'b10) ? alu_res_ME : (ID_ForwardB == 2'b01) ? write_data_WB : regB_ID;
     
-// = ALU ==================================
-wire [31:0] alu_b = alu_src ? imm_out : reg_r2;
+    // salto si JAL/JALR o si condición de BRANCH ok
+    assign Branch_Taken = jump_ID | (branch_ID & (cmp_A == cmp_B)); 
     
-alu alu_inst(
-    .A(reg_r1),
-    .B(alu_b),
-    .sel(alu_op),
-    .R(alu_out)
-);
-// ========================================
+    // MUX DirSalto
+    wire is_jalr = (ir_ID[6:0] == 7'b1100111);
+    wire [31:0] base_salto = is_jalr ? cmp_A : npc_ID;
     
-// = DMEM =================================
-wire [31:0] dmem_read_data;
+    assign branch_target_ID = (base_salto + imm_ID) & ~32'b1;
 
-dmem dmem_inst(
-    .clk(clk),
-    .we(we_mem),
-    .address(alu_out),
-    .write_data(reg_r2),
-    .read_data(dmem_read_data)
-);
+    // detector de riesgos
+    wire ID_EX_Clr;
+    hazard u_hazard (
+        .IF_ID_Rs1(rs1_ID), .IF_ID_Rs2(rs2_ID),
+        .ID_EX_Rd(rd_EX), .ID_EX_MemRead(mem_to_reg_EX),
+        .Branch_Taken(Branch_Taken),
+        .PC_En(PC_En), .IF_ID_En(IF_ID_En), .IF_ID_Clr(IF_ID_Clr), .ID_EX_Clr(ID_EX_Clr)
+    );
 
-assign mem_data = dmem_read_data;
-// ========================================
+    // ==========================================
+    // REGISTRO ID/EX
+    // ==========================================
+    wire [31:0] pc_EX, pc4_EX, regA_EX, regB_EX, imm_EX;
+    wire [4:0] rs1_EX, rs2_EX, rd_EX;
+    wire we_reg_EX, we_mem_EX, mem_to_reg_EX, alu_src_EX, branch_EX, jump_EX;
+    wire [3:0] alu_op_EX;
 
-// PC increment
-assign pc_next = branch_taken ? (pc_curr + imm_out) : (pc_curr + 4);
+    id_ex u_id_ex (
+        .clk(clk), .rst(rst), .clr(ID_EX_Clr),
+        .we_reg_in(we_reg_ID), .we_mem_in(we_mem_ID), .mem_to_reg_in(mem_to_reg_ID), 
+        .alu_src_in(alu_src_ID), .branch_in(branch_ID), .alu_op_in(alu_op_ID), 
+        .jump_in(jump_ID), 
+        .we_reg_out(we_reg_EX), .we_mem_out(we_mem_EX), .mem_to_reg_out(mem_to_reg_EX), 
+        .alu_src_out(alu_src_EX), .branch_out(branch_EX), .alu_op_out(alu_op_EX),
+        .jump_out(jump_EX), 
+        .pc4_in(pc4_ID), .regA_in(regA_ID), .regB_in(regB_ID), .regC_in(imm_ID),
+        .rs1_in(rs1_ID), .rs2_in(rs2_ID), .rd_in(rd_ID),
+        .pc4_out(pc4_EX), .regA_out(regA_EX), .regB_out(regB_EX), .regC_out(imm_EX),
+        .rs1_out(rs1_EX), .rs2_out(rs2_EX), .rd_out(rd_EX)
+    );
+
+    // ==========================================
+    // ETAPA EX
+    // ==========================================
+    wire [1:0] EX_ForwardA, EX_ForwardB;
+    wire [31:0] alu_A, alu_B_temp, alu_B, alu_res_EX_raw, alu_res_EX;
+    wire alu_zero_EX;
+    wire [31:0] alu_res_ME;
+
+    forwarding u_forwarding (
+        .ID_EX_Rs1(rs1_EX), .ID_EX_Rs2(rs2_EX), .IF_ID_Rs1(rs1_ID), .IF_ID_Rs2(rs2_ID),
+        .EX_ME_Rd(rd_ME), .EX_ME_RegWrite(we_reg_ME), .ME_WB_Rd(rd_WB), .ME_WB_RegWrite(we_reg_WB),
+        .EX_ForwardA(EX_ForwardA), .EX_ForwardB(EX_ForwardB),
+        .ID_ForwardA(ID_ForwardA), .ID_ForwardB(ID_ForwardB)
+    );
+
+    assign alu_A      = (EX_ForwardA == 2'b10) ? alu_res_ME : (EX_ForwardA == 2'b01) ? write_data_WB : regA_EX;
+    assign alu_B_temp = (EX_ForwardB == 2'b10) ? alu_res_ME : (EX_ForwardB == 2'b01) ? write_data_WB : regB_EX;
+    assign alu_B      = (alu_src_EX) ? imm_EX : alu_B_temp;
+
+    alu u_alu (
+        .A(alu_A), .B(alu_B), .sel(alu_op_EX), .R(alu_res_EX_raw), .zero(alu_zero_EX)
+    );
+
+    // MUX post-ALU para guardar PC+4 si es un salto (JAL/JALR)
+    assign alu_res_EX = jump_EX ? pc4_EX : alu_res_EX_raw;
+
+    // ==========================================
+    // REGISTRO EX/ME
+    // ==========================================
+    wire [31:0] regB_ME, pc4_ME;
+    wire [4:0] rd_ME;
+    wire we_reg_ME, we_mem_ME, mem_to_reg_ME;
+
+    ex_me u_ex_me (
+        .clk(clk), .rst(rst),
+        .we_reg_in(we_reg_EX), .we_mem_in(we_mem_EX), .mem_to_reg_in(mem_to_reg_EX),
+        .we_reg_out(we_reg_ME), .we_mem_out(we_mem_ME), .mem_to_reg_out(mem_to_reg_ME),
+        .alu_in(alu_res_EX), .regB_in(alu_B_temp), .pc4_in(pc4_EX), .rd_in(rd_EX),
+        .alu_out(alu_res_ME), .regB_out(regB_ME), .pc4_out(pc4_ME), .rd_out(rd_ME)
+    );
+
+    // ==========================================
+    // ETAPA ME & WB
+    // ==========================================
+    wire [31:0] mem_data_ME;
+    dmem u_dmem (
+        .clk(clk), .we(we_mem_ME), .address(alu_res_ME), 
+        .write_data(regB_ME), .read_data(mem_data_ME)
+    );
+
+    wire [31:0] alu_res_WB, mem_data_WB, pc4_WB;
+    wire [4:0] rd_WB;
+    wire we_reg_WB, mem_to_reg_WB;
+
+    me_wb u_me_wb (
+        .clk(clk), .rst(rst),
+        .we_reg_in(we_reg_ME), .mem_to_reg_in(mem_to_reg_ME),
+        .we_reg_out(we_reg_WB), .mem_to_reg_out(mem_to_reg_WB),
+        .alu_in(alu_res_ME), .mem_data_in(mem_data_ME), .pc4_in(pc4_ME), .rd_in(rd_ME),
+        .alu_out(alu_res_WB), .mem_data_out(mem_data_WB), .pc4_out(pc4_WB), .rd_out(rd_WB)
+    );
+
+    assign write_data_WB = (mem_to_reg_WB) ? mem_data_WB : alu_res_WB;
+    
+    // ==========================================
+    // DEBUG
+    // ==========================================
+    assign leds[0] = Branch_Taken; // se enciende cuando hay salto
+    assign leds[1] = ID_EX_Clr; // se enciende en bloqueos
+       
+    assign debug = {
+        alu_res_EX[15:0],
+        rd_WB,
+        rs1_ID,
+        npc_IF[7:2]
+    };
     
 endmodule

riscv-ac.xpr

@@ -4,7 +4,7 @@
 <!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.                   -->
 <!-- Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.   -->
 
-<Project Product="Vivado" Version="7" Minor="71" Path="/home/jomaa/Projects/vivado/riscv-ac/riscv-ac.xpr">
+<Project Product="Vivado" Version="7" Minor="71" Path="/home/jomaa/git/riscv-ac/riscv-ac.xpr">
   <DefaultLaunch Dir="$PRUNDIR"/>
   <Configuration>
     <Option Name="Id" Val="2041d6f4559245b6ae163170cfe36c08"/>
@@ -44,10 +44,11 @@
     <Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
     <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
     <Option Name="BoardPart" Val="digilentinc.com:cmod_a7-35t:part0:1.2"/>
-    <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../.Xilinx/Vivado/2025.2/xhub/board_store/xilinx_board_store"/>
+    <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../.Xilinx/Vivado/2025.2/xhub/board_store/xilinx_board_store"/>
     <Option Name="ActiveSimSet" Val="sim_1"/>
     <Option Name="DefaultLib" Val="xil_defaultlib"/>
     <Option Name="ProjectType" Val="Default"/>
+    <Option Name="IPRepoPath" Val="$PPRDIR/../../ip_repo"/>
     <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
     <Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
     <Option Name="IPCachePermission" Val="read"/>
@@ -60,7 +61,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="cmod_a7-35t"/>
-    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTXSimLaunchSim" Val="22"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -112,6 +113,41 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/sources_1/new/ex_me.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/forwarding.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/hazard.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/id_ex.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sources_1/new/if_id.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <File Path="$PSRCDIR/sources_1/new/imem.v">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -126,6 +162,13 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PSRCDIR/sources_1/new/me_wb.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <File Path="$PSRCDIR/sources_1/new/pc.v">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
@@ -155,16 +198,35 @@
     </FileSet>
     <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
       <Filter Type="Constrs"/>
+      <File Path="$PSRCDIR/constrs_1/new/CmodA7_Master.xdc">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="ConstrsType" Val="XDC"/>
       </Config>
     </FileSet>
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
+      <Filter Type="Srcs"/>
+      <File Path="$PSRCDIR/sim_1/new/program.mem">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PSRCDIR/sim_1/new/tb_top.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="top"/>
+        <Option Name="TopModule" Val="tb_top"/>
         <Option Name="TopLib" Val="xil_defaultlib"/>
-        <Option Name="TopAutoSet" Val="TRUE"/>
         <Option Name="TransportPathDelay" Val="0"/>
         <Option Name="TransportIntDelay" Val="0"/>
         <Option Name="SelectedSimModel" Val="rtl"/>
@@ -173,6 +235,7 @@
         <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
         <Option Name="PamPseudoTop" Val="pseudo_tb"/>
         <Option Name="SrcSet" Val="sources_1"/>
+        <Option Name="XSimWcfgFile" Val="$PPRDIR/tb_top_behav.wcfg"/>
         <Option Name="CosimPdi" Val=""/>
         <Option Name="CosimPlatform" Val=""/>
         <Option Name="CosimElf" Val=""/>
@@ -218,9 +281,7 @@
   <Runs Version="1" Minor="22">
     <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2025">
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2025"/>
         <Step Id="synth_design"/>
       </Strategy>
       <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2025"/>
@@ -229,9 +290,7 @@
     </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a35tcpg236-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2025">
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2025"/>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>

tb_top_behav.wcfg

@@ -0,0 +1,335 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="tb_top_behav.wdb" id="1">
+         <top_modules>
+            <top_module name="glbl" />
+            <top_module name="tb_top" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <zoom_setting>
+      <ZoomStartTime time="0.000 ns"></ZoomStartTime>
+      <ZoomEndTime time="127.201 ns"></ZoomEndTime>
+      <Cursor1Time time="120.000 ns"></Cursor1Time>
+   </zoom_setting>
+   <column_width_setting>
+      <NameColumnWidth column_width="175"></NameColumnWidth>
+      <ValueColumnWidth column_width="146"></ValueColumnWidth>
+   </column_width_setting>
+   <WVObjectSize size="67" />
+   <wvobject type="logic" fp_name="/tb_top/clk">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_top/rst">
+      <obj_property name="ElementShortName">rst</obj_property>
+      <obj_property name="ObjectShortName">rst</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/pc_F">
+      <obj_property name="ElementShortName">pc_F[31:0]</obj_property>
+      <obj_property name="ObjectShortName">pc_F[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/pc4_F">
+      <obj_property name="ElementShortName">pc4_F[31:0]</obj_property>
+      <obj_property name="ObjectShortName">pc4_F[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/instr_F">
+      <obj_property name="ElementShortName">instr_F[31:0]</obj_property>
+      <obj_property name="ObjectShortName">instr_F[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/next_pc_F">
+      <obj_property name="ElementShortName">next_pc_F[31:0]</obj_property>
+      <obj_property name="ObjectShortName">next_pc_F[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_top/uut/PC_En">
+      <obj_property name="ElementShortName">PC_En</obj_property>
+      <obj_property name="ObjectShortName">PC_En</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_top/uut/IF_ID_En">
+      <obj_property name="ElementShortName">IF_ID_En</obj_property>
+      <obj_property name="ObjectShortName">IF_ID_En</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_top/uut/IF_ID_Clr">
+      <obj_property name="ElementShortName">IF_ID_Clr</obj_property>
+      <obj_property name="ObjectShortName">IF_ID_Clr</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/pc_D">
+      <obj_property name="ElementShortName">pc_D[31:0]</obj_property>
+      <obj_property name="ObjectShortName">pc_D[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/pc4_D">
+      <obj_property name="ElementShortName">pc4_D[31:0]</obj_property>
+      <obj_property name="ObjectShortName">pc4_D[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/instr_D">
+      <obj_property name="ElementShortName">instr_D[31:0]</obj_property>
+      <obj_property name="ObjectShortName">instr_D[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/rs1_D">
+      <obj_property name="ElementShortName">rs1_D[4:0]</obj_property>
+      <obj_property name="ObjectShortName">rs1_D[4:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/rs2_D">
+      <obj_property name="ElementShortName">rs2_D[4:0]</obj_property>
+      <obj_property name="ObjectShortName">rs2_D[4:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/rd_D">
+      <obj_property name="ElementShortName">rd_D[4:0]</obj_property>
+      <obj_property name="ObjectShortName">rd_D[4:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/imm_D">
+      <obj_property name="ElementShortName">imm_D[31:0]</obj_property>
+      <obj_property name="ObjectShortName">imm_D[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/regA_D">
+      <obj_property name="ElementShortName">regA_D[31:0]</obj_property>
+      <obj_property name="ObjectShortName">regA_D[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/regB_D">
+      <obj_property name="ElementShortName">regB_D[31:0]</obj_property>
+      <obj_property name="ObjectShortName">regB_D[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_top/uut/we_reg_D">
+      <obj_property name="ElementShortName">we_reg_D</obj_property>
+      <obj_property name="ObjectShortName">we_reg_D</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_top/uut/we_mem_D">
+      <obj_property name="ElementShortName">we_mem_D</obj_property>
+      <obj_property name="ObjectShortName">we_mem_D</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_top/uut/mem_to_reg_D">
+      <obj_property name="ElementShortName">mem_to_reg_D</obj_property>
+      <obj_property name="ObjectShortName">mem_to_reg_D</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_top/uut/alu_src_D">
+      <obj_property name="ElementShortName">alu_src_D</obj_property>
+      <obj_property name="ObjectShortName">alu_src_D</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_top/uut/branch_D">
+      <obj_property name="ElementShortName">branch_D</obj_property>
+      <obj_property name="ObjectShortName">branch_D</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/alu_op_D">
+      <obj_property name="ElementShortName">alu_op_D[3:0]</obj_property>
+      <obj_property name="ObjectShortName">alu_op_D[3:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_top/uut/Branch_Taken">
+      <obj_property name="ElementShortName">Branch_Taken</obj_property>
+      <obj_property name="ObjectShortName">Branch_Taken</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/branch_target_D">
+      <obj_property name="ElementShortName">branch_target_D[31:0]</obj_property>
+      <obj_property name="ObjectShortName">branch_target_D[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/ID_ForwardA">
+      <obj_property name="ElementShortName">ID_ForwardA[1:0]</obj_property>
+      <obj_property name="ObjectShortName">ID_ForwardA[1:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/ID_ForwardB">
+      <obj_property name="ElementShortName">ID_ForwardB[1:0]</obj_property>
+      <obj_property name="ObjectShortName">ID_ForwardB[1:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/cmp_A">
+      <obj_property name="ElementShortName">cmp_A[31:0]</obj_property>
+      <obj_property name="ObjectShortName">cmp_A[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/cmp_B">
+      <obj_property name="ElementShortName">cmp_B[31:0]</obj_property>
+      <obj_property name="ObjectShortName">cmp_B[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_top/uut/ID_EX_Clr">
+      <obj_property name="ElementShortName">ID_EX_Clr</obj_property>
+      <obj_property name="ObjectShortName">ID_EX_Clr</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/pc_E">
+      <obj_property name="ElementShortName">pc_E[31:0]</obj_property>
+      <obj_property name="ObjectShortName">pc_E[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/pc4_E">
+      <obj_property name="ElementShortName">pc4_E[31:0]</obj_property>
+      <obj_property name="ObjectShortName">pc4_E[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/regA_E">
+      <obj_property name="ElementShortName">regA_E[31:0]</obj_property>
+      <obj_property name="ObjectShortName">regA_E[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/regB_E">
+      <obj_property name="ElementShortName">regB_E[31:0]</obj_property>
+      <obj_property name="ObjectShortName">regB_E[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/imm_E">
+      <obj_property name="ElementShortName">imm_E[31:0]</obj_property>
+      <obj_property name="ObjectShortName">imm_E[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/rs1_E">
+      <obj_property name="ElementShortName">rs1_E[4:0]</obj_property>
+      <obj_property name="ObjectShortName">rs1_E[4:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/rs2_E">
+      <obj_property name="ElementShortName">rs2_E[4:0]</obj_property>
+      <obj_property name="ObjectShortName">rs2_E[4:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/rd_E">
+      <obj_property name="ElementShortName">rd_E[4:0]</obj_property>
+      <obj_property name="ObjectShortName">rd_E[4:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_top/uut/we_reg_E">
+      <obj_property name="ElementShortName">we_reg_E</obj_property>
+      <obj_property name="ObjectShortName">we_reg_E</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_top/uut/we_mem_E">
+      <obj_property name="ElementShortName">we_mem_E</obj_property>
+      <obj_property name="ObjectShortName">we_mem_E</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_top/uut/mem_to_reg_E">
+      <obj_property name="ElementShortName">mem_to_reg_E</obj_property>
+      <obj_property name="ObjectShortName">mem_to_reg_E</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_top/uut/alu_src_E">
+      <obj_property name="ElementShortName">alu_src_E</obj_property>
+      <obj_property name="ObjectShortName">alu_src_E</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_top/uut/branch_E">
+      <obj_property name="ElementShortName">branch_E</obj_property>
+      <obj_property name="ObjectShortName">branch_E</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/alu_op_E">
+      <obj_property name="ElementShortName">alu_op_E[3:0]</obj_property>
+      <obj_property name="ObjectShortName">alu_op_E[3:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/EX_ForwardA">
+      <obj_property name="ElementShortName">EX_ForwardA[1:0]</obj_property>
+      <obj_property name="ObjectShortName">EX_ForwardA[1:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/EX_ForwardB">
+      <obj_property name="ElementShortName">EX_ForwardB[1:0]</obj_property>
+      <obj_property name="ObjectShortName">EX_ForwardB[1:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/alu_A">
+      <obj_property name="ElementShortName">alu_A[31:0]</obj_property>
+      <obj_property name="ObjectShortName">alu_A[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/alu_B_temp">
+      <obj_property name="ElementShortName">alu_B_temp[31:0]</obj_property>
+      <obj_property name="ObjectShortName">alu_B_temp[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/alu_B">
+      <obj_property name="ElementShortName">alu_B[31:0]</obj_property>
+      <obj_property name="ObjectShortName">alu_B[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/alu_res_E">
+      <obj_property name="ElementShortName">alu_res_E[31:0]</obj_property>
+      <obj_property name="ObjectShortName">alu_res_E[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_top/uut/alu_zero_E">
+      <obj_property name="ElementShortName">alu_zero_E</obj_property>
+      <obj_property name="ObjectShortName">alu_zero_E</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/alu_res_M">
+      <obj_property name="ElementShortName">alu_res_M[31:0]</obj_property>
+      <obj_property name="ObjectShortName">alu_res_M[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/regB_M">
+      <obj_property name="ElementShortName">regB_M[31:0]</obj_property>
+      <obj_property name="ObjectShortName">regB_M[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/pc4_M">
+      <obj_property name="ElementShortName">pc4_M[31:0]</obj_property>
+      <obj_property name="ObjectShortName">pc4_M[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/rd_M">
+      <obj_property name="ElementShortName">rd_M[4:0]</obj_property>
+      <obj_property name="ObjectShortName">rd_M[4:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_top/uut/we_reg_M">
+      <obj_property name="ElementShortName">we_reg_M</obj_property>
+      <obj_property name="ObjectShortName">we_reg_M</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_top/uut/we_mem_M">
+      <obj_property name="ElementShortName">we_mem_M</obj_property>
+      <obj_property name="ObjectShortName">we_mem_M</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_top/uut/mem_to_reg_M">
+      <obj_property name="ElementShortName">mem_to_reg_M</obj_property>
+      <obj_property name="ObjectShortName">mem_to_reg_M</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/mem_data_M">
+      <obj_property name="ElementShortName">mem_data_M[31:0]</obj_property>
+      <obj_property name="ObjectShortName">mem_data_M[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/alu_res_W">
+      <obj_property name="ElementShortName">alu_res_W[31:0]</obj_property>
+      <obj_property name="ObjectShortName">alu_res_W[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/mem_data_W">
+      <obj_property name="ElementShortName">mem_data_W[31:0]</obj_property>
+      <obj_property name="ObjectShortName">mem_data_W[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/pc4_W">
+      <obj_property name="ElementShortName">pc4_W[31:0]</obj_property>
+      <obj_property name="ObjectShortName">pc4_W[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/rd_W">
+      <obj_property name="ElementShortName">rd_W[4:0]</obj_property>
+      <obj_property name="ObjectShortName">rd_W[4:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_top/uut/we_reg_W">
+      <obj_property name="ElementShortName">we_reg_W</obj_property>
+      <obj_property name="ObjectShortName">we_reg_W</obj_property>
+   </wvobject>
+   <wvobject type="logic" fp_name="/tb_top/uut/mem_to_reg_W">
+      <obj_property name="ElementShortName">mem_to_reg_W</obj_property>
+      <obj_property name="ObjectShortName">mem_to_reg_W</obj_property>
+   </wvobject>
+   <wvobject type="array" fp_name="/tb_top/uut/write_data_W">
+      <obj_property name="ElementShortName">write_data_W[31:0]</obj_property>
+      <obj_property name="ObjectShortName">write_data_W[31:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+</wave_config>