diff --git a/riscv-ac.sim/sim_1/behav/xsim/compile.sh b/riscv-ac.sim/sim_1/behav/xsim/compile.sh new file mode 100755 index 0000000..b388302 --- /dev/null +++ b/riscv-ac.sim/sim_1/behav/xsim/compile.sh @@ -0,0 +1,28 @@ +#!/bin/bash -f +# **************************************************************************** +# Vivado (TM) v2025.2 (64-bit) +# +# Filename : compile.sh +# Simulator : AMD Vivado Simulator +# Description : Script for compiling the simulation design source files +# +# Generated by Vivado on Mon Mar 02 22:22:56 CET 2026 +# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 +# +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +# +# usage: compile.sh +# +# **************************************************************************** +export SIM_VER_XSIM=2025.2 +export GCC_VER_XSIM=9.3.0 + +# catch pipeline exit status +set -Eeuo pipefail +# compile Verilog/System Verilog design sources +echo "xvlog --incr --relax -prj tb_top_vlog.prj" +xvlog --incr --relax -prj tb_top_vlog.prj 2>&1 | tee compile.log + +echo "Waiting for jobs to finish..." +echo "No pending jobs, compilation finished." diff --git a/riscv-ac.sim/sim_1/behav/xsim/elaborate.sh b/riscv-ac.sim/sim_1/behav/xsim/elaborate.sh new file mode 100755 index 0000000..a912f99 --- /dev/null +++ b/riscv-ac.sim/sim_1/behav/xsim/elaborate.sh @@ -0,0 +1,26 @@ +#!/bin/bash -f +# **************************************************************************** +# Vivado (TM) v2025.2 (64-bit) +# +# Filename : elaborate.sh +# Simulator : AMD Vivado Simulator +# Description : Script for elaborating the compiled design +# +# Generated by Vivado on Mon Mar 02 22:22:58 CET 2026 +# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 +# +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +# +# usage: elaborate.sh +# +# **************************************************************************** +export SIM_VER_XSIM=2025.2 +export GCC_VER_XSIM=9.3.0 + +# catch pipeline exit status +set -Eeuo pipefail +# elaborate design +echo "xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_top_behav xil_defaultlib.tb_top xil_defaultlib.glbl -log elaborate.log" +xelab --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_top_behav xil_defaultlib.tb_top xil_defaultlib.glbl -log elaborate.log + diff --git a/riscv-ac.sim/sim_1/behav/xsim/glbl.v b/riscv-ac.sim/sim_1/behav/xsim/glbl.v new file mode 100644 index 0000000..ed3b249 --- /dev/null +++ b/riscv-ac.sim/sim_1/behav/xsim/glbl.v @@ -0,0 +1,84 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $ +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + parameter GRES_WIDTH = 10000; + parameter GRES_START = 10000; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + wire GRESTORE; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + reg GRESTORE_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + assign (strong1, weak0) GRESTORE = GRESTORE_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + + initial begin + GRESTORE_int = 1'b0; + #(GRES_START); + GRESTORE_int = 1'b1; + #(GRES_WIDTH); + GRESTORE_int = 1'b0; + end + +endmodule +`endif diff --git a/riscv-ac.sim/sim_1/behav/xsim/program.mem b/riscv-ac.sim/sim_1/behav/xsim/program.mem new file mode 100755 index 0000000..3571c71 --- /dev/null +++ b/riscv-ac.sim/sim_1/behav/xsim/program.mem @@ -0,0 +1,3 @@ +000000B3 +00810113 +002080B3 \ No newline at end of file diff --git a/riscv-ac.sim/sim_1/behav/xsim/simulate.sh b/riscv-ac.sim/sim_1/behav/xsim/simulate.sh new file mode 100755 index 0000000..782e214 --- /dev/null +++ b/riscv-ac.sim/sim_1/behav/xsim/simulate.sh @@ -0,0 +1,26 @@ +#!/bin/bash -f +# **************************************************************************** +# Vivado (TM) v2025.2 (64-bit) +# +# Filename : simulate.sh +# Simulator : AMD Vivado Simulator +# Description : Script for simulating the design by launching the simulator +# +# Generated by Vivado on Mon Mar 02 22:16:52 CET 2026 +# SW Build 6299465 on Fri Nov 14 12:34:56 MST 2025 +# +# Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +# Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved. +# +# usage: simulate.sh +# +# **************************************************************************** +export SIM_VER_XSIM=2025.2 +export GCC_VER_XSIM=9.3.0 + +# catch pipeline exit status +set -Eeuo pipefail +# simulate design +echo "xsim tb_top_behav -key {Behavioral:sim_1:Functional:tb_top} -tclbatch tb_top.tcl -log simulate.log" +xsim tb_top_behav -key {Behavioral:sim_1:Functional:tb_top} -tclbatch tb_top.tcl -log simulate.log + diff --git a/riscv-ac.sim/sim_1/behav/xsim/tb_top.tcl b/riscv-ac.sim/sim_1/behav/xsim/tb_top.tcl new file mode 100644 index 0000000..1094e45 --- /dev/null +++ b/riscv-ac.sim/sim_1/behav/xsim/tb_top.tcl @@ -0,0 +1,11 @@ +set curr_wave [current_wave_config] +if { [string length $curr_wave] == 0 } { + if { [llength [get_objects]] > 0} { + add_wave / + set_property needs_save false [current_wave_config] + } else { + send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console." + } +} + +run 1000ns diff --git a/riscv-ac.sim/sim_1/behav/xsim/tb_top.vcd b/riscv-ac.sim/sim_1/behav/xsim/tb_top.vcd new file mode 100644 index 0000000..704e984 --- /dev/null +++ b/riscv-ac.sim/sim_1/behav/xsim/tb_top.vcd @@ -0,0 +1,7391 @@ +$date + Sun Mar 1 19:39:07 2026 +$end + +$version + 2025.2 + $dumpfile ("tb_top.vcd") +$end + +$timescale + 1ps +$end + +$scope module tb_top $end +$var reg 1 ! clk $end +$var reg 1 " rst $end +$scope module uut $end +$var wire 1 # clk $end +$var wire 1 $ rst $end +$var wire 32 % pc_F [31:0] $end +$var wire 32 & pc4_F [31:0] $end +$var wire 32 ' instr_F [31:0] $end +$var wire 32 ( next_pc_F [31:0] $end +$var wire 1 ) PC_En $end +$var wire 1 * IF_ID_En $end +$var wire 1 + IF_ID_Clr $end +$var wire 32 , pc_D [31:0] $end +$var wire 32 - pc4_D [31:0] $end +$var wire 32 . instr_D [31:0] $end +$var wire 5 / rs1_D [4:0] $end +$var wire 5 0 rs2_D [4:0] $end +$var wire 5 1 rd_D [4:0] $end +$var wire 32 2 imm_D [31:0] $end +$var wire 32 3 regA_D [31:0] $end +$var wire 32 4 regB_D [31:0] $end +$var wire 1 5 we_reg_D $end +$var wire 1 6 we_mem_D $end +$var wire 1 7 mem_to_reg_D $end +$var wire 1 8 alu_src_D $end +$var wire 1 9 branch_D $end +$var wire 4 : alu_op_D [3:0] $end +$var wire 1 ; Branch_Taken $end +$var wire 32 < branch_target_D [31:0] $end +$var wire 2 = ID_ForwardA [1:0] $end +$var wire 2 > ID_ForwardB [1:0] $end +$var wire 32 ? cmp_A [31:0] $end +$var wire 32 @ cmp_B [31:0] $end +$var wire 1 A ID_EX_Clr $end +$var wire 32 B pc_E [31:0] $end +$var wire 32 C pc4_E [31:0] $end +$var wire 32 D regA_E [31:0] $end +$var wire 32 E regB_E [31:0] $end +$var wire 32 F imm_E [31:0] $end +$var wire 5 G rs1_E [4:0] $end +$var wire 5 H rs2_E [4:0] $end +$var wire 5 I rd_E [4:0] $end +$var wire 1 J we_reg_E $end +$var wire 1 K we_mem_E $end +$var wire 1 L mem_to_reg_E $end +$var wire 1 M alu_src_E $end +$var wire 1 N branch_E $end +$var wire 4 O alu_op_E [3:0] $end +$var wire 2 P EX_ForwardA [1:0] $end +$var wire 2 Q EX_ForwardB [1:0] $end +$var wire 32 R alu_A [31:0] $end +$var wire 32 S alu_B_temp [31:0] $end +$var wire 32 T alu_B [31:0] $end +$var wire 32 U alu_res_E [31:0] $end +$var wire 1 V alu_zero_E $end +$var wire 32 W alu_res_M [31:0] $end +$var wire 32 X regB_M [31:0] $end +$var wire 32 Y pc4_M [31:0] $end +$var wire 5 Z rd_M [4:0] $end +$var wire 1 [ we_reg_M $end +$var wire 1 \ we_mem_M $end +$var wire 1 ] mem_to_reg_M $end +$var wire 32 ^ mem_data_M [31:0] $end +$var wire 32 _ alu_res_W [31:0] $end +$var wire 32 ` mem_data_W [31:0] $end +$var wire 32 a pc4_W [31:0] $end +$var wire 5 b rd_W [4:0] $end +$var wire 1 c we_reg_W $end +$var wire 1 d mem_to_reg_W $end +$var wire 32 e write_data_W [31:0] $end +$scope module u_pc $end +$var wire 1 # clk $end +$var wire 1 f rst $end +$var wire 32 ( next_pc [31:0] $end +$var reg 32 g imem_addr [31:0] $end +$upscope $end +$scope module u_imem $end +$var wire 1 # clk $end +$var wire 32 % address [31:0] $end +$var wire 1 h we $end +$var wire 32 i write_data [31:0] $end +$var wire 8 j write_addr [7:0] $end +$var wire 32 ' instruction [31:0] $end +$upscope $end +$scope module u_if_id $end +$var wire 1 # clk $end +$var wire 1 $ rst $end +$var wire 1 * en $end +$var wire 1 + clr $end +$var wire 32 % pc_in [31:0] $end +$var wire 32 & pc4_in [31:0] $end +$var wire 32 ' inst_in [31:0] $end +$var reg 32 k pc_out [31:0] $end +$var reg 32 l pc4_out [31:0] $end +$var reg 32 m inst_out [31:0] $end +$upscope $end +$scope module u_control $end +$var wire 7 n opcode [6:0] $end +$var wire 3 o aux [14:12] $end +$var wire 7 p func [31:25] $end +$var reg 1 q we_reg $end +$var reg 1 r we_mem $end +$var reg 1 s mem_to_reg $end +$var reg 1 t alu_src $end +$var reg 4 u alu_op [3:0] $end +$var reg 1 v branch $end +$upscope $end +$scope module u_regfile $end +$var wire 1 w clk $end +$var wire 1 c regwrite $end +$var wire 5 / rs1 [4:0] $end +$var wire 5 0 rs2 [4:0] $end +$var wire 5 b rd [4:0] $end +$var wire 32 e write_data [31:0] $end +$var wire 32 3 read_data_1 [31:0] $end +$var wire 32 4 read_data_2 [31:0] $end +$upscope $end +$scope module u_imm_gen $end +$var wire 32 . instr [31:0] $end +$var reg 32 x imm_out [31:0] $end +$upscope $end +$scope module u_hazard $end +$var wire 5 / IF_ID_Rs1 [4:0] $end +$var wire 5 0 IF_ID_Rs2 [4:0] $end +$var wire 5 I ID_EX_Rd [4:0] $end +$var wire 1 L ID_EX_MemRead $end +$var wire 1 ; Branch_Taken $end +$var reg 1 y PC_En $end +$var reg 1 z IF_ID_En $end +$var reg 1 { IF_ID_Clr $end +$var reg 1 | ID_EX_Clr $end +$upscope $end +$scope module u_id_ex $end +$var wire 1 # clk $end +$var wire 1 $ rst $end +$var wire 1 A clr $end +$var wire 1 5 we_reg_in $end +$var wire 1 6 we_mem_in $end +$var wire 1 7 mem_to_reg_in $end +$var wire 1 8 alu_src_in $end +$var wire 1 9 branch_in $end +$var wire 4 : alu_op_in [3:0] $end +$var reg 1 } we_reg_out $end +$var reg 1 ~ we_mem_out $end +$var reg 1 !! mem_to_reg_out $end +$var reg 1 "! alu_src_out $end +$var reg 1 #! branch_out $end +$var reg 4 $! alu_op_out [3:0] $end +$var wire 32 , pc_in [31:0] $end +$var wire 32 - pc4_in [31:0] $end +$var wire 32 3 regA_in [31:0] $end +$var wire 32 4 regB_in [31:0] $end +$var wire 32 2 imm_in [31:0] $end +$var wire 5 / rs1_in [4:0] $end +$var wire 5 0 rs2_in [4:0] $end +$var wire 5 1 rd_in [4:0] $end +$var reg 32 %! pc_out [31:0] $end +$var reg 32 &! pc4_out [31:0] $end +$var reg 32 '! regA_out [31:0] $end +$var reg 32 (! regB_out [31:0] $end +$var reg 32 )! imm_out [31:0] $end +$var reg 5 *! rs1_out [4:0] $end +$var reg 5 +! rs2_out [4:0] $end +$var reg 5 ,! rd_out [4:0] $end +$upscope $end +$scope module u_forwarding $end +$var wire 5 G ID_EX_Rs1 [4:0] $end +$var wire 5 H ID_EX_Rs2 [4:0] $end +$var wire 5 / IF_ID_Rs1 [4:0] $end +$var wire 5 0 IF_ID_Rs2 [4:0] $end +$var wire 5 Z EX_ME_Rd [4:0] $end +$var wire 1 [ EX_ME_RegWrite $end +$var wire 5 b ME_WB_Rd [4:0] $end +$var wire 1 c ME_WB_RegWrite $end +$var reg 2 -! EX_ForwardA [1:0] $end +$var reg 2 .! EX_ForwardB [1:0] $end +$var reg 2 /! ID_ForwardA [1:0] $end +$var reg 2 0! ID_ForwardB [1:0] $end +$upscope $end +$scope module u_alu $end +$var wire 32 R A [31:0] $end +$var wire 32 T B [31:0] $end +$var wire 4 O sel [3:0] $end +$var reg 32 1! R [31:0] $end +$var wire 1 V zero $end +$upscope $end +$scope module u_ex_me $end +$var wire 1 # clk $end +$var wire 1 $ rst $end +$var wire 1 J we_reg_in $end +$var wire 1 K we_mem_in $end +$var wire 1 L mem_to_reg_in $end +$var reg 1 2! we_reg_out $end +$var reg 1 3! we_mem_out $end +$var reg 1 4! mem_to_reg_out $end +$var wire 32 U alu_res_in [31:0] $end +$var wire 32 S regB_in [31:0] $end +$var wire 32 C pc4_in [31:0] $end +$var wire 5 I rd_in [4:0] $end +$var reg 32 5! alu_res_out [31:0] $end +$var reg 32 6! regB_out [31:0] $end +$var reg 32 7! pc4_out [31:0] $end +$var reg 5 8! rd_out [4:0] $end +$upscope $end +$scope module u_dmem $end +$var wire 1 # clk $end +$var wire 1 \ we $end +$var wire 32 W address [31:0] $end +$var wire 32 X write_data [31:0] $end +$var wire 32 ^ read_data [31:0] $end +$upscope $end +$scope module u_me_wb $end +$var wire 1 # clk $end +$var wire 1 $ rst $end +$var wire 1 [ we_reg_in $end +$var wire 1 ] mem_to_reg_in $end +$var reg 1 9! we_reg_out $end +$var reg 1 :! mem_to_reg_out $end +$var wire 32 W alu_res_in [31:0] $end +$var wire 32 ^ mem_data_in [31:0] $end +$var wire 32 Y pc4_in [31:0] $end +$var wire 5 Z rd_in [4:0] $end +$var reg 32 ;! alu_res_out [31:0] $end +$var reg 32 ! rd_out [4:0] $end +$upscope $end +$upscope $end +$upscope $end +$enddefinitions $end + +#0 +$dumpvars +0! +0!! +1" +0"! +0# +0#! +1$ +b0 $! +b0 % +b0 %! +b100 & +b0 &! +b10100010011 ' +b0 '! +b100 ( +b0 (! +1) +b0 )! +1* +b0 *! +0+ +b0 +! +b0 , +b0 ,! +b0 - +b0 -! +b0 . +b0 .! +b0 / +b0 /! +b0 0 +b0 0! +b0 1 +b0 1! +b0 2 +02! +b0 3 +03! +b0 4 +04! +05 +b0 5! +06 +b0 6! +07 +b0 7! +08 +b0 8! +09 +09! +b0 : +0:! +0; +b0 ;! +b0 < +b0 +b0 >! +b0 ? +b0 @ +0A +b0 B +b0 C +b0 D +b0 E +b0 F +b0 G +b0 H +b0 I +0J +0K +0L +0M +0N +b0 O +b0 P +b0 Q +b0 R +b0 S +b0 T +b0 U +1V +b0 W +b0 X +b0 Y +b0 Z +0[ +0\ +0] +bx ^ +b0 _ +b0 ` +b0 a +b0 b +0c +0d +b0 e +1f +b0 g +0h +b0 i +b0 j +b0 k +b0 l +b0 m +b0 n +b0 o +b0 p +0q +0r +0s +0t +b0 u +0v +1w +b0 x +1y +1z +0{ +0| +0} +0~ +$end + +#5000 +1! +1# +0w + +#10000 +0! +0# +1w + +#15000 +1! +1# +0w + +#20000 +0! +0" +0# +0$ +0f +1w + +#25000 +1! +1# +b100 % +b1000 & +b1100000000000110010011 ' +b1000 ( +b100 - +b10100010011 . +b1010 1 +15 +18 +bx ! +b0 ? +b1000 B +b1100 C +b100100 F +b100 H +b10 I +b100100 T +b100100 U +b11 W +bx X +b1000 Y +b11 Z +b100 a +b1010 b +1c +b10000 g +b1100 k +b10000 l +b10001010010001010000011 m +b11 n +b10 o +b0 p +1q +1s +1t +0w +b100 x + +#60000 +0! +0# +b0 3 +1w + +#65000 +1! +1!! +1# +b0 % +b1100 %! +b100 & +b10000 &! +b10100010011 ' +b100 ( +0) +b100 )! +0* +b1010 *! +b10000 , +b101 ,! +b10100 - +b1100101000000010110011 . +b101 / +b0 /! +b11 0 +b1 0! +b1 1 +b100 1! +b0 2 +bx 3 +b100100 5! +07 +b1100 7! +08 +b10 8! +b11 ;! +b10000 < +b0 = +b1000 =! +b1 > +b11 >! +bx ? +b11 @ +1A +b1100 B +b10000 C +b100 F +b1010 G +b101 I +1L +b100 T +b100 U +b100100 W +b1100 Y +b10 Z +b11 _ +b1000 a +b11 b +b11 e +1f +b0 g +b10000 k +b10100 l +b1100101000000010110011 m +b110011 n +b0 o +b0 p +1q +0s +0t +0w +b0 x +0y +0z +1| + +#70000 +0! +0# +b11 4 +1w + +#75000 +1! +0!! +0"! +1# +b0 %! +b0 &! +b0 (! +1) +b0 )! +1* +b0 *! +b0 +! +b0 ,! +b10 /! +b0 0! +b0 1! +14! +b100 5! +b10000 7! +b101 8! +b100100 ;! +b10 = +b1100 =! +b0 > +b10 >! +b100 ? +b11 @ +0A +b0 B +b0 C +b0 E +b0 F +b0 G +b0 H +b0 I +0J +0L +0M +b0 S +b0 T +b0 U +1V +b100 W +b10000 Y +b101 Z +1] +b100100 _ +b1100 a +b10 b +b100100 e +0f +0w +1y +1z +0| +0} + +#80000 +0! +0# +1w + +#85000 +1! +1# +b100 % +b10000 %! +b1000 & +b10100 &! +b1100000000000110010011 ' +bx '! +b1000 ( +b11 (! +b101 *! +b11 +! +b0 , +b1 ,! +b100 - +b1 -! +b10100010011 . +b0 / +b0 /! +b0 0 +b1010 1 +bx 1! +02! +b0 3 +b0 4 +04! +b0 5! +b0 6! +b0 7! +18 +b0 8! +1:! +b100 ;! +b0 < +b0 = +b10000 =! +b101 >! +b0 ? +b0 @ +b10000 B +b10100 C +bx D +b11 E +b101 G +b11 H +b1 I +1J +b1 P +bx R +b11 S +b11 T +bx U +xV +b0 W +b0 X +b0 Y +b0 Z +0[ +0] +b100 _ +b10000 a +b101 b +1d +bx e +b100 g +b0 k +b100 l +b10100010011 m +b10011 n +b0 o +b0 p +1q +1t +0w +1} + +#90000 +0! +0# +1w + +#95000 +1! +1"! +1# +b1000 % +b0 %! +b1100 & +b100 &! +b10010000000000000100010011 ' +b0 '! +b1100 ( +b0 (! +b0 *! +b0 +! +b100 , +b1010 ,! +b1000 - +b0 -! +b1100000000000110010011 . +b11 0 +b11 1 +b0 1! +b11 2 +12! +b11 4 +bx 5! +b11 6! +b10100 7! +b1 8! +09! +0:! +b0 ;! +b111 < +b0 =! +b0 >! +b11 @ +b0 B +b100 C +b0 D +b0 E +b0 G +b0 H +b1010 I +1M +b0 P +b0 R +b0 S +b0 T +b0 U +1V +bx W +b11 X +b10100 Y +b1 Z +1[ +b0 _ +b0 a +b0 b +0c +0d +b0 e +b1000 g +b100 k +b1000 l +b1100000000000110010011 m +b10011 n +b0 o +b0 p +0w +b11 x + +#100000 +0! +0# +1w + +#105000 +1! +1# +b1100 % +b100 %! +b10000 & +b1000 &! +b10001010010001010000011 ' +b10000 ( +b11 (! +b11 )! +b11 +! +b1000 , +b11 ,! +b1100 - +b10010000000000000100010011 . +b100 0 +b10 1 +b11 1! +b100100 2 +bx 4 +b0 5! +b0 6! +b100 7! +b1010 8! +19! +bx ;! +b101100 < +b10100 =! +b1 >! +bx @ +b100 B +b1000 C +b11 E +b11 F +b11 H +b11 I +b11 S +b11 T +b11 U +0V +b0 W +b0 X +b100 Y +b1010 Z +bx _ +b10100 a +b1 b +1c +bx e +b1100 g +b1000 k +b1100 l +b10010000000000000100010011 m +b10011 n +b0 o +b1 p +1q +1t +0w +b100100 x + +#110000 +0! +0# +1w + +#115000 +1! +1# +b10000 % +b1000 %! +b10100 & +b1100 &! +b1100101000000010110011 ' +b10100 ( +bx (! +b100100 )! +b100 +! +b1100 , +b10 ,! +b10000 - +b10001010010001010000011 . +b1010 / +b1 /! +b101 1 +b100100 1! +b100 2 +b11 5! +b11 6! +17 +b1000 7! +b11 8! +b0 ;! +b10000 < +b1 = +b100 =! +b1010 >! +b1000 B +b1100 C +bx E +b100100 F +b100 H +b10 I +bx S +b100100 T +b100100 U +b11 W +b11 X +b1000 Y +b11 Z +b0 _ +b100 a +b1010 b +b0 e +b10000 g +b1100 k +b10000 l +b10001010010001010000011 m +b11 n +b10 o +b0 p +1q +1s +1t +0w +b100 x + +#120000 +0! +0# +1w + +#125000 +1! +1!! +1# +b0 % +b1100 %! +b100 & +b10000 &! +b10100010011 ' +b100 ( +0) +b100 )! +0* +b1010 *! +b10000 , +b101 ,! +b10100 - +b1100101000000010110011 . +b101 / +b0 /! +b11 0 +b1 0! +b1 1 +b100 1! +b0 2 +bx 3 +b11 4 +b100100 5! +bx 6! +07 +b1100 7! +08 +b10 8! +b11 ;! +b10000 < +b0 = +b1000 =! +b1 > +b11 >! +bx ? +b11 @ +1A +b1100 B +b10000 C +b100 F +b1010 G +b101 I +1L +b100 T +b100 U +b100100 W +bx X +b1100 Y +b10 Z +b11 _ +b1000 a +b11 b +b11 e +1f +b0 g +b10000 k +b10100 l +b1100101000000010110011 m +b110011 n +b0 o +b0 p +1q +0s +0t +0w +b0 x +0y +0z +1| + +#130000 +0! +0# +1w + +#135000 +1! +0!! +0"! +1# +b0 %! +b0 &! +b0 (! +1) +b0 )! +1* +b0 *! +b0 +! +b0 ,! +b10 /! +b0 0! +b0 1! +14! +b100 5! +b10000 7! +b101 8! +b100100 ;! +b10 = +b1100 =! +b0 > +b10 >! +b100 ? +b11 @ +0A +b0 B +b0 C +b0 E +b0 F +b0 G +b0 H +b0 I +0J +0L +0M +b0 S +b0 T +b0 U +1V +b100 W +b10000 Y +b101 Z +1] +b100100 _ +b1100 a +b10 b +b100100 e +0f +0w +1y +1z +0| +0} + +#140000 +0! +0# +1w + +#145000 +1! +1# +b100 % +b10000 %! +b1000 & +b10100 &! +b1100000000000110010011 ' +bx '! +b1000 ( +b11 (! +b101 *! +b11 +! +b0 , +b1 ,! +b100 - +b1 -! +b10100010011 . +b0 / +b0 /! +b0 0 +b1010 1 +bx 1! +02! +b0 3 +b0 4 +04! +b0 5! +b0 6! +b0 7! +18 +b0 8! +1:! +b100 ;! +b0 < +b0 = +b10000 =! +b101 >! +b0 ? +b0 @ +b10000 B +b10100 C +bx D +b11 E +b101 G +b11 H +b1 I +1J +b1 P +bx R +b11 S +b11 T +bx U +xV +b0 W +b0 X +b0 Y +b0 Z +0[ +0] +b100 _ +b10000 a +b101 b +1d +bx e +b100 g +b0 k +b100 l +b10100010011 m +b10011 n +b0 o +b0 p +1q +1t +0w +1} + +#150000 +0! +0# +1w + +#155000 +1! +1"! +1# +b1000 % +b0 %! +b1100 & +b100 &! +b10010000000000000100010011 ' +b0 '! +b1100 ( +b0 (! +b0 *! +b0 +! +b100 , +b1010 ,! +b1000 - +b0 -! +b1100000000000110010011 . +b11 0 +b11 1 +b0 1! +b11 2 +12! +b11 4 +bx 5! +b11 6! +b10100 7! +b1 8! +09! +0:! +b0 ;! +b111 < +b0 =! +b0 >! +b11 @ +b0 B +b100 C +b0 D +b0 E +b0 G +b0 H +b1010 I +1M +b0 P +b0 R +b0 S +b0 T +b0 U +1V +bx W +b11 X +b10100 Y +b1 Z +1[ +b0 _ +b0 a +b0 b +0c +0d +b0 e +b1000 g +b100 k +b1000 l +b1100000000000110010011 m +b10011 n +b0 o +b0 p +0w +b11 x + +#160000 +0! +0# +1w + +#165000 +1! +1# +b1100 % +b100 %! +b10000 & +b1000 &! +b10001010010001010000011 ' +b10000 ( +b11 (! +b11 )! +b11 +! +b1000 , +b11 ,! +b1100 - +b10010000000000000100010011 . +b100 0 +b10 1 +b11 1! +b100100 2 +bx 4 +b0 5! +b0 6! +b100 7! +b1010 8! +19! +bx ;! +b101100 < +b10100 =! +b1 >! +bx @ +b100 B +b1000 C +b11 E +b11 F +b11 H +b11 I +b11 S +b11 T +b11 U +0V +b0 W +b0 X +b100 Y +b1010 Z +bx _ +b10100 a +b1 b +1c +bx e +b1100 g +b1000 k +b1100 l +b10010000000000000100010011 m +b10011 n +b0 o +b1 p +1q +1t +0w +b100100 x + +#170000 +0! +0# +1w + +#175000 +1! +1# +b10000 % +b1000 %! +b10100 & +b1100 &! +b1100101000000010110011 ' +b10100 ( +bx (! +b100100 )! +b100 +! +b1100 , +b10 ,! +b10000 - +b10001010010001010000011 . +b1010 / +b1 /! +b101 1 +b100100 1! +b100 2 +b11 5! +b11 6! +17 +b1000 7! +b11 8! +b0 ;! +b10000 < +b1 = +b100 =! +b1010 >! +b1000 B +b1100 C +bx E +b100100 F +b100 H +b10 I +bx S +b100100 T +b100100 U +b11 W +b11 X +b1000 Y +b11 Z +b0 _ +b100 a +b1010 b +b0 e +b10000 g +b1100 k +b10000 l +b10001010010001010000011 m +b11 n +b10 o +b0 p +1q +1s +1t +0w +b100 x + +#180000 +0! +0# +1w + +#185000 +1! +1!! +1# +b0 % +b1100 %! +b100 & +b10000 &! +b10100010011 ' +b100 ( +0) +b100 )! +0* +b1010 *! +b10000 , +b101 ,! +b10100 - +b1100101000000010110011 . +b101 / +b0 /! +b11 0 +b1 0! +b1 1 +b100 1! +b0 2 +bx 3 +b11 4 +b100100 5! +bx 6! +07 +b1100 7! +08 +b10 8! +b11 ;! +b10000 < +b0 = +b1000 =! +b1 > +b11 >! +bx ? +b11 @ +1A +b1100 B +b10000 C +b100 F +b1010 G +b101 I +1L +b100 T +b100 U +b100100 W +bx X +b1100 Y +b10 Z +b11 _ +b1000 a +b11 b +b11 e +1f +b0 g +b10000 k +b10100 l +b1100101000000010110011 m +b110011 n +b0 o +b0 p +1q +0s +0t +0w +b0 x +0y +0z +1| + +#190000 +0! +0# +1w + +#195000 +1! +0!! +0"! +1# +b0 %! +b0 &! +b0 (! +1) +b0 )! +1* +b0 *! +b0 +! +b0 ,! +b10 /! +b0 0! +b0 1! +14! +b100 5! +b10000 7! +b101 8! +b100100 ;! +b10 = +b1100 =! +b0 > +b10 >! +b100 ? +b11 @ +0A +b0 B +b0 C +b0 E +b0 F +b0 G +b0 H +b0 I +0J +0L +0M +b0 S +b0 T +b0 U +1V +b100 W +b10000 Y +b101 Z +1] +b100100 _ +b1100 a +b10 b +b100100 e +0f +0w +1y +1z +0| +0} + +#200000 +0! +0# +1w + +#205000 +1! +1# +b100 % +b10000 %! +b1000 & +b10100 &! +b1100000000000110010011 ' +bx '! +b1000 ( +b11 (! +b101 *! +b11 +! +b0 , +b1 ,! +b100 - +b1 -! +b10100010011 . +b0 / +b0 /! +b0 0 +b1010 1 +bx 1! +02! +b0 3 +b0 4 +04! +b0 5! +b0 6! +b0 7! +18 +b0 8! +1:! +b100 ;! +b0 < +b0 = +b10000 =! +b101 >! +b0 ? +b0 @ +b10000 B +b10100 C +bx D +b11 E +b101 G +b11 H +b1 I +1J +b1 P +bx R +b11 S +b11 T +bx U +xV +b0 W +b0 X +b0 Y +b0 Z +0[ +0] +b100 _ +b10000 a +b101 b +1d +bx e +b100 g +b0 k +b100 l +b10100010011 m +b10011 n +b0 o +b0 p +1q +1t +0w +1} + +#210000 +0! +0# +1w + +#215000 +1! +1"! +1# +b1000 % +b0 %! +b1100 & +b100 &! +b10010000000000000100010011 ' +b0 '! +b1100 ( +b0 (! +b0 *! +b0 +! +b100 , +b1010 ,! +b1000 - +b0 -! +b1100000000000110010011 . +b11 0 +b11 1 +b0 1! +b11 2 +12! +b11 4 +bx 5! +b11 6! +b10100 7! +b1 8! +09! +0:! +b0 ;! +b111 < +b0 =! +b0 >! +b11 @ +b0 B +b100 C +b0 D +b0 E +b0 G +b0 H +b1010 I +1M +b0 P +b0 R +b0 S +b0 T +b0 U +1V +bx W +b11 X +b10100 Y +b1 Z +1[ +b0 _ +b0 a +b0 b +0c +0d +b0 e +b1000 g +b100 k +b1000 l +b1100000000000110010011 m +b10011 n +b0 o +b0 p +0w +b11 x + +#220000 +0! +0# +1w + +#225000 +1! +1# +b1100 % +b100 %! +b10000 & +b1000 &! +b10001010010001010000011 ' +b10000 ( +b11 (! +b11 )! +b11 +! +b1000 , +b11 ,! +b1100 - +b10010000000000000100010011 . +b100 0 +b10 1 +b11 1! +b100100 2 +bx 4 +b0 5! +b0 6! +b100 7! +b1010 8! +19! +bx ;! +b101100 < +b10100 =! +b1 >! +bx @ +b100 B +b1000 C +b11 E +b11 F +b11 H +b11 I +b11 S +b11 T +b11 U +0V +b0 W +b0 X +b100 Y +b1010 Z +bx _ +b10100 a +b1 b +1c +bx e +b1100 g +b1000 k +b1100 l +b10010000000000000100010011 m +b10011 n +b0 o +b1 p +1q +1t +0w +b100100 x + +#230000 +0! +0# +1w + +#235000 +1! +1# +b10000 % +b1000 %! +b10100 & +b1100 &! +b1100101000000010110011 ' +b10100 ( +bx (! +b100100 )! +b100 +! +b1100 , +b10 ,! +b10000 - +b10001010010001010000011 . +b1010 / +b1 /! +b101 1 +b100100 1! +b100 2 +b11 5! +b11 6! +17 +b1000 7! +b11 8! +b0 ;! +b10000 < +b1 = +b100 =! +b1010 >! +b1000 B +b1100 C +bx E +b100100 F +b100 H +b10 I +bx S +b100100 T +b100100 U +b11 W +b11 X +b1000 Y +b11 Z +b0 _ +b100 a +b1010 b +b0 e +b10000 g +b1100 k +b10000 l +b10001010010001010000011 m +b11 n +b10 o +b0 p +1q +1s +1t +0w +b100 x + +#240000 +0! +0# +1w + +#245000 +1! +1!! +1# +b0 % +b1100 %! +b100 & +b10000 &! +b10100010011 ' +b100 ( +0) +b100 )! +0* +b1010 *! +b10000 , +b101 ,! +b10100 - +b1100101000000010110011 . +b101 / +b0 /! +b11 0 +b1 0! +b1 1 +b100 1! +b0 2 +bx 3 +b11 4 +b100100 5! +bx 6! +07 +b1100 7! +08 +b10 8! +b11 ;! +b10000 < +b0 = +b1000 =! +b1 > +b11 >! +bx ? +b11 @ +1A +b1100 B +b10000 C +b100 F +b1010 G +b101 I +1L +b100 T +b100 U +b100100 W +bx X +b1100 Y +b10 Z +b11 _ +b1000 a +b11 b +b11 e +1f +b0 g +b10000 k +b10100 l +b1100101000000010110011 m +b110011 n +b0 o +b0 p +1q +0s +0t +0w +b0 x +0y +0z +1| + +#250000 +0! +0# +1w + +#255000 +1! +0!! +0"! +1# +b0 %! +b0 &! +b0 (! +1) +b0 )! +1* +b0 *! +b0 +! +b0 ,! +b10 /! +b0 0! +b0 1! +14! +b100 5! +b10000 7! +b101 8! +b100100 ;! +b10 = +b1100 =! +b0 > +b10 >! +b100 ? +b11 @ +0A +b0 B +b0 C +b0 E +b0 F +b0 G +b0 H +b0 I +0J +0L +0M +b0 S +b0 T +b0 U +1V +b100 W +b10000 Y +b101 Z +1] +b100100 _ +b1100 a +b10 b +b100100 e +0f +0w +1y +1z +0| +0} + +#260000 +0! +0# +1w + +#265000 +1! +1# +b100 % +b10000 %! +b1000 & +b10100 &! +b1100000000000110010011 ' +bx '! +b1000 ( +b11 (! +b101 *! +b11 +! +b0 , +b1 ,! +b100 - +b1 -! +b10100010011 . +b0 / +b0 /! +b0 0 +b1010 1 +bx 1! +02! +b0 3 +b0 4 +04! +b0 5! +b0 6! +b0 7! +18 +b0 8! +1:! +b100 ;! +b0 < +b0 = +b10000 =! +b101 >! +b0 ? +b0 @ +b10000 B +b10100 C +bx D +b11 E +b101 G +b11 H +b1 I +1J +b1 P +bx R +b11 S +b11 T +bx U +xV +b0 W +b0 X +b0 Y +b0 Z +0[ +0] +b100 _ +b10000 a +b101 b +1d +bx e +b100 g +b0 k +b100 l +b10100010011 m +b10011 n +b0 o +b0 p +1q +1t +0w +1} + +#270000 +0! +0# +1w + +#275000 +1! +1"! +1# +b1000 % +b0 %! +b1100 & +b100 &! +b10010000000000000100010011 ' +b0 '! +b1100 ( +b0 (! +b0 *! +b0 +! +b100 , +b1010 ,! +b1000 - +b0 -! +b1100000000000110010011 . +b11 0 +b11 1 +b0 1! +b11 2 +12! +b11 4 +bx 5! +b11 6! +b10100 7! +b1 8! +09! +0:! +b0 ;! +b111 < +b0 =! +b0 >! +b11 @ +b0 B +b100 C +b0 D +b0 E +b0 G +b0 H +b1010 I +1M +b0 P +b0 R +b0 S +b0 T +b0 U +1V +bx W +b11 X +b10100 Y +b1 Z +1[ +b0 _ +b0 a +b0 b +0c +0d +b0 e +b1000 g +b100 k +b1000 l +b1100000000000110010011 m +b10011 n +b0 o +b0 p +0w +b11 x + +#280000 +0! +0# +1w + +#285000 +1! +1# +b1100 % +b100 %! +b10000 & +b1000 &! +b10001010010001010000011 ' +b10000 ( +b11 (! +b11 )! +b11 +! +b1000 , +b11 ,! +b1100 - +b10010000000000000100010011 . +b100 0 +b10 1 +b11 1! +b100100 2 +bx 4 +b0 5! +b0 6! +b100 7! +b1010 8! +19! +bx ;! +b101100 < +b10100 =! +b1 >! +bx @ +b100 B +b1000 C +b11 E +b11 F +b11 H +b11 I +b11 S +b11 T +b11 U +0V +b0 W +b0 X +b100 Y +b1010 Z +bx _ +b10100 a +b1 b +1c +bx e +b1100 g +b1000 k +b1100 l +b10010000000000000100010011 m +b10011 n +b0 o +b1 p +1q +1t +0w +b100100 x + +#290000 +0! +0# +1w + +#295000 +1! +1# +b10000 % +b1000 %! +b10100 & +b1100 &! +b1100101000000010110011 ' +b10100 ( +bx (! +b100100 )! +b100 +! +b1100 , +b10 ,! +b10000 - +b10001010010001010000011 . +b1010 / +b1 /! +b101 1 +b100100 1! +b100 2 +b11 5! +b11 6! +17 +b1000 7! +b11 8! +b0 ;! +b10000 < +b1 = +b100 =! +b1010 >! +b1000 B +b1100 C +bx E +b100100 F +b100 H +b10 I +bx S +b100100 T +b100100 U +b11 W +b11 X +b1000 Y +b11 Z +b0 _ +b100 a +b1010 b +b0 e +b10000 g +b1100 k +b10000 l +b10001010010001010000011 m +b11 n +b10 o +b0 p +1q +1s +1t +0w +b100 x + +#300000 +0! +0# +1w + +#305000 +1! +1!! +1# +b0 % +b1100 %! +b100 & +b10000 &! +b10100010011 ' +b100 ( +0) +b100 )! +0* +b1010 *! +b10000 , +b101 ,! +b10100 - +b1100101000000010110011 . +b101 / +b0 /! +b11 0 +b1 0! +b1 1 +b100 1! +b0 2 +bx 3 +b11 4 +b100100 5! +bx 6! +07 +b1100 7! +08 +b10 8! +b11 ;! +b10000 < +b0 = +b1000 =! +b1 > +b11 >! +bx ? +b11 @ +1A +b1100 B +b10000 C +b100 F +b1010 G +b101 I +1L +b100 T +b100 U +b100100 W +bx X +b1100 Y +b10 Z +b11 _ +b1000 a +b11 b +b11 e +1f +b0 g +b10000 k +b10100 l +b1100101000000010110011 m +b110011 n +b0 o +b0 p +1q +0s +0t +0w +b0 x +0y +0z +1| + +#310000 +0! +0# +1w + +#315000 +1! +0!! +0"! +1# +b0 %! +b0 &! +b0 (! +1) +b0 )! +1* +b0 *! +b0 +! +b0 ,! +b10 /! +b0 0! +b0 1! +14! +b100 5! +b10000 7! +b101 8! +b100100 ;! +b10 = +b1100 =! +b0 > +b10 >! +b100 ? +b11 @ +0A +b0 B +b0 C +b0 E +b0 F +b0 G +b0 H +b0 I +0J +0L +0M +b0 S +b0 T +b0 U +1V +b100 W +b10000 Y +b101 Z +1] +b100100 _ +b1100 a +b10 b +b100100 e +0f +0w +1y +1z +0| +0} + +#320000 +0! +0# +1w + +#325000 +1! +1# +b100 % +b10000 %! +b1000 & +b10100 &! +b1100000000000110010011 ' +bx '! +b1000 ( +b11 (! +b101 *! +b11 +! +b0 , +b1 ,! +b100 - +b1 -! +b10100010011 . +b0 / +b0 /! +b0 0 +b1010 1 +bx 1! +02! +b0 3 +b0 4 +04! +b0 5! +b0 6! +b0 7! +18 +b0 8! +1:! +b100 ;! +b0 < +b0 = +b10000 =! +b101 >! +b0 ? +b0 @ +b10000 B +b10100 C +bx D +b11 E +b101 G +b11 H +b1 I +1J +b1 P +bx R +b11 S +b11 T +bx U +xV +b0 W +b0 X +b0 Y +b0 Z +0[ +0] +b100 _ +b10000 a +b101 b +1d +bx e +b100 g +b0 k +b100 l +b10100010011 m +b10011 n +b0 o +b0 p +1q +1t +0w +1} + +#330000 +0! +0# +1w + +#335000 +1! +1"! +1# +b1000 % +b0 %! +b1100 & +b100 &! +b10010000000000000100010011 ' +b0 '! +b1100 ( +b0 (! +b0 *! +b0 +! +b100 , +b1010 ,! +b1000 - +b0 -! +b1100000000000110010011 . +b11 0 +b11 1 +b0 1! +b11 2 +12! +b11 4 +bx 5! +b11 6! +b10100 7! +b1 8! +09! +0:! +b0 ;! +b111 < +b0 =! +b0 >! +b11 @ +b0 B +b100 C +b0 D +b0 E +b0 G +b0 H +b1010 I +1M +b0 P +b0 R +b0 S +b0 T +b0 U +1V +bx W +b11 X +b10100 Y +b1 Z +1[ +b0 _ +b0 a +b0 b +0c +0d +b0 e +b1000 g +b100 k +b1000 l +b1100000000000110010011 m +b10011 n +b0 o +b0 p +0w +b11 x + +#340000 +0! +0# +1w + +#345000 +1! +1# +b1100 % +b100 %! +b10000 & +b1000 &! +b10001010010001010000011 ' +b10000 ( +b11 (! +b11 )! +b11 +! +b1000 , +b11 ,! +b1100 - +b10010000000000000100010011 . +b100 0 +b10 1 +b11 1! +b100100 2 +bx 4 +b0 5! +b0 6! +b100 7! +b1010 8! +19! +bx ;! +b101100 < +b10100 =! +b1 >! +bx @ +b100 B +b1000 C +b11 E +b11 F +b11 H +b11 I +b11 S +b11 T +b11 U +0V +b0 W +b0 X +b100 Y +b1010 Z +bx _ +b10100 a +b1 b +1c +bx e +b1100 g +b1000 k +b1100 l +b10010000000000000100010011 m +b10011 n +b0 o +b1 p +1q +1t +0w +b100100 x + +#350000 +0! +0# +1w + +#355000 +1! +1# +b10000 % +b1000 %! +b10100 & +b1100 &! +b1100101000000010110011 ' +b10100 ( +bx (! +b100100 )! +b100 +! +b1100 , +b10 ,! +b10000 - +b10001010010001010000011 . +b1010 / +b1 /! +b101 1 +b100100 1! +b100 2 +b11 5! +b11 6! +17 +b1000 7! +b11 8! +b0 ;! +b10000 < +b1 = +b100 =! +b1010 >! +b1000 B +b1100 C +bx E +b100100 F +b100 H +b10 I +bx S +b100100 T +b100100 U +b11 W +b11 X +b1000 Y +b11 Z +b0 _ +b100 a +b1010 b +b0 e +b10000 g +b1100 k +b10000 l +b10001010010001010000011 m +b11 n +b10 o +b0 p +1q +1s +1t +0w +b100 x + +#360000 +0! +0# +1w + +#365000 +1! +1!! +1# +b0 % +b1100 %! +b100 & +b10000 &! +b10100010011 ' +b100 ( +0) +b100 )! +0* +b1010 *! +b10000 , +b101 ,! +b10100 - +b1100101000000010110011 . +b101 / +b0 /! +b11 0 +b1 0! +b1 1 +b100 1! +b0 2 +bx 3 +b11 4 +b100100 5! +bx 6! +07 +b1100 7! +08 +b10 8! +b11 ;! +b10000 < +b0 = +b1000 =! +b1 > +b11 >! +bx ? +b11 @ +1A +b1100 B +b10000 C +b100 F +b1010 G +b101 I +1L +b100 T +b100 U +b100100 W +bx X +b1100 Y +b10 Z +b11 _ +b1000 a +b11 b +b11 e +1f +b0 g +b10000 k +b10100 l +b1100101000000010110011 m +b110011 n +b0 o +b0 p +1q +0s +0t +0w +b0 x +0y +0z +1| + +#370000 +0! +0# +1w + +#375000 +1! +0!! +0"! +1# +b0 %! +b0 &! +b0 (! +1) +b0 )! +1* +b0 *! +b0 +! +b0 ,! +b10 /! +b0 0! +b0 1! +14! +b100 5! +b10000 7! +b101 8! +b100100 ;! +b10 = +b1100 =! +b0 > +b10 >! +b100 ? +b11 @ +0A +b0 B +b0 C +b0 E +b0 F +b0 G +b0 H +b0 I +0J +0L +0M +b0 S +b0 T +b0 U +1V +b100 W +b10000 Y +b101 Z +1] +b100100 _ +b1100 a +b10 b +b100100 e +0f +0w +1y +1z +0| +0} + +#380000 +0! +0# +1w + +#385000 +1! +1# +b100 % +b10000 %! +b1000 & +b10100 &! +b1100000000000110010011 ' +bx '! +b1000 ( +b11 (! +b101 *! +b11 +! +b0 , +b1 ,! +b100 - +b1 -! +b10100010011 . +b0 / +b0 /! +b0 0 +b1010 1 +bx 1! +02! +b0 3 +b0 4 +04! +b0 5! +b0 6! +b0 7! +18 +b0 8! +1:! +b100 ;! +b0 < +b0 = +b10000 =! +b101 >! +b0 ? +b0 @ +b10000 B +b10100 C +bx D +b11 E +b101 G +b11 H +b1 I +1J +b1 P +bx R +b11 S +b11 T +bx U +xV +b0 W +b0 X +b0 Y +b0 Z +0[ +0] +b100 _ +b10000 a +b101 b +1d +bx e +b100 g +b0 k +b100 l +b10100010011 m +b10011 n +b0 o +b0 p +1q +1t +0w +1} + +#390000 +0! +0# +1w + +#395000 +1! +1"! +1# +b1000 % +b0 %! +b1100 & +b100 &! +b10010000000000000100010011 ' +b0 '! +b1100 ( +b0 (! +b0 *! +b0 +! +b100 , +b1010 ,! +b1000 - +b0 -! +b1100000000000110010011 . +b11 0 +b11 1 +b0 1! +b11 2 +12! +b11 4 +bx 5! +b11 6! +b10100 7! +b1 8! +09! +0:! +b0 ;! +b111 < +b0 =! +b0 >! +b11 @ +b0 B +b100 C +b0 D +b0 E +b0 G +b0 H +b1010 I +1M +b0 P +b0 R +b0 S +b0 T +b0 U +1V +bx W +b11 X +b10100 Y +b1 Z +1[ +b0 _ +b0 a +b0 b +0c +0d +b0 e +b1000 g +b100 k +b1000 l +b1100000000000110010011 m +b10011 n +b0 o +b0 p +0w +b11 x + +#400000 +0! +0# +1w + +#405000 +1! +1# +b1100 % +b100 %! +b10000 & +b1000 &! +b10001010010001010000011 ' +b10000 ( +b11 (! +b11 )! +b11 +! +b1000 , +b11 ,! +b1100 - +b10010000000000000100010011 . +b100 0 +b10 1 +b11 1! +b100100 2 +bx 4 +b0 5! +b0 6! +b100 7! +b1010 8! +19! +bx ;! +b101100 < +b10100 =! +b1 >! +bx @ +b100 B +b1000 C +b11 E +b11 F +b11 H +b11 I +b11 S +b11 T +b11 U +0V +b0 W +b0 X +b100 Y +b1010 Z +bx _ +b10100 a +b1 b +1c +bx e +b1100 g +b1000 k +b1100 l +b10010000000000000100010011 m +b10011 n +b0 o +b1 p +1q +1t +0w +b100100 x + +#410000 +0! +0# +1w + +#415000 +1! +1# +b10000 % +b1000 %! +b10100 & +b1100 &! +b1100101000000010110011 ' +b10100 ( +bx (! +b100100 )! +b100 +! +b1100 , +b10 ,! +b10000 - +b10001010010001010000011 . +b1010 / +b1 /! +b101 1 +b100100 1! +b100 2 +b11 5! +b11 6! +17 +b1000 7! +b11 8! +b0 ;! +b10000 < +b1 = +b100 =! +b1010 >! +b1000 B +b1100 C +bx E +b100100 F +b100 H +b10 I +bx S +b100100 T +b100100 U +b11 W +b11 X +b1000 Y +b11 Z +b0 _ +b100 a +b1010 b +b0 e +b10000 g +b1100 k +b10000 l +b10001010010001010000011 m +b11 n +b10 o +b0 p +1q +1s +1t +0w +b100 x + +#420000 +0! +0# +1w + +#425000 +1! +1!! +1# +b0 % +b1100 %! +b100 & +b10000 &! +b10100010011 ' +b100 ( +0) +b100 )! +0* +b1010 *! +b10000 , +b101 ,! +b10100 - +b1100101000000010110011 . +b101 / +b0 /! +b11 0 +b1 0! +b1 1 +b100 1! +b0 2 +bx 3 +b11 4 +b100100 5! +bx 6! +07 +b1100 7! +08 +b10 8! +b11 ;! +b10000 < +b0 = +b1000 =! +b1 > +b11 >! +bx ? +b11 @ +1A +b1100 B +b10000 C +b100 F +b1010 G +b101 I +1L +b100 T +b100 U +b100100 W +bx X +b1100 Y +b10 Z +b11 _ +b1000 a +b11 b +b11 e +1f +b0 g +b10000 k +b10100 l +b1100101000000010110011 m +b110011 n +b0 o +b0 p +1q +0s +0t +0w +b0 x +0y +0z +1| + +#430000 +0! +0# +1w + +#435000 +1! +0!! +0"! +1# +b0 %! +b0 &! +b0 (! +1) +b0 )! +1* +b0 *! +b0 +! +b0 ,! +b10 /! +b0 0! +b0 1! +14! +b100 5! +b10000 7! +b101 8! +b100100 ;! +b10 = +b1100 =! +b0 > +b10 >! +b100 ? +b11 @ +0A +b0 B +b0 C +b0 E +b0 F +b0 G +b0 H +b0 I +0J +0L +0M +b0 S +b0 T +b0 U +1V +b100 W +b10000 Y +b101 Z +1] +b100100 _ +b1100 a +b10 b +b100100 e +0f +0w +1y +1z +0| +0} + +#440000 +0! +0# +1w + +#445000 +1! +1# +b100 % +b10000 %! +b1000 & +b10100 &! +b1100000000000110010011 ' +bx '! +b1000 ( +b11 (! +b101 *! +b11 +! +b0 , +b1 ,! +b100 - +b1 -! +b10100010011 . +b0 / +b0 /! +b0 0 +b1010 1 +bx 1! +02! +b0 3 +b0 4 +04! +b0 5! +b0 6! +b0 7! +18 +b0 8! +1:! +b100 ;! +b0 < +b0 = +b10000 =! +b101 >! +b0 ? +b0 @ +b10000 B +b10100 C +bx D +b11 E +b101 G +b11 H +b1 I +1J +b1 P +bx R +b11 S +b11 T +bx U +xV +b0 W +b0 X +b0 Y +b0 Z +0[ +0] +b100 _ +b10000 a +b101 b +1d +bx e +b100 g +b0 k +b100 l +b10100010011 m +b10011 n +b0 o +b0 p +1q +1t +0w +1} + +#450000 +0! +0# +1w + +#455000 +1! +1"! +1# +b1000 % +b0 %! +b1100 & +b100 &! +b10010000000000000100010011 ' +b0 '! +b1100 ( +b0 (! +b0 *! +b0 +! +b100 , +b1010 ,! +b1000 - +b0 -! +b1100000000000110010011 . +b11 0 +b11 1 +b0 1! +b11 2 +12! +b11 4 +bx 5! +b11 6! +b10100 7! +b1 8! +09! +0:! +b0 ;! +b111 < +b0 =! +b0 >! +b11 @ +b0 B +b100 C +b0 D +b0 E +b0 G +b0 H +b1010 I +1M +b0 P +b0 R +b0 S +b0 T +b0 U +1V +bx W +b11 X +b10100 Y +b1 Z +1[ +b0 _ +b0 a +b0 b +0c +0d +b0 e +b1000 g +b100 k +b1000 l +b1100000000000110010011 m +b10011 n +b0 o +b0 p +0w +b11 x + +#460000 +0! +0# +1w + +#465000 +1! +1# +b1100 % +b100 %! +b10000 & +b1000 &! +b10001010010001010000011 ' +b10000 ( +b11 (! +b11 )! +b11 +! +b1000 , +b11 ,! +b1100 - +b10010000000000000100010011 . +b100 0 +b10 1 +b11 1! +b100100 2 +bx 4 +b0 5! +b0 6! +b100 7! +b1010 8! +19! +bx ;! +b101100 < +b10100 =! +b1 >! +bx @ +b100 B +b1000 C +b11 E +b11 F +b11 H +b11 I +b11 S +b11 T +b11 U +0V +b0 W +b0 X +b100 Y +b1010 Z +bx _ +b10100 a +b1 b +1c +bx e +b1100 g +b1000 k +b1100 l +b10010000000000000100010011 m +b10011 n +b0 o +b1 p +1q +1t +0w +b100100 x + +#470000 +0! +0# +1w + +#475000 +1! +1# +b10000 % +b1000 %! +b10100 & +b1100 &! +b1100101000000010110011 ' +b10100 ( +bx (! +b100100 )! +b100 +! +b1100 , +b10 ,! +b10000 - +b10001010010001010000011 . +b1010 / +b1 /! +b101 1 +b100100 1! +b100 2 +b11 5! +b11 6! +17 +b1000 7! +b11 8! +b0 ;! +b10000 < +b1 = +b100 =! +b1010 >! +b1000 B +b1100 C +bx E +b100100 F +b100 H +b10 I +bx S +b100100 T +b100100 U +b11 W +b11 X +b1000 Y +b11 Z +b0 _ +b100 a +b1010 b +b0 e +b10000 g +b1100 k +b10000 l +b10001010010001010000011 m +b11 n +b10 o +b0 p +1q +1s +1t +0w +b100 x + +#480000 +0! +0# +1w + +#485000 +1! +1!! +1# +b0 % +b1100 %! +b100 & +b10000 &! +b10100010011 ' +b100 ( +0) +b100 )! +0* +b1010 *! +b10000 , +b101 ,! +b10100 - +b1100101000000010110011 . +b101 / +b0 /! +b11 0 +b1 0! +b1 1 +b100 1! +b0 2 +bx 3 +b11 4 +b100100 5! +bx 6! +07 +b1100 7! +08 +b10 8! +b11 ;! +b10000 < +b0 = +b1000 =! +b1 > +b11 >! +bx ? +b11 @ +1A +b1100 B +b10000 C +b100 F +b1010 G +b101 I +1L +b100 T +b100 U +b100100 W +bx X +b1100 Y +b10 Z +b11 _ +b1000 a +b11 b +b11 e +1f +b0 g +b10000 k +b10100 l +b1100101000000010110011 m +b110011 n +b0 o +b0 p +1q +0s +0t +0w +b0 x +0y +0z +1| + +#490000 +0! +0# +1w + +#495000 +1! +0!! +0"! +1# +b0 %! +b0 &! +b0 (! +1) +b0 )! +1* +b0 *! +b0 +! +b0 ,! +b10 /! +b0 0! +b0 1! +14! +b100 5! +b10000 7! +b101 8! +b100100 ;! +b10 = +b1100 =! +b0 > +b10 >! +b100 ? +b11 @ +0A +b0 B +b0 C +b0 E +b0 F +b0 G +b0 H +b0 I +0J +0L +0M +b0 S +b0 T +b0 U +1V +b100 W +b10000 Y +b101 Z +1] +b100100 _ +b1100 a +b10 b +b100100 e +0f +0w +1y +1z +0| +0} + +#500000 +0! +0# +1w + +#505000 +1! +1# +b100 % +b10000 %! +b1000 & +b10100 &! +b1100000000000110010011 ' +bx '! +b1000 ( +b11 (! +b101 *! +b11 +! +b0 , +b1 ,! +b100 - +b1 -! +b10100010011 . +b0 / +b0 /! +b0 0 +b1010 1 +bx 1! +02! +b0 3 +b0 4 +04! +b0 5! +b0 6! +b0 7! +18 +b0 8! +1:! +b100 ;! +b0 < +b0 = +b10000 =! +b101 >! +b0 ? +b0 @ +b10000 B +b10100 C +bx D +b11 E +b101 G +b11 H +b1 I +1J +b1 P +bx R +b11 S +b11 T +bx U +xV +b0 W +b0 X +b0 Y +b0 Z +0[ +0] +b100 _ +b10000 a +b101 b +1d +bx e +b100 g +b0 k +b100 l +b10100010011 m +b10011 n +b0 o +b0 p +1q +1t +0w +1} + +#510000 +0! +0# +1w + +#515000 +1! +1"! +1# +b1000 % +b0 %! +b1100 & +b100 &! +b10010000000000000100010011 ' +b0 '! +b1100 ( +b0 (! +b0 *! +b0 +! +b100 , +b1010 ,! +b1000 - +b0 -! +b1100000000000110010011 . +b11 0 +b11 1 +b0 1! +b11 2 +12! +b11 4 +bx 5! +b11 6! +b10100 7! +b1 8! +09! +0:! +b0 ;! +b111 < +b0 =! +b0 >! +b11 @ +b0 B +b100 C +b0 D +b0 E +b0 G +b0 H +b1010 I +1M +b0 P +b0 R +b0 S +b0 T +b0 U +1V +bx W +b11 X +b10100 Y +b1 Z +1[ +b0 _ +b0 a +b0 b +0c +0d +b0 e +b1000 g +b100 k +b1000 l +b1100000000000110010011 m +b10011 n +b0 o +b0 p +0w +b11 x + +#520000 +0! +0# +1w + +#525000 +1! +1# +b1100 % +b100 %! +b10000 & +b1000 &! +b10001010010001010000011 ' +b10000 ( +b11 (! +b11 )! +b11 +! +b1000 , +b11 ,! +b1100 - +b10010000000000000100010011 . +b100 0 +b10 1 +b11 1! +b100100 2 +bx 4 +b0 5! +b0 6! +b100 7! +b1010 8! +19! +bx ;! +b101100 < +b10100 =! +b1 >! +bx @ +b100 B +b1000 C +b11 E +b11 F +b11 H +b11 I +b11 S +b11 T +b11 U +0V +b0 W +b0 X +b100 Y +b1010 Z +bx _ +b10100 a +b1 b +1c +bx e +b1100 g +b1000 k +b1100 l +b10010000000000000100010011 m +b10011 n +b0 o +b1 p +1q +1t +0w +b100100 x + +#530000 +0! +0# +1w + +#535000 +1! +1# +b10000 % +b1000 %! +b10100 & +b1100 &! +b1100101000000010110011 ' +b10100 ( +bx (! +b100100 )! +b100 +! +b1100 , +b10 ,! +b10000 - +b10001010010001010000011 . +b1010 / +b1 /! +b101 1 +b100100 1! +b100 2 +b11 5! +b11 6! +17 +b1000 7! +b11 8! +b0 ;! +b10000 < +b1 = +b100 =! +b1010 >! +b1000 B +b1100 C +bx E +b100100 F +b100 H +b10 I +bx S +b100100 T +b100100 U +b11 W +b11 X +b1000 Y +b11 Z +b0 _ +b100 a +b1010 b +b0 e +b10000 g +b1100 k +b10000 l +b10001010010001010000011 m +b11 n +b10 o +b0 p +1q +1s +1t +0w +b100 x + +#540000 +0! +0# +1w + +#545000 +1! +1!! +1# +b0 % +b1100 %! +b100 & +b10000 &! +b10100010011 ' +b100 ( +0) +b100 )! +0* +b1010 *! +b10000 , +b101 ,! +b10100 - +b1100101000000010110011 . +b101 / +b0 /! +b11 0 +b1 0! +b1 1 +b100 1! +b0 2 +bx 3 +b11 4 +b100100 5! +bx 6! +07 +b1100 7! +08 +b10 8! +b11 ;! +b10000 < +b0 = +b1000 =! +b1 > +b11 >! +bx ? +b11 @ +1A +b1100 B +b10000 C +b100 F +b1010 G +b101 I +1L +b100 T +b100 U +b100100 W +bx X +b1100 Y +b10 Z +b11 _ +b1000 a +b11 b +b11 e +1f +b0 g +b10000 k +b10100 l +b1100101000000010110011 m +b110011 n +b0 o +b0 p +1q +0s +0t +0w +b0 x +0y +0z +1| + +#550000 +0! +0# +1w + +#555000 +1! +0!! +0"! +1# +b0 %! +b0 &! +b0 (! +1) +b0 )! +1* +b0 *! +b0 +! +b0 ,! +b10 /! +b0 0! +b0 1! +14! +b100 5! +b10000 7! +b101 8! +b100100 ;! +b10 = +b1100 =! +b0 > +b10 >! +b100 ? +b11 @ +0A +b0 B +b0 C +b0 E +b0 F +b0 G +b0 H +b0 I +0J +0L +0M +b0 S +b0 T +b0 U +1V +b100 W +b10000 Y +b101 Z +1] +b100100 _ +b1100 a +b10 b +b100100 e +0f +0w +1y +1z +0| +0} + +#560000 +0! +0# +1w + +#565000 +1! +1# +b100 % +b10000 %! +b1000 & +b10100 &! +b1100000000000110010011 ' +bx '! +b1000 ( +b11 (! +b101 *! +b11 +! +b0 , +b1 ,! +b100 - +b1 -! +b10100010011 . +b0 / +b0 /! +b0 0 +b1010 1 +bx 1! +02! +b0 3 +b0 4 +04! +b0 5! +b0 6! +b0 7! +18 +b0 8! +1:! +b100 ;! +b0 < +b0 = +b10000 =! +b101 >! +b0 ? +b0 @ +b10000 B +b10100 C +bx D +b11 E +b101 G +b11 H +b1 I +1J +b1 P +bx R +b11 S +b11 T +bx U +xV +b0 W +b0 X +b0 Y +b0 Z +0[ +0] +b100 _ +b10000 a +b101 b +1d +bx e +b100 g +b0 k +b100 l +b10100010011 m +b10011 n +b0 o +b0 p +1q +1t +0w +1} + +#570000 +0! +0# +1w + +#575000 +1! +1"! +1# +b1000 % +b0 %! +b1100 & +b100 &! +b10010000000000000100010011 ' +b0 '! +b1100 ( +b0 (! +b0 *! +b0 +! +b100 , +b1010 ,! +b1000 - +b0 -! +b1100000000000110010011 . +b11 0 +b11 1 +b0 1! +b11 2 +12! +b11 4 +bx 5! +b11 6! +b10100 7! +b1 8! +09! +0:! +b0 ;! +b111 < +b0 =! +b0 >! +b11 @ +b0 B +b100 C +b0 D +b0 E +b0 G +b0 H +b1010 I +1M +b0 P +b0 R +b0 S +b0 T +b0 U +1V +bx W +b11 X +b10100 Y +b1 Z +1[ +b0 _ +b0 a +b0 b +0c +0d +b0 e +b1000 g +b100 k +b1000 l +b1100000000000110010011 m +b10011 n +b0 o +b0 p +0w +b11 x + +#580000 +0! +0# +1w + +#585000 +1! +1# +b1100 % +b100 %! +b10000 & +b1000 &! +b10001010010001010000011 ' +b10000 ( +b11 (! +b11 )! +b11 +! +b1000 , +b11 ,! +b1100 - +b10010000000000000100010011 . +b100 0 +b10 1 +b11 1! +b100100 2 +bx 4 +b0 5! +b0 6! +b100 7! +b1010 8! +19! +bx ;! +b101100 < +b10100 =! +b1 >! +bx @ +b100 B +b1000 C +b11 E +b11 F +b11 H +b11 I +b11 S +b11 T +b11 U +0V +b0 W +b0 X +b100 Y +b1010 Z +bx _ +b10100 a +b1 b +1c +bx e +b1100 g +b1000 k +b1100 l +b10010000000000000100010011 m +b10011 n +b0 o +b1 p +1q +1t +0w +b100100 x + +#590000 +0! +0# +1w + +#595000 +1! +1# +b10000 % +b1000 %! +b10100 & +b1100 &! +b1100101000000010110011 ' +b10100 ( +bx (! +b100100 )! +b100 +! +b1100 , +b10 ,! +b10000 - +b10001010010001010000011 . +b1010 / +b1 /! +b101 1 +b100100 1! +b100 2 +b11 5! +b11 6! +17 +b1000 7! +b11 8! +b0 ;! +b10000 < +b1 = +b100 =! +b1010 >! +b1000 B +b1100 C +bx E +b100100 F +b100 H +b10 I +bx S +b100100 T +b100100 U +b11 W +b11 X +b1000 Y +b11 Z +b0 _ +b100 a +b1010 b +b0 e +b10000 g +b1100 k +b10000 l +b10001010010001010000011 m +b11 n +b10 o +b0 p +1q +1s +1t +0w +b100 x + +#600000 +0! +0# +1w + +#605000 +1! +1!! +1# +b0 % +b1100 %! +b100 & +b10000 &! +b10100010011 ' +b100 ( +0) +b100 )! +0* +b1010 *! +b10000 , +b101 ,! +b10100 - +b1100101000000010110011 . +b101 / +b0 /! +b11 0 +b1 0! +b1 1 +b100 1! +b0 2 +bx 3 +b11 4 +b100100 5! +bx 6! +07 +b1100 7! +08 +b10 8! +b11 ;! +b10000 < +b0 = +b1000 =! +b1 > +b11 >! +bx ? +b11 @ +1A +b1100 B +b10000 C +b100 F +b1010 G +b101 I +1L +b100 T +b100 U +b100100 W +bx X +b1100 Y +b10 Z +b11 _ +b1000 a +b11 b +b11 e +1f +b0 g +b10000 k +b10100 l +b1100101000000010110011 m +b110011 n +b0 o +b0 p +1q +0s +0t +0w +b0 x +0y +0z +1| + +#610000 +0! +0# +1w + +#615000 +1! +0!! +0"! +1# +b0 %! +b0 &! +b0 (! +1) +b0 )! +1* +b0 *! +b0 +! +b0 ,! +b10 /! +b0 0! +b0 1! +14! +b100 5! +b10000 7! +b101 8! +b100100 ;! +b10 = +b1100 =! +b0 > +b10 >! +b100 ? +b11 @ +0A +b0 B +b0 C +b0 E +b0 F +b0 G +b0 H +b0 I +0J +0L +0M +b0 S +b0 T +b0 U +1V +b100 W +b10000 Y +b101 Z +1] +b100100 _ +b1100 a +b10 b +b100100 e +0f +0w +1y +1z +0| +0} + +#620000 +0! +0# +1w + +#625000 +1! +1# +b100 % +b10000 %! +b1000 & +b10100 &! +b1100000000000110010011 ' +bx '! +b1000 ( +b11 (! +b101 *! +b11 +! +b0 , +b1 ,! +b100 - +b1 -! +b10100010011 . +b0 / +b0 /! +b0 0 +b1010 1 +bx 1! +02! +b0 3 +b0 4 +04! +b0 5! +b0 6! +b0 7! +18 +b0 8! +1:! +b100 ;! +b0 < +b0 = +b10000 =! +b101 >! +b0 ? +b0 @ +b10000 B +b10100 C +bx D +b11 E +b101 G +b11 H +b1 I +1J +b1 P +bx R +b11 S +b11 T +bx U +xV +b0 W +b0 X +b0 Y +b0 Z +0[ +0] +b100 _ +b10000 a +b101 b +1d +bx e +b100 g +b0 k +b100 l +b10100010011 m +b10011 n +b0 o +b0 p +1q +1t +0w +1} + +#630000 +0! +0# +1w + +#635000 +1! +1"! +1# +b1000 % +b0 %! +b1100 & +b100 &! +b10010000000000000100010011 ' +b0 '! +b1100 ( +b0 (! +b0 *! +b0 +! +b100 , +b1010 ,! +b1000 - +b0 -! +b1100000000000110010011 . +b11 0 +b11 1 +b0 1! +b11 2 +12! +b11 4 +bx 5! +b11 6! +b10100 7! +b1 8! +09! +0:! +b0 ;! +b111 < +b0 =! +b0 >! +b11 @ +b0 B +b100 C +b0 D +b0 E +b0 G +b0 H +b1010 I +1M +b0 P +b0 R +b0 S +b0 T +b0 U +1V +bx W +b11 X +b10100 Y +b1 Z +1[ +b0 _ +b0 a +b0 b +0c +0d +b0 e +b1000 g +b100 k +b1000 l +b1100000000000110010011 m +b10011 n +b0 o +b0 p +0w +b11 x + +#640000 +0! +0# +1w + +#645000 +1! +1# +b1100 % +b100 %! +b10000 & +b1000 &! +b10001010010001010000011 ' +b10000 ( +b11 (! +b11 )! +b11 +! +b1000 , +b11 ,! +b1100 - +b10010000000000000100010011 . +b100 0 +b10 1 +b11 1! +b100100 2 +bx 4 +b0 5! +b0 6! +b100 7! +b1010 8! +19! +bx ;! +b101100 < +b10100 =! +b1 >! +bx @ +b100 B +b1000 C +b11 E +b11 F +b11 H +b11 I +b11 S +b11 T +b11 U +0V +b0 W +b0 X +b100 Y +b1010 Z +bx _ +b10100 a +b1 b +1c +bx e +b1100 g +b1000 k +b1100 l +b10010000000000000100010011 m +b10011 n +b0 o +b1 p +1q +1t +0w +b100100 x + +#650000 +0! +0# +1w + +#655000 +1! +1# +b10000 % +b1000 %! +b10100 & +b1100 &! +b1100101000000010110011 ' +b10100 ( +bx (! +b100100 )! +b100 +! +b1100 , +b10 ,! +b10000 - +b10001010010001010000011 . +b1010 / +b1 /! +b101 1 +b100100 1! +b100 2 +b11 5! +b11 6! +17 +b1000 7! +b11 8! +b0 ;! +b10000 < +b1 = +b100 =! +b1010 >! +b1000 B +b1100 C +bx E +b100100 F +b100 H +b10 I +bx S +b100100 T +b100100 U +b11 W +b11 X +b1000 Y +b11 Z +b0 _ +b100 a +b1010 b +b0 e +b10000 g +b1100 k +b10000 l +b10001010010001010000011 m +b11 n +b10 o +b0 p +1q +1s +1t +0w +b100 x + +#660000 +0! +0# +1w + +#665000 +1! +1!! +1# +b0 % +b1100 %! +b100 & +b10000 &! +b10100010011 ' +b100 ( +0) +b100 )! +0* +b1010 *! +b10000 , +b101 ,! +b10100 - +b1100101000000010110011 . +b101 / +b0 /! +b11 0 +b1 0! +b1 1 +b100 1! +b0 2 +bx 3 +b11 4 +b100100 5! +bx 6! +07 +b1100 7! +08 +b10 8! +b11 ;! +b10000 < +b0 = +b1000 =! +b1 > +b11 >! +bx ? +b11 @ +1A +b1100 B +b10000 C +b100 F +b1010 G +b101 I +1L +b100 T +b100 U +b100100 W +bx X +b1100 Y +b10 Z +b11 _ +b1000 a +b11 b +b11 e +1f +b0 g +b10000 k +b10100 l +b1100101000000010110011 m +b110011 n +b0 o +b0 p +1q +0s +0t +0w +b0 x +0y +0z +1| + +#670000 +0! +0# +1w + +#675000 +1! +0!! +0"! +1# +b0 %! +b0 &! +b0 (! +1) +b0 )! +1* +b0 *! +b0 +! +b0 ,! +b10 /! +b0 0! +b0 1! +14! +b100 5! +b10000 7! +b101 8! +b100100 ;! +b10 = +b1100 =! +b0 > +b10 >! +b100 ? +b11 @ +0A +b0 B +b0 C +b0 E +b0 F +b0 G +b0 H +b0 I +0J +0L +0M +b0 S +b0 T +b0 U +1V +b100 W +b10000 Y +b101 Z +1] +b100100 _ +b1100 a +b10 b +b100100 e +0f +0w +1y +1z +0| +0} + +#680000 +0! +0# +1w + +#685000 +1! +1# +b100 % +b10000 %! +b1000 & +b10100 &! +b1100000000000110010011 ' +bx '! +b1000 ( +b11 (! +b101 *! +b11 +! +b0 , +b1 ,! +b100 - +b1 -! +b10100010011 . +b0 / +b0 /! +b0 0 +b1010 1 +bx 1! +02! +b0 3 +b0 4 +04! +b0 5! +b0 6! +b0 7! +18 +b0 8! +1:! +b100 ;! +b0 < +b0 = +b10000 =! +b101 >! +b0 ? +b0 @ +b10000 B +b10100 C +bx D +b11 E +b101 G +b11 H +b1 I +1J +b1 P +bx R +b11 S +b11 T +bx U +xV +b0 W +b0 X +b0 Y +b0 Z +0[ +0] +b100 _ +b10000 a +b101 b +1d +bx e +b100 g +b0 k +b100 l +b10100010011 m +b10011 n +b0 o +b0 p +1q +1t +0w +1} + +#690000 +0! +0# +1w + +#695000 +1! +1"! +1# +b1000 % +b0 %! +b1100 & +b100 &! +b10010000000000000100010011 ' +b0 '! +b1100 ( +b0 (! +b0 *! +b0 +! +b100 , +b1010 ,! +b1000 - +b0 -! +b1100000000000110010011 . +b11 0 +b11 1 +b0 1! +b11 2 +12! +b11 4 +bx 5! +b11 6! +b10100 7! +b1 8! +09! +0:! +b0 ;! +b111 < +b0 =! +b0 >! +b11 @ +b0 B +b100 C +b0 D +b0 E +b0 G +b0 H +b1010 I +1M +b0 P +b0 R +b0 S +b0 T +b0 U +1V +bx W +b11 X +b10100 Y +b1 Z +1[ +b0 _ +b0 a +b0 b +0c +0d +b0 e +b1000 g +b100 k +b1000 l +b1100000000000110010011 m +b10011 n +b0 o +b0 p +0w +b11 x + +#700000 +0! +0# +1w + +#705000 +1! +1# +b1100 % +b100 %! +b10000 & +b1000 &! +b10001010010001010000011 ' +b10000 ( +b11 (! +b11 )! +b11 +! +b1000 , +b11 ,! +b1100 - +b10010000000000000100010011 . +b100 0 +b10 1 +b11 1! +b100100 2 +bx 4 +b0 5! +b0 6! +b100 7! +b1010 8! +19! +bx ;! +b101100 < +b10100 =! +b1 >! +bx @ +b100 B +b1000 C +b11 E +b11 F +b11 H +b11 I +b11 S +b11 T +b11 U +0V +b0 W +b0 X +b100 Y +b1010 Z +bx _ +b10100 a +b1 b +1c +bx e +b1100 g +b1000 k +b1100 l +b10010000000000000100010011 m +b10011 n +b0 o +b1 p +1q +1t +0w +b100100 x + +#710000 +0! +0# +1w + +#715000 +1! +1# +b10000 % +b1000 %! +b10100 & +b1100 &! +b1100101000000010110011 ' +b10100 ( +bx (! +b100100 )! +b100 +! +b1100 , +b10 ,! +b10000 - +b10001010010001010000011 . +b1010 / +b1 /! +b101 1 +b100100 1! +b100 2 +b11 5! +b11 6! +17 +b1000 7! +b11 8! +b0 ;! +b10000 < +b1 = +b100 =! +b1010 >! +b1000 B +b1100 C +bx E +b100100 F +b100 H +b10 I +bx S +b100100 T +b100100 U +b11 W +b11 X +b1000 Y +b11 Z +b0 _ +b100 a +b1010 b +b0 e +b10000 g +b1100 k +b10000 l +b10001010010001010000011 m +b11 n +b10 o +b0 p +1q +1s +1t +0w +b100 x + +#720000 +0! +0# +1w + +#725000 +1! +1!! +1# +b0 % +b1100 %! +b100 & +b10000 &! +b10100010011 ' +b100 ( +0) +b100 )! +0* +b1010 *! +b10000 , +b101 ,! +b10100 - +b1100101000000010110011 . +b101 / +b0 /! +b11 0 +b1 0! +b1 1 +b100 1! +b0 2 +bx 3 +b11 4 +b100100 5! +bx 6! +07 +b1100 7! +08 +b10 8! +b11 ;! +b10000 < +b0 = +b1000 =! +b1 > +b11 >! +bx ? +b11 @ +1A +b1100 B +b10000 C +b100 F +b1010 G +b101 I +1L +b100 T +b100 U +b100100 W +bx X +b1100 Y +b10 Z +b11 _ +b1000 a +b11 b +b11 e +1f +b0 g +b10000 k +b10100 l +b1100101000000010110011 m +b110011 n +b0 o +b0 p +1q +0s +0t +0w +b0 x +0y +0z +1| + +#730000 +0! +0# +1w + +#735000 +1! +0!! +0"! +1# +b0 %! +b0 &! +b0 (! +1) +b0 )! +1* +b0 *! +b0 +! +b0 ,! +b10 /! +b0 0! +b0 1! +14! +b100 5! +b10000 7! +b101 8! +b100100 ;! +b10 = +b1100 =! +b0 > +b10 >! +b100 ? +b11 @ +0A +b0 B +b0 C +b0 E +b0 F +b0 G +b0 H +b0 I +0J +0L +0M +b0 S +b0 T +b0 U +1V +b100 W +b10000 Y +b101 Z +1] +b100100 _ +b1100 a +b10 b +b100100 e +0f +0w +1y +1z +0| +0} + +#740000 +0! +0# +1w + +#745000 +1! +1# +b100 % +b10000 %! +b1000 & +b10100 &! +b1100000000000110010011 ' +bx '! +b1000 ( +b11 (! +b101 *! +b11 +! +b0 , +b1 ,! +b100 - +b1 -! +b10100010011 . +b0 / +b0 /! +b0 0 +b1010 1 +bx 1! +02! +b0 3 +b0 4 +04! +b0 5! +b0 6! +b0 7! +18 +b0 8! +1:! +b100 ;! +b0 < +b0 = +b10000 =! +b101 >! +b0 ? +b0 @ +b10000 B +b10100 C +bx D +b11 E +b101 G +b11 H +b1 I +1J +b1 P +bx R +b11 S +b11 T +bx U +xV +b0 W +b0 X +b0 Y +b0 Z +0[ +0] +b100 _ +b10000 a +b101 b +1d +bx e +b100 g +b0 k +b100 l +b10100010011 m +b10011 n +b0 o +b0 p +1q +1t +0w +1} + +#750000 +0! +0# +1w + +#755000 +1! +1"! +1# +b1000 % +b0 %! +b1100 & +b100 &! +b10010000000000000100010011 ' +b0 '! +b1100 ( +b0 (! +b0 *! +b0 +! +b100 , +b1010 ,! +b1000 - +b0 -! +b1100000000000110010011 . +b11 0 +b11 1 +b0 1! +b11 2 +12! +b11 4 +bx 5! +b11 6! +b10100 7! +b1 8! +09! +0:! +b0 ;! +b111 < +b0 =! +b0 >! +b11 @ +b0 B +b100 C +b0 D +b0 E +b0 G +b0 H +b1010 I +1M +b0 P +b0 R +b0 S +b0 T +b0 U +1V +bx W +b11 X +b10100 Y +b1 Z +1[ +b0 _ +b0 a +b0 b +0c +0d +b0 e +b1000 g +b100 k +b1000 l +b1100000000000110010011 m +b10011 n +b0 o +b0 p +0w +b11 x + +#760000 +0! +0# +1w + +#765000 +1! +1# +b1100 % +b100 %! +b10000 & +b1000 &! +b10001010010001010000011 ' +b10000 ( +b11 (! +b11 )! +b11 +! +b1000 , +b11 ,! +b1100 - +b10010000000000000100010011 . +b100 0 +b10 1 +b11 1! +b100100 2 +bx 4 +b0 5! +b0 6! +b100 7! +b1010 8! +19! +bx ;! +b101100 < +b10100 =! +b1 >! +bx @ +b100 B +b1000 C +b11 E +b11 F +b11 H +b11 I +b11 S +b11 T +b11 U +0V +b0 W +b0 X +b100 Y +b1010 Z +bx _ +b10100 a +b1 b +1c +bx e +b1100 g +b1000 k +b1100 l +b10010000000000000100010011 m +b10011 n +b0 o +b1 p +1q +1t +0w +b100100 x + +#770000 +0! +0# +1w + +#775000 +1! +1# +b10000 % +b1000 %! +b10100 & +b1100 &! +b1100101000000010110011 ' +b10100 ( +bx (! +b100100 )! +b100 +! +b1100 , +b10 ,! +b10000 - +b10001010010001010000011 . +b1010 / +b1 /! +b101 1 +b100100 1! +b100 2 +b11 5! +b11 6! +17 +b1000 7! +b11 8! +b0 ;! +b10000 < +b1 = +b100 =! +b1010 >! +b1000 B +b1100 C +bx E +b100100 F +b100 H +b10 I +bx S +b100100 T +b100100 U +b11 W +b11 X +b1000 Y +b11 Z +b0 _ +b100 a +b1010 b +b0 e +b10000 g +b1100 k +b10000 l +b10001010010001010000011 m +b11 n +b10 o +b0 p +1q +1s +1t +0w +b100 x + +#780000 +0! +0# +1w + +#785000 +1! +1!! +1# +b0 % +b1100 %! +b100 & +b10000 &! +b10100010011 ' +b100 ( +0) +b100 )! +0* +b1010 *! +b10000 , +b101 ,! +b10100 - +b1100101000000010110011 . +b101 / +b0 /! +b11 0 +b1 0! +b1 1 +b100 1! +b0 2 +bx 3 +b11 4 +b100100 5! +bx 6! +07 +b1100 7! +08 +b10 8! +b11 ;! +b10000 < +b0 = +b1000 =! +b1 > +b11 >! +bx ? +b11 @ +1A +b1100 B +b10000 C +b100 F +b1010 G +b101 I +1L +b100 T +b100 U +b100100 W +bx X +b1100 Y +b10 Z +b11 _ +b1000 a +b11 b +b11 e +1f +b0 g +b10000 k +b10100 l +b1100101000000010110011 m +b110011 n +b0 o +b0 p +1q +0s +0t +0w +b0 x +0y +0z +1| + +#790000 +0! +0# +1w + +#795000 +1! +0!! +0"! +1# +b0 %! +b0 &! +b0 (! +1) +b0 )! +1* +b0 *! +b0 +! +b0 ,! +b10 /! +b0 0! +b0 1! +14! +b100 5! +b10000 7! +b101 8! +b100100 ;! +b10 = +b1100 =! +b0 > +b10 >! +b100 ? +b11 @ +0A +b0 B +b0 C +b0 E +b0 F +b0 G +b0 H +b0 I +0J +0L +0M +b0 S +b0 T +b0 U +1V +b100 W +b10000 Y +b101 Z +1] +b100100 _ +b1100 a +b10 b +b100100 e +0f +0w +1y +1z +0| +0} + +#800000 +0! +0# +1w + +#805000 +1! +1# +b100 % +b10000 %! +b1000 & +b10100 &! +b1100000000000110010011 ' +bx '! +b1000 ( +b11 (! +b101 *! +b11 +! +b0 , +b1 ,! +b100 - +b1 -! +b10100010011 . +b0 / +b0 /! +b0 0 +b1010 1 +bx 1! +02! +b0 3 +b0 4 +04! +b0 5! +b0 6! +b0 7! +18 +b0 8! +1:! +b100 ;! +b0 < +b0 = +b10000 =! +b101 >! +b0 ? +b0 @ +b10000 B +b10100 C +bx D +b11 E +b101 G +b11 H +b1 I +1J +b1 P +bx R +b11 S +b11 T +bx U +xV +b0 W +b0 X +b0 Y +b0 Z +0[ +0] +b100 _ +b10000 a +b101 b +1d +bx e +b100 g +b0 k +b100 l +b10100010011 m +b10011 n +b0 o +b0 p +1q +1t +0w +1} + +#810000 +0! +0# +1w + +#815000 +1! +1"! +1# +b1000 % +b0 %! +b1100 & +b100 &! +b10010000000000000100010011 ' +b0 '! +b1100 ( +b0 (! +b0 *! +b0 +! +b100 , +b1010 ,! +b1000 - +b0 -! +b1100000000000110010011 . +b11 0 +b11 1 +b0 1! +b11 2 +12! +b11 4 +bx 5! +b11 6! +b10100 7! +b1 8! +09! +0:! +b0 ;! +b111 < +b0 =! +b0 >! +b11 @ +b0 B +b100 C +b0 D +b0 E +b0 G +b0 H +b1010 I +1M +b0 P +b0 R +b0 S +b0 T +b0 U +1V +bx W +b11 X +b10100 Y +b1 Z +1[ +b0 _ +b0 a +b0 b +0c +0d +b0 e +b1000 g +b100 k +b1000 l +b1100000000000110010011 m +b10011 n +b0 o +b0 p +0w +b11 x + +#820000 +0! +0# +1w + +#825000 +1! +1# +b1100 % +b100 %! +b10000 & +b1000 &! +b10001010010001010000011 ' +b10000 ( +b11 (! +b11 )! +b11 +! +b1000 , +b11 ,! +b1100 - +b10010000000000000100010011 . +b100 0 +b10 1 +b11 1! +b100100 2 +bx 4 +b0 5! +b0 6! +b100 7! +b1010 8! +19! +bx ;! +b101100 < +b10100 =! +b1 >! +bx @ +b100 B +b1000 C +b11 E +b11 F +b11 H +b11 I +b11 S +b11 T +b11 U +0V +b0 W +b0 X +b100 Y +b1010 Z +bx _ +b10100 a +b1 b +1c +bx e +b1100 g +b1000 k +b1100 l +b10010000000000000100010011 m +b10011 n +b0 o +b1 p +1q +1t +0w +b100100 x + +#830000 +0! +0# +1w + +#835000 +1! +1# +b10000 % +b1000 %! +b10100 & +b1100 &! +b1100101000000010110011 ' +b10100 ( +bx (! +b100100 )! +b100 +! +b1100 , +b10 ,! +b10000 - +b10001010010001010000011 . +b1010 / +b1 /! +b101 1 +b100100 1! +b100 2 +b11 5! +b11 6! +17 +b1000 7! +b11 8! +b0 ;! +b10000 < +b1 = +b100 =! +b1010 >! +b1000 B +b1100 C +bx E +b100100 F +b100 H +b10 I +bx S +b100100 T +b100100 U +b11 W +b11 X +b1000 Y +b11 Z +b0 _ +b100 a +b1010 b +b0 e +b10000 g +b1100 k +b10000 l +b10001010010001010000011 m +b11 n +b10 o +b0 p +1q +1s +1t +0w +b100 x + +#840000 +0! +0# +1w + +#845000 +1! +1!! +1# +b0 % +b1100 %! +b100 & +b10000 &! +b10100010011 ' +b100 ( +0) +b100 )! +0* +b1010 *! +b10000 , +b101 ,! +b10100 - +b1100101000000010110011 . +b101 / +b0 /! +b11 0 +b1 0! +b1 1 +b100 1! +b0 2 +bx 3 +b11 4 +b100100 5! +bx 6! +07 +b1100 7! +08 +b10 8! +b11 ;! +b10000 < +b0 = +b1000 =! +b1 > +b11 >! +bx ? +b11 @ +1A +b1100 B +b10000 C +b100 F +b1010 G +b101 I +1L +b100 T +b100 U +b100100 W +bx X +b1100 Y +b10 Z +b11 _ +b1000 a +b11 b +b11 e +1f +b0 g +b10000 k +b10100 l +b1100101000000010110011 m +b110011 n +b0 o +b0 p +1q +0s +0t +0w +b0 x +0y +0z +1| + +#850000 +0! +0# +1w + +#855000 +1! +0!! +0"! +1# +b0 %! +b0 &! +b0 (! +1) +b0 )! +1* +b0 *! +b0 +! +b0 ,! +b10 /! +b0 0! +b0 1! +14! +b100 5! +b10000 7! +b101 8! +b100100 ;! +b10 = +b1100 =! +b0 > +b10 >! +b100 ? +b11 @ +0A +b0 B +b0 C +b0 E +b0 F +b0 G +b0 H +b0 I +0J +0L +0M +b0 S +b0 T +b0 U +1V +b100 W +b10000 Y +b101 Z +1] +b100100 _ +b1100 a +b10 b +b100100 e +0f +0w +1y +1z +0| +0} + +#860000 +0! +0# +1w + +#865000 +1! +1# +b100 % +b10000 %! +b1000 & +b10100 &! +b1100000000000110010011 ' +bx '! +b1000 ( +b11 (! +b101 *! +b11 +! +b0 , +b1 ,! +b100 - +b1 -! +b10100010011 . +b0 / +b0 /! +b0 0 +b1010 1 +bx 1! +02! +b0 3 +b0 4 +04! +b0 5! +b0 6! +b0 7! +18 +b0 8! +1:! +b100 ;! +b0 < +b0 = +b10000 =! +b101 >! +b0 ? +b0 @ +b10000 B +b10100 C +bx D +b11 E +b101 G +b11 H +b1 I +1J +b1 P +bx R +b11 S +b11 T +bx U +xV +b0 W +b0 X +b0 Y +b0 Z +0[ +0] +b100 _ +b10000 a +b101 b +1d +bx e +b100 g +b0 k +b100 l +b10100010011 m +b10011 n +b0 o +b0 p +1q +1t +0w +1} + +#870000 +0! +0# +1w + +#875000 +1! +1"! +1# +b1000 % +b0 %! +b1100 & +b100 &! +b10010000000000000100010011 ' +b0 '! +b1100 ( +b0 (! +b0 *! +b0 +! +b100 , +b1010 ,! +b1000 - +b0 -! +b1100000000000110010011 . +b11 0 +b11 1 +b0 1! +b11 2 +12! +b11 4 +bx 5! +b11 6! +b10100 7! +b1 8! +09! +0:! +b0 ;! +b111 < +b0 =! +b0 >! +b11 @ +b0 B +b100 C +b0 D +b0 E +b0 G +b0 H +b1010 I +1M +b0 P +b0 R +b0 S +b0 T +b0 U +1V +bx W +b11 X +b10100 Y +b1 Z +1[ +b0 _ +b0 a +b0 b +0c +0d +b0 e +b1000 g +b100 k +b1000 l +b1100000000000110010011 m +b10011 n +b0 o +b0 p +0w +b11 x + +#880000 +0! +0# +1w + +#885000 +1! +1# +b1100 % +b100 %! +b10000 & +b1000 &! +b10001010010001010000011 ' +b10000 ( +b11 (! +b11 )! +b11 +! +b1000 , +b11 ,! +b1100 - +b10010000000000000100010011 . +b100 0 +b10 1 +b11 1! +b100100 2 +bx 4 +b0 5! +b0 6! +b100 7! +b1010 8! +19! +bx ;! +b101100 < +b10100 =! +b1 >! +bx @ +b100 B +b1000 C +b11 E +b11 F +b11 H +b11 I +b11 S +b11 T +b11 U +0V +b0 W +b0 X +b100 Y +b1010 Z +bx _ +b10100 a +b1 b +1c +bx e +b1100 g +b1000 k +b1100 l +b10010000000000000100010011 m +b10011 n +b0 o +b1 p +1q +1t +0w +b100100 x + +#890000 +0! +0# +1w + +#895000 +1! +1# +b10000 % +b1000 %! +b10100 & +b1100 &! +b1100101000000010110011 ' +b10100 ( +bx (! +b100100 )! +b100 +! +b1100 , +b10 ,! +b10000 - +b10001010010001010000011 . +b1010 / +b1 /! +b101 1 +b100100 1! +b100 2 +b11 5! +b11 6! +17 +b1000 7! +b11 8! +b0 ;! +b10000 < +b1 = +b100 =! +b1010 >! +b1000 B +b1100 C +bx E +b100100 F +b100 H +b10 I +bx S +b100100 T +b100100 U +b11 W +b11 X +b1000 Y +b11 Z +b0 _ +b100 a +b1010 b +b0 e +b10000 g +b1100 k +b10000 l +b10001010010001010000011 m +b11 n +b10 o +b0 p +1q +1s +1t +0w +b100 x + +#900000 +0! +0# +1w + +#905000 +1! +1!! +1# +b0 % +b1100 %! +b100 & +b10000 &! +b10100010011 ' +b100 ( +0) +b100 )! +0* +b1010 *! +b10000 , +b101 ,! +b10100 - +b1100101000000010110011 . +b101 / +b0 /! +b11 0 +b1 0! +b1 1 +b100 1! +b0 2 +bx 3 +b11 4 +b100100 5! +bx 6! +07 +b1100 7! +08 +b10 8! +b11 ;! +b10000 < +b0 = +b1000 =! +b1 > +b11 >! +bx ? +b11 @ +1A +b1100 B +b10000 C +b100 F +b1010 G +b101 I +1L +b100 T +b100 U +b100100 W +bx X +b1100 Y +b10 Z +b11 _ +b1000 a +b11 b +b11 e +1f +b0 g +b10000 k +b10100 l +b1100101000000010110011 m +b110011 n +b0 o +b0 p +1q +0s +0t +0w +b0 x +0y +0z +1| + +#910000 +0! +0# +1w + +#915000 +1! +0!! +0"! +1# +b0 %! +b0 &! +b0 (! +1) +b0 )! +1* +b0 *! +b0 +! +b0 ,! +b10 /! +b0 0! +b0 1! +14! +b100 5! +b10000 7! +b101 8! +b100100 ;! +b10 = +b1100 =! +b0 > +b10 >! +b100 ? +b11 @ +0A +b0 B +b0 C +b0 E +b0 F +b0 G +b0 H +b0 I +0J +0L +0M +b0 S +b0 T +b0 U +1V +b100 W +b10000 Y +b101 Z +1] +b100100 _ +b1100 a +b10 b +b100100 e +0f +0w +1y +1z +0| +0} + +#920000 +0! +0# +1w + +#925000 +1! +1# +b100 % +b10000 %! +b1000 & +b10100 &! +b1100000000000110010011 ' +bx '! +b1000 ( +b11 (! +b101 *! +b11 +! +b0 , +b1 ,! +b100 - +b1 -! +b10100010011 . +b0 / +b0 /! +b0 0 +b1010 1 +bx 1! +02! +b0 3 +b0 4 +04! +b0 5! +b0 6! +b0 7! +18 +b0 8! +1:! +b100 ;! +b0 < +b0 = +b10000 =! +b101 >! +b0 ? +b0 @ +b10000 B +b10100 C +bx D +b11 E +b101 G +b11 H +b1 I +1J +b1 P +bx R +b11 S +b11 T +bx U +xV +b0 W +b0 X +b0 Y +b0 Z +0[ +0] +b100 _ +b10000 a +b101 b +1d +bx e +b100 g +b0 k +b100 l +b10100010011 m +b10011 n +b0 o +b0 p +1q +1t +0w +1} + +#930000 +0! +0# +1w + +#935000 +1! +1"! +1# +b1000 % +b0 %! +b1100 & +b100 &! +b10010000000000000100010011 ' +b0 '! +b1100 ( +b0 (! +b0 *! +b0 +! +b100 , +b1010 ,! +b1000 - +b0 -! +b1100000000000110010011 . +b11 0 +b11 1 +b0 1! +b11 2 +12! +b11 4 +bx 5! +b11 6! +b10100 7! +b1 8! +09! +0:! +b0 ;! +b111 < +b0 =! +b0 >! +b11 @ +b0 B +b100 C +b0 D +b0 E +b0 G +b0 H +b1010 I +1M +b0 P +b0 R +b0 S +b0 T +b0 U +1V +bx W +b11 X +b10100 Y +b1 Z +1[ +b0 _ +b0 a +b0 b +0c +0d +b0 e +b1000 g +b100 k +b1000 l +b1100000000000110010011 m +b10011 n +b0 o +b0 p +0w +b11 x + +#940000 +0! +0# +1w + +#945000 +1! +1# +b1100 % +b100 %! +b10000 & +b1000 &! +b10001010010001010000011 ' +b10000 ( +b11 (! +b11 )! +b11 +! +b1000 , +b11 ,! +b1100 - +b10010000000000000100010011 . +b100 0 +b10 1 +b11 1! +b100100 2 +bx 4 +b0 5! +b0 6! +b100 7! +b1010 8! +19! +bx ;! +b101100 < +b10100 =! +b1 >! +bx @ +b100 B +b1000 C +b11 E +b11 F +b11 H +b11 I +b11 S +b11 T +b11 U +0V +b0 W +b0 X +b100 Y +b1010 Z +bx _ +b10100 a +b1 b +1c +bx e +b1100 g +b1000 k +b1100 l +b10010000000000000100010011 m +b10011 n +b0 o +b1 p +1q +1t +0w +b100100 x + +#950000 +0! +0# +1w + +#955000 +1! +1# +b10000 % +b1000 %! +b10100 & +b1100 &! +b1100101000000010110011 ' +b10100 ( +bx (! +b100100 )! +b100 +! +b1100 , +b10 ,! +b10000 - +b10001010010001010000011 . +b1010 / +b1 /! +b101 1 +b100100 1! +b100 2 +b11 5! +b11 6! +17 +b1000 7! +b11 8! +b0 ;! +b10000 < +b1 = +b100 =! +b1010 >! +b1000 B +b1100 C +bx E +b100100 F +b100 H +b10 I +bx S +b100100 T +b100100 U +b11 W +b11 X +b1000 Y +b11 Z +b0 _ +b100 a +b1010 b +b0 e +b10000 g +b1100 k +b10000 l +b10001010010001010000011 m +b11 n +b10 o +b0 p +1q +1s +1t +0w +b100 x + +#960000 +0! +0# +1w + +#965000 +1! +1!! +1# +b0 % +b1100 %! +b100 & +b10000 &! +b10100010011 ' +b100 ( +0) +b100 )! +0* +b1010 *! +b10000 , +b101 ,! +b10100 - +b1100101000000010110011 . +b101 / +b0 /! +b11 0 +b1 0! +b1 1 +b100 1! +b0 2 +bx 3 +b11 4 +b100100 5! +bx 6! +07 +b1100 7! +08 +b10 8! +b11 ;! +b10000 < +b0 = +b1000 =! +b1 > +b11 >! +bx ? +b11 @ +1A +b1100 B +b10000 C +b100 F +b1010 G +b101 I +1L +b100 T +b100 U +b100100 W +bx X +b1100 Y +b10 Z +b11 _ +b1000 a +b11 b +b11 e +1f +b0 g +b10000 k +b10100 l +b1100101000000010110011 m +b110011 n +b0 o +b0 p +1q +0s +0t +0w +b0 x +0y +0z +1| + +#970000 +0! +0# +1w + +#975000 +1! +0!! +0"! +1# +b0 %! +b0 &! +b0 (! +1) +b0 )! +1* +b0 *! +b0 +! +b0 ,! +b10 /! +b0 0! +b0 1! +14! +b100 5! +b10000 7! +b101 8! +b100100 ;! +b10 = +b1100 =! +b0 > +b10 >! +b100 ? +b11 @ +0A +b0 B +b0 C +b0 E +b0 F +b0 G +b0 H +b0 I +0J +0L +0M +b0 S +b0 T +b0 U +1V +b100 W +b10000 Y +b101 Z +1] +b100100 _ +b1100 a +b10 b +b100100 e +0f +0w +1y +1z +0| +0} + +#980000 +0! +0# +1w + +#985000 +1! +1# +b100 % +b10000 %! +b1000 & +b10100 &! +b1100000000000110010011 ' +bx '! +b1000 ( +b11 (! +b101 *! +b11 +! +b0 , +b1 ,! +b100 - +b1 -! +b10100010011 . +b0 / +b0 /! +b0 0 +b1010 1 +bx 1! +02! +b0 3 +b0 4 +04! +b0 5! +b0 6! +b0 7! +18 +b0 8! +1:! +b100 ;! +b0 < +b0 = +b10000 =! +b101 >! +b0 ? +b0 @ +b10000 B +b10100 C +bx D +b11 E +b101 G +b11 H +b1 I +1J +b1 P +bx R +b11 S +b11 T +bx U +xV +b0 W +b0 X +b0 Y +b0 Z +0[ +0] +b100 _ +b10000 a +b101 b +1d +bx e +b100 g +b0 k +b100 l +b10100010011 m +b10011 n +b0 o +b0 p +1q +1t +0w +1} + +#990000 +0! +0# +1w + +#995000 +1! +1"! +1# +b1000 % +b0 %! +b1100 & +b100 &! +b10010000000000000100010011 ' +b0 '! +b1100 ( +b0 (! +b0 *! +b0 +! +b100 , +b1010 ,! +b1000 - +b0 -! +b1100000000000110010011 . +b11 0 +b11 1 +b0 1! +b11 2 +12! +b11 4 +bx 5! +b11 6! +b10100 7! +b1 8! +09! +0:! +b0 ;! +b111 < +b0 =! +b0 >! +b11 @ +b0 B +b100 C +b0 D +b0 E +b0 G +b0 H +b1010 I +1M +b0 P +b0 R +b0 S +b0 T +b0 U +1V +bx W +b11 X +b10100 Y +b1 Z +1[ +b0 _ +b0 a +b0 b +0c +0d +b0 e +b1000 g +b100 k +b1000 l +b1100000000000110010011 m +b10011 n +b0 o +b0 p +0w +b11 x + +#1000000 +0! +0# +1w diff --git a/riscv-ac.sim/sim_1/behav/xsim/tb_top_behav.wdb b/riscv-ac.sim/sim_1/behav/xsim/tb_top_behav.wdb new file mode 100644 index 0000000..95b798b Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/tb_top_behav.wdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/tb_top_vlog.prj b/riscv-ac.sim/sim_1/behav/xsim/tb_top_vlog.prj new file mode 100644 index 0000000..3c6b9ee --- /dev/null +++ b/riscv-ac.sim/sim_1/behav/xsim/tb_top_vlog.prj @@ -0,0 +1,23 @@ +# compile verilog/system verilog design source files +verilog xil_defaultlib --include "../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef" \ +"../../../../riscv-ac.srcs/sources_1/new/alu.v" \ +"../../../../riscv-ac.srcs/sources_1/new/control.v" \ +"../../../../riscv-ac.srcs/sources_1/new/dmem.v" \ +"../../../../riscv-ac.srcs/sources_1/new/ex_me.v" \ +"../../../../riscv-ac.srcs/sources_1/new/forwarding.v" \ +"../../../../riscv-ac.srcs/sources_1/new/hazard.v" \ +"../../../../riscv-ac.srcs/sources_1/new/id_ex.v" \ +"../../../../riscv-ac.srcs/sources_1/new/if_id.v" \ +"../../../../riscv-ac.srcs/sources_1/new/imem.v" \ +"../../../../riscv-ac.srcs/sources_1/new/imm_gen.v" \ +"../../../../riscv-ac.srcs/sources_1/new/me_wb.v" \ +"../../../../riscv-ac.srcs/sources_1/new/pc.v" \ +"../../../../riscv-ac.srcs/sources_1/new/regfile.v" \ +"../../../../riscv-ac.srcs/sources_1/new/top.v" \ +"../../../../riscv-ac.srcs/sim_1/new/tb_top.v" \ + +# compile glbl module +verilog xil_defaultlib "glbl.v" + +# Do not sort compile order +nosort diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/Compile_Options.txt b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/Compile_Options.txt new file mode 100644 index 0000000..1ba54ab --- /dev/null +++ b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/Compile_Options.txt @@ -0,0 +1 @@ +--incr --debug "typical" --relax --mt "8" -L "xil_defaultlib" -L "unisims_ver" -L "unimacro_ver" -L "secureip" --snapshot "tb_top_behav" "xil_defaultlib.tb_top" "xil_defaultlib.glbl" -log "elaborate.log" diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/TempBreakPointFile.txt b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/TempBreakPointFile.txt new file mode 100644 index 0000000..fdbc612 --- /dev/null +++ b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/TempBreakPointFile.txt @@ -0,0 +1 @@ +Breakpoint File Version 1.0 diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/obj/xsim_0.lnx64.o b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/obj/xsim_0.lnx64.o new file mode 100644 index 0000000..37ddb81 Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/obj/xsim_0.lnx64.o differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/obj/xsim_1.lnx64.o b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/obj/xsim_1.lnx64.o new file mode 100644 index 0000000..fc30c61 Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/obj/xsim_1.lnx64.o differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.dbg b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.dbg new file mode 100644 index 0000000..d7a88f0 Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.dbg differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.mem b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.mem new file mode 100644 index 0000000..1806ff8 Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.mem differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.reloc b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.reloc new file mode 100644 index 0000000..49a6444 Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.reloc differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.rlx b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.rlx new file mode 100644 index 0000000..5e00684 --- /dev/null +++ b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.rlx @@ -0,0 +1,12 @@ + +{ + crc : 1048859293793588504 , + ccp_crc : 0 , + cmdline : " --incr --debug typical --relax --mt 8 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip --snapshot tb_top_behav xil_defaultlib.tb_top xil_defaultlib.glbl" , + buildDate : "Nov 14 2025" , + buildTime : "12:36:23" , + linkCmd : "/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/g++ -Wa,-W -O -fPIC -m64 -Wl,--no-as-needed -Wl,--unresolved-symbols=ignore-all -o \"xsim.dir/tb_top_behav/xsimk\" \"xsim.dir/tb_top_behav/obj/xsim_0.lnx64.o\" \"xsim.dir/tb_top_behav/obj/xsim_1.lnx64.o\" -L\"/opt/Xilinx/2025.2/Vivado/lib/lnx64.o\" -lxv_simulator_kernel -L/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -Wl,--disable-new-dtags -Wl,-rpath=/opt/Xilinx/2025.2/Vivado/lib/lnx64.o/../../tps/lnx64/gcc-9.3.0/bin/../lib64 -lxv_simbridge_kernel" , + aggregate_nets : + [ + ] +} \ No newline at end of file diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.rtti b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.rtti new file mode 100644 index 0000000..cd0577f Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.rtti differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.svtype b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.svtype new file mode 100644 index 0000000..10f09ab Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.svtype differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.type b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.type new file mode 100644 index 0000000..14a09a2 Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.type differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.version b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.version new file mode 100644 index 0000000..6327f31 --- /dev/null +++ b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.version @@ -0,0 +1 @@ +hjhoth \ No newline at end of file diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.xdbg b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.xdbg new file mode 100644 index 0000000..0b42d29 Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsim.xdbg differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsimSettings.ini b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsimSettings.ini new file mode 100644 index 0000000..5bc733c --- /dev/null +++ b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsimSettings.ini @@ -0,0 +1,50 @@ +[General] +ARRAY_DISPLAY_LIMIT=512 +RADIX=hex +TIME_UNIT=ns +TRACE_LIMIT=2147483647 +VHDL_ENTITY_SCOPE_FILTER=true +VHDL_PACKAGE_SCOPE_FILTER=false +VHDL_BLOCK_SCOPE_FILTER=true +VHDL_PROCESS_SCOPE_FILTER=false +VHDL_PROCEDURE_SCOPE_FILTER=false +VERILOG_MODULE_SCOPE_FILTER=true +VERILOG_PACKAGE_SCOPE_FILTER=false +VERILOG_BLOCK_SCOPE_FILTER=false +VERILOG_TASK_SCOPE_FILTER=false +VERILOG_PROCESS_SCOPE_FILTER=false +INPUT_OBJECT_FILTER=true +OUTPUT_OBJECT_FILTER=true +INOUT_OBJECT_FILTER=true +INTERNAL_OBJECT_FILTER=true +CONSTANT_OBJECT_FILTER=true +VARIABLE_OBJECT_FILTER=true +INPUT_PROTOINST_FILTER=true +OUTPUT_PROTOINST_FILTER=true +INOUT_PROTOINST_FILTER=true +INTERNAL_PROTOINST_FILTER=true +CONSTANT_PROTOINST_FILTER=true +VARIABLE_PROTOINST_FILTER=true +SCOPE_NAME_COLUMN_WIDTH=93 +SCOPE_DESIGN_UNIT_COLUMN_WIDTH=83 +SCOPE_BLOCK_TYPE_COLUMN_WIDTH=103 +OBJECT_NAME_COLUMN_WIDTH=121 +OBJECT_VALUE_COLUMN_WIDTH=72 +OBJECT_DATA_TYPE_COLUMN_WIDTH=75 +PROCESS_NAME_COLUMN_WIDTH=75 +PROCESS_TYPE_COLUMN_WIDTH=75 +FRAME_INDEX_COLUMN_WIDTH=75 +FRAME_NAME_COLUMN_WIDTH=75 +FRAME_FILE_NAME_COLUMN_WIDTH=75 +FRAME_LINE_NUM_COLUMN_WIDTH=75 +LOCAL_NAME_COLUMN_WIDTH=75 +LOCAL_VALUE_COLUMN_WIDTH=75 +LOCAL_DATA_TYPE_COLUMN_WIDTH=0 +PROTO_NAME_COLUMN_WIDTH=0 +PROTO_VALUE_COLUMN_WIDTH=0 +INPUT_LOCAL_FILTER=1 +OUTPUT_LOCAL_FILTER=1 +INOUT_LOCAL_FILTER=1 +INTERNAL_LOCAL_FILTER=1 +CONSTANT_LOCAL_FILTER=1 +VARIABLE_LOCAL_FILTER=1 diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsimk b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsimk new file mode 100755 index 0000000..3257b77 Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/tb_top_behav/xsimk differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/alu.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/alu.sdb new file mode 100644 index 0000000..e03dbb9 Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/alu.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/control.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/control.sdb new file mode 100644 index 0000000..ef9f466 Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/control.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/dmem.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/dmem.sdb new file mode 100644 index 0000000..36e4811 Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/dmem.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/ex_me.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/ex_me.sdb new file mode 100644 index 0000000..0ecd600 Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/ex_me.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/forwarding.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/forwarding.sdb new file mode 100644 index 0000000..1ed0a82 Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/forwarding.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb new file mode 100644 index 0000000..7141f40 Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/glbl.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/hazard.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/hazard.sdb new file mode 100644 index 0000000..9c60435 Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/hazard.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/id_ex.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/id_ex.sdb new file mode 100644 index 0000000..f01e2c4 Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/id_ex.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/if_id.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/if_id.sdb new file mode 100644 index 0000000..835d2f8 Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/if_id.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/imem.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/imem.sdb new file mode 100644 index 0000000..d385a6c Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/imem.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/imm_gen.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/imm_gen.sdb new file mode 100644 index 0000000..505461a Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/imm_gen.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/me_wb.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/me_wb.sdb new file mode 100644 index 0000000..82e8b99 Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/me_wb.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pc.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pc.sdb new file mode 100644 index 0000000..694fb9a Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/pc.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/regfile.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/regfile.sdb new file mode 100644 index 0000000..bbb8c2f Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/regfile.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_top.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_top.sdb new file mode 100644 index 0000000..7ac098f Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/tb_top.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/top.sdb b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/top.sdb new file mode 100644 index 0000000..1cea5ad Binary files /dev/null and b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/top.sdb differ diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx new file mode 100644 index 0000000..c5d7a2b --- /dev/null +++ b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xil_defaultlib/xil_defaultlib.rlx @@ -0,0 +1,20 @@ +0.7 +2020.2 +Nov 14 2025 +12:36:23 +/home/jomaa/git/riscv-ac/riscv-ac.sim/sim_1/behav/xsim/glbl.v,1756381829,verilog,,,,glbl,,,,,,,, +/home/jomaa/git/riscv-ac/riscv-ac.srcs/sim_1/new/tb_top.v,1772486573,verilog,,,,tb_top,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, +/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/alu.v,1772483312,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/control.v,,alu,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, +/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/control.v,1772483371,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/dmem.v,,control,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, +/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/dmem.v,1772485582,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/ex_me.v,,dmem,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, +/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/ex_me.v,1772468735,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/forwarding.v,,ex_me,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, +/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/forwarding.v,1772467332,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/hazard.v,,forwarding,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, +/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/hazard.v,1772467244,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/id_ex.v,,hazard,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, +/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/id_ex.v,1772472446,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/if_id.v,,id_ex,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, +/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/if_id.v,1772468688,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imem.v,,if_id,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, +/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imem.v,1772485445,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imm_gen.v,,imem,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, +/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/imm_gen.v,1772470571,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/me_wb.v,,imm_gen,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, +/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/me_wb.v,1772468767,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/pc.v,,me_wb,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, +/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/pc.v,1772289140,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/regfile.v,,pc,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, +/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/regfile.v,1772483280,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/top.v,,regfile,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, +/home/jomaa/git/riscv-ac/riscv-ac.srcs/sources_1/new/top.v,1772486142,verilog,,/home/jomaa/git/riscv-ac/riscv-ac.srcs/sim_1/new/tb_top.v,,top,,,../../../../../../../../opt/Xilinx/2025.2/data/rsb/busdef,,,,, diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xsim.version b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xsim.version new file mode 100644 index 0000000..6327f31 --- /dev/null +++ b/riscv-ac.sim/sim_1/behav/xsim/xsim.dir/xsim.version @@ -0,0 +1 @@ +hjhoth \ No newline at end of file diff --git a/riscv-ac.sim/sim_1/behav/xsim/xsim.ini b/riscv-ac.sim/sim_1/behav/xsim/xsim.ini new file mode 100644 index 0000000..e8199b2 --- /dev/null +++ b/riscv-ac.sim/sim_1/behav/xsim/xsim.ini @@ -0,0 +1 @@ +xil_defaultlib=xsim.dir/xil_defaultlib diff --git a/riscv-ac.srcs/constrs_1/new/CmodA7_Master.xdc b/riscv-ac.srcs/constrs_1/new/CmodA7_Master.xdc new file mode 100644 index 0000000..1a936ad --- /dev/null +++ b/riscv-ac.srcs/constrs_1/new/CmodA7_Master.xdc @@ -0,0 +1,139 @@ +## This file is a general .xdc for the CmodA7 rev. B +## To use it in a project: +## - uncomment the lines corresponding to used pins +## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project + +# Clock signal 12 MHz +set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_14 Sch=gclk +create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports {clk}]; + + +## LEDs +set_property -dict { PACKAGE_PIN A17 IOSTANDARD LVCMOS33 } [get_ports { leds[0] }]; #IO_L12N_T1_MRCC_16 Sch=led[1] +set_property -dict { PACKAGE_PIN C16 IOSTANDARD LVCMOS33 } [get_ports { leds[1] }]; #IO_L13P_T2_MRCC_16 Sch=led[2] + +#set_property -dict { PACKAGE_PIN B17 IOSTANDARD LVCMOS33 } [get_ports { led_b}]; #IO_L14N_T2_SRCC_16 Sch=led0_b +#set_property -dict { PACKAGE_PIN B16 IOSTANDARD LVCMOS33 } [get_ports { led_g }]; #IO_L13N_T2_MRCC_16 Sch=led0_g +#set_property -dict { PACKAGE_PIN C17 IOSTANDARD LVCMOS33 } [get_ports { led }]; #IO_L14P_T2_SRCC_16 Sch=led0_r + + +# Buttons +set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { rst }]; #IO_L19N_T3_VREF_16 Sch=btn[0] +#set_property -dict { PACKAGE_PIN B18 IOSTANDARD LVCMOS33 } [get_ports { btn[1] }]; #IO_L19P_T3_16 Sch=btn[1] + + +## Pmod Header JA +#set_property -dict { PACKAGE_PIN G17 IOSTANDARD LVCMOS33 } [get_ports { ja[0] }]; #IO_L5N_T0_D07_14 Sch=ja[1] +#set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { ja[1] }]; #IO_L4N_T0_D05_14 Sch=ja[2] +#set_property -dict { PACKAGE_PIN N18 IOSTANDARD LVCMOS33 } [get_ports { ja[2] }]; #IO_L9P_T1_DQS_14 Sch=ja[3] +#set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { ja[3] }]; #IO_L8P_T1_D11_14 Sch=ja[4] +#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { ja[4] }]; #IO_L5P_T0_D06_14 Sch=ja[7] +#set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 } [get_ports { ja[5] }]; #IO_L4P_T0_D04_14 Sch=ja[8] +#set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports { ja[6] }]; #IO_L6N_T0_D08_VREF_14 Sch=ja[9] +#set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { ja[7] }]; #IO_L8N_T1_D12_14 Sch=ja[10] + + +# Analog XADC Pins +# Only declare these if you want to use pins 15 and 16 as single ended analog inputs. pin 15 -> vaux4, pin16 -> vaux12 +#set_property -dict { PACKAGE_PIN G2 IOSTANDARD LVCMOS33 } [get_ports { xa_n[0] }]; #IO_L1N_T0_AD4N_35 Sch=ain_n[15] +#set_property -dict { PACKAGE_PIN G3 IOSTANDARD LVCMOS33 } [get_ports { xa_p[0] }]; #IO_L1P_T0_AD4P_35 Sch=ain_p[15] +#set_property -dict { PACKAGE_PIN J2 IOSTANDARD LVCMOS33 } [get_ports { xa_n[1] }]; #IO_L2N_T0_AD12N_35 Sch=ain_n[16] +#set_property -dict { PACKAGE_PIN H2 IOSTANDARD LVCMOS33 } [get_ports { xa_p[1] }]; #IO_L2P_T0_AD12P_35 Sch=ain_p[16] + + +## GPIO Pins +## Pins 15 and 16 should remain commented if using them as analog inputs +set_property -dict { PACKAGE_PIN M3 IOSTANDARD LVCMOS33 } [get_ports { debug[0] }]; #IO_L8N_T1_AD14N_35 Sch=pio[01] +set_property -dict { PACKAGE_PIN L3 IOSTANDARD LVCMOS33 } [get_ports { debug[1] }]; #IO_L8P_T1_AD14P_35 Sch=pio[02] +set_property -dict { PACKAGE_PIN A16 IOSTANDARD LVCMOS33 } [get_ports { debug[2] }]; #IO_L12P_T1_MRCC_16 Sch=pio[03] +set_property -dict { PACKAGE_PIN K3 IOSTANDARD LVCMOS33 } [get_ports { debug[3] }]; #IO_L7N_T1_AD6N_35 Sch=pio[04] +set_property -dict { PACKAGE_PIN C15 IOSTANDARD LVCMOS33 } [get_ports { debug[4] }]; #IO_L11P_T1_SRCC_16 Sch=pio[05] +set_property -dict { PACKAGE_PIN H1 IOSTANDARD LVCMOS33 } [get_ports { debug[5] }]; #IO_L3P_T0_DQS_AD5P_35 Sch=pio[06] +set_property -dict { PACKAGE_PIN A15 IOSTANDARD LVCMOS33 } [get_ports { debug[6] }]; #IO_L6N_T0_VREF_16 Sch=pio[07] +set_property -dict { PACKAGE_PIN B15 IOSTANDARD LVCMOS33 } [get_ports { debug[7] }]; #IO_L11N_T1_SRCC_16 Sch=pio[08] +set_property -dict { PACKAGE_PIN A14 IOSTANDARD LVCMOS33 } [get_ports { debug[8] }]; #IO_L6P_T0_16 Sch=pio[09] +set_property -dict { PACKAGE_PIN J3 IOSTANDARD LVCMOS33 } [get_ports { debug[9] }]; #IO_L7P_T1_AD6P_35 Sch=pio[10] +set_property -dict { PACKAGE_PIN J1 IOSTANDARD LVCMOS33 } [get_ports { debug[10] }]; #IO_L3N_T0_DQS_AD5N_35 Sch=pio[11] +set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { debug[11] }]; #IO_L5P_T0_AD13P_35 Sch=pio[12] +set_property -dict { PACKAGE_PIN L1 IOSTANDARD LVCMOS33 } [get_ports { debug[12] }]; #IO_L6N_T0_VREF_35 Sch=pio[13] +set_property -dict { PACKAGE_PIN L2 IOSTANDARD LVCMOS33 } [get_ports { debug[13] }]; #IO_L5N_T0_AD13N_35 Sch=pio[14] +set_property -dict { PACKAGE_PIN M1 IOSTANDARD LVCMOS33 } [get_ports { debug[14] }]; #IO_L9N_T1_DQS_AD7N_35 Sch=pio[17] +set_property -dict { PACKAGE_PIN N3 IOSTANDARD LVCMOS33 } [get_ports { debug[15] }]; #IO_L12P_T1_MRCC_35 Sch=pio[18] +set_property -dict { PACKAGE_PIN P3 IOSTANDARD LVCMOS33 } [get_ports { debug[16] }]; #IO_L12N_T1_MRCC_35 Sch=pio[19] +set_property -dict { PACKAGE_PIN M2 IOSTANDARD LVCMOS33 } [get_ports { debug[17] }]; #IO_L9P_T1_DQS_AD7P_35 Sch=pio[20] +set_property -dict { PACKAGE_PIN N1 IOSTANDARD LVCMOS33 } [get_ports { debug[18] }]; #IO_L10N_T1_AD15N_35 Sch=pio[21] +set_property -dict { PACKAGE_PIN N2 IOSTANDARD LVCMOS33 } [get_ports { debug[19] }]; #IO_L10P_T1_AD15P_35 Sch=pio[22] +set_property -dict { PACKAGE_PIN P1 IOSTANDARD LVCMOS33 } [get_ports { debug[20] }]; #IO_L19N_T3_VREF_35 Sch=pio[23] +set_property -dict { PACKAGE_PIN R3 IOSTANDARD LVCMOS33 } [get_ports { debug[21] }]; #IO_L2P_T0_34 Sch=pio[26] +set_property -dict { PACKAGE_PIN T3 IOSTANDARD LVCMOS33 } [get_ports { debug[22] }]; #IO_L2N_T0_34 Sch=pio[27] +set_property -dict { PACKAGE_PIN R2 IOSTANDARD LVCMOS33 } [get_ports { debug[23] }]; #IO_L1P_T0_34 Sch=pio[28] +set_property -dict { PACKAGE_PIN T1 IOSTANDARD LVCMOS33 } [get_ports { debug[24] }]; #IO_L3P_T0_DQS_34 Sch=pio[29] +set_property -dict { PACKAGE_PIN T2 IOSTANDARD LVCMOS33 } [get_ports { debug[25] }]; #IO_L1N_T0_34 Sch=pio[30] +set_property -dict { PACKAGE_PIN U1 IOSTANDARD LVCMOS33 } [get_ports { debug[26] }]; #IO_L3N_T0_DQS_34 Sch=pio[31] +set_property -dict { PACKAGE_PIN W2 IOSTANDARD LVCMOS33 } [get_ports { debug[27] }]; #IO_L5N_T0_34 Sch=pio[32] +set_property -dict { PACKAGE_PIN V2 IOSTANDARD LVCMOS33 } [get_ports { debug[28] }]; #IO_L5P_T0_34 Sch=pio[33] +set_property -dict { PACKAGE_PIN W3 IOSTANDARD LVCMOS33 } [get_ports { debug[29] }]; #IO_L6N_T0_VREF_34 Sch=pio[34] +set_property -dict { PACKAGE_PIN V3 IOSTANDARD LVCMOS33 } [get_ports { debug[30] }]; #IO_L6P_T0_34 Sch=pio[35] +set_property -dict { PACKAGE_PIN W5 IOSTANDARD LVCMOS33 } [get_ports { debug[31] }]; #IO_L12P_T1_MRCC_34 Sch=pio[36] +#set_property -dict { PACKAGE_PIN V4 IOSTANDARD LVCMOS33 } [get_ports { pio[37] }]; #IO_L11N_T1_SRCC_34 Sch=pio[37] +#set_property -dict { PACKAGE_PIN U4 IOSTANDARD LVCMOS33 } [get_ports { pio[38] }]; #IO_L11P_T1_SRCC_34 Sch=pio[38] +#set_property -dict { PACKAGE_PIN V5 IOSTANDARD LVCMOS33 } [get_ports { pio[39] }]; #IO_L16N_T2_34 Sch=pio[39] +#set_property -dict { PACKAGE_PIN W4 IOSTANDARD LVCMOS33 } [get_ports { pio[40] }]; #IO_L12N_T1_MRCC_34 Sch=pio[40] +#set_property -dict { PACKAGE_PIN U5 IOSTANDARD LVCMOS33 } [get_ports { pio[41] }]; #IO_L16P_T2_34 Sch=pio[41] +#set_property -dict { PACKAGE_PIN U2 IOSTANDARD LVCMOS33 } [get_ports { pio[42] }]; #IO_L9N_T1_DQS_34 Sch=pio[42] +#set_property -dict { PACKAGE_PIN W6 IOSTANDARD LVCMOS33 } [get_ports { pio[43] }]; #IO_L13N_T2_MRCC_34 Sch=pio[43] +#set_property -dict { PACKAGE_PIN U3 IOSTANDARD LVCMOS33 } [get_ports { pio[44] }]; #IO_L9P_T1_DQS_34 Sch=pio[44] +#set_property -dict { PACKAGE_PIN U7 IOSTANDARD LVCMOS33 } [get_ports { pio[45] }]; #IO_L19P_T3_34 Sch=pio[45] +#set_property -dict { PACKAGE_PIN W7 IOSTANDARD LVCMOS33 } [get_ports { pio[46] }]; #IO_L13P_T2_MRCC_34 Sch=pio[46] +#set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS33 } [get_ports { pio[47] }]; #IO_L14P_T2_SRCC_34 Sch=pio[47] +#set_property -dict { PACKAGE_PIN V8 IOSTANDARD LVCMOS33 } [get_ports { pio[48] }]; #IO_L14N_T2_SRCC_34 Sch=pio[48] + + +## UART +#set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { uart_rxd_out }]; #IO_L7N_T1_D10_14 Sch=uart_rxd_out +#set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { uart_txd_in }]; #IO_L7P_T1_D09_14 Sch=uart_txd_in + + +## Crypto 1 Wire Interface +#set_property -dict { PACKAGE_PIN D17 IOSTANDARD LVCMOS33 } [get_ports { crypto_sda }]; #IO_0_14 Sch=crypto_sda + + +## QSPI +#set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { qspi_cs }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_cs +#set_property -dict { PACKAGE_PIN D18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[0] }]; #IO_L1P_T0_D00_MOSI_14 Sch=qspi_dq[0] +#set_property -dict { PACKAGE_PIN D19 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] +#set_property -dict { PACKAGE_PIN G18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] +#set_property -dict { PACKAGE_PIN F18 IOSTANDARD LVCMOS33 } [get_ports { qspi_dq[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] + + +## Cellular RAM +#set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[0] }]; #IO_L11P_T1_SRCC_14 Sch=sram- a[0] +#set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[1] }]; #IO_L11N_T1_SRCC_14 Sch=sram- a[1] +#set_property -dict { PACKAGE_PIN K17 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[2] }]; #IO_L12N_T1_MRCC_14 Sch=sram- a[2] +#set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[3] }]; #IO_L13P_T2_MRCC_14 Sch=sram- a[3] +#set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[4] }]; #IO_L13N_T2_MRCC_14 Sch=sram- a[4] +#set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[5] }]; #IO_L14P_T2_SRCC_14 Sch=sram- a[5] +#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[6] }]; #IO_L14N_T2_SRCC_14 Sch=sram- a[6] +#set_property -dict { PACKAGE_PIN W19 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[7] }]; #IO_L16N_T2_A15_D31_14 Sch=sram- a[7] +#set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[8] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sram- a[8] +#set_property -dict { PACKAGE_PIN V19 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[9] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=sram- a[9] +#set_property -dict { PACKAGE_PIN W18 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[10] }]; #IO_L16P_T2_CSI_B_14 Sch=sram- a[10] +#set_property -dict { PACKAGE_PIN T17 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[11] }]; #IO_L17P_T2_A14_D30_14 Sch=sram- a[11] +#set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[12] }]; #IO_L17N_T2_A13_D29_14 Sch=sram- a[12] +#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[13] }]; #IO_L18P_T2_A12_D28_14 Sch=sram- a[13] +#set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[14] }]; #IO_L18N_T2_A11_D27_14 Sch=sram- a[14] +#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[15] }]; #IO_L19P_T3_A10_D26_14 Sch=sram- a[15] +#set_property -dict { PACKAGE_PIN W16 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[16] }]; #IO_L20P_T3_A08_D24_14 Sch=sram- a[16] +#set_property -dict { PACKAGE_PIN W17 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[17] }]; #IO_L20N_T3_A07_D23_14 Sch=sram- a[17] +#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { MemAdr[18] }]; #IO_L21P_T3_DQS_14 Sch=sram- a[18] +#set_property -dict { PACKAGE_PIN W15 IOSTANDARD LVCMOS33 } [get_ports { MemDB[0] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=sram-dq[0] +#set_property -dict { PACKAGE_PIN W13 IOSTANDARD LVCMOS33 } [get_ports { MemDB[1] }]; #IO_L22P_T3_A05_D21_14 Sch=sram-dq[1] +#set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { MemDB[2] }]; #IO_L22N_T3_A04_D20_14 Sch=sram-dq[2] +#set_property -dict { PACKAGE_PIN U15 IOSTANDARD LVCMOS33 } [get_ports { MemDB[3] }]; #IO_L23P_T3_A03_D19_14 Sch=sram-dq[3] +#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { MemDB[4] }]; #IO_L23N_T3_A02_D18_14 Sch=sram-dq[4] +#set_property -dict { PACKAGE_PIN V13 IOSTANDARD LVCMOS33 } [get_ports { MemDB[5] }]; #IO_L24P_T3_A01_D17_14 Sch=sram-dq[5] +#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { MemDB[6] }]; #IO_L24N_T3_A00_D16_14 Sch=sram-dq[6] +#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { MemDB[7] }]; #IO_25_14 Sch=sram-dq[7] +#set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports { RamOEn }]; #IO_L10P_T1_D14_14 Sch=sram-oe +#set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports { RamWEn }]; #IO_L10N_T1_D15_14 Sch=sram-we +#set_property -dict { PACKAGE_PIN N19 IOSTANDARD LVCMOS33 } [get_ports { RamCEn }]; #IO_L9N_T1_DQS_D13_14 Sch=sram-ce \ No newline at end of file diff --git a/riscv-ac.srcs/sim_1/new/program.mem b/riscv-ac.srcs/sim_1/new/program.mem new file mode 100644 index 0000000..3571c71 --- /dev/null +++ b/riscv-ac.srcs/sim_1/new/program.mem @@ -0,0 +1,3 @@ +000000B3 +00810113 +002080B3 \ No newline at end of file diff --git a/riscv-ac.srcs/sim_1/new/tb_top.v b/riscv-ac.srcs/sim_1/new/tb_top.v new file mode 100644 index 0000000..6b4c1d2 --- /dev/null +++ b/riscv-ac.srcs/sim_1/new/tb_top.v @@ -0,0 +1,58 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 03/01/2026 07:26:34 PM +// Design Name: +// Module Name: tb_top +// Project Name: +// Target Devices: +// Tool Versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +`timescale 1ns / 1ps + +module tb_top(); + reg clk; + reg rst; + wire [1:0] leds; + wire [31:0] debug; + + top uut ( + .clk(clk), + .rst(rst), + .leds(leds), + .debug(debug) + ); + + // T_CLK = 10ns + always #5 clk = ~clk; + + initial begin + // inicializamos señales + clk = 0; + rst = 1; + + // cargamos programa + $readmemh("/home/jomaa/git/riscv-ac/riscv-ac.srcs/sim_1/new/program.mem", uut.u_imem.memory); + + // activamos reset 20ns + #20; + rst = 0; + + // ejecución de 100 ciclos + #150; + + $finish; + end +endmodule \ No newline at end of file diff --git a/riscv-ac.srcs/sources_1/new/alu.v b/riscv-ac.srcs/sources_1/new/alu.v index 9f1f57a..a7257b0 100644 --- a/riscv-ac.srcs/sources_1/new/alu.v +++ b/riscv-ac.srcs/sources_1/new/alu.v @@ -1,19 +1,19 @@ `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: +// Company: nope +// Engineer: Jose // // Create Date: 02/20/2026 09:21:52 AM -// Design Name: +// Design Name: Arithmetic-Logic Unit // Module Name: alu -// Project Name: -// Target Devices: -// Tool Versions: -// Description: +// Project Name: riscv-ac +// Target Devices: Artix 7 +// Tool Versions: 2025.2 +// Description: Main functional unit of the EX stage // // Dependencies: // -// Revision: +// Revision: 1.0 // Revision 0.01 - File Created // Additional Comments: // @@ -29,18 +29,18 @@ module alu( always @(*) begin case(sel) - 4'b0000: R <= A + B; // add - 4'b0001: R <= A - B; // sub - 4'b0010: R <= A & B; // and - 4'b0011: R <= A | B; // or - 4'b0100: R <= A ^ B; // xor - 4'b0101: R <= A << B[4:0]; // sll (shamt = 5 bits) - 4'b0110: R <= A >> B[4:0]; // srl (logical) - 4'b0111: R <= ($signed(A) < $signed(B)) ? 1 : 0; // slt signed - 4'b1000: R <= (A < B) ? 1 : 0; // sltu unsigned - 4'b1001: R <= $signed(A) >>> B[4:0]; // sra arithmetic right - 4'b1010: R <= 32'b0; // default / nop opcional - default: R <= 32'b0; + 4'b0000: R = A + B; // add + 4'b0001: R = A - B; // sub + 4'b0010: R = A & B; // and + 4'b0011: R = A | B; // or + 4'b0100: R = A ^ B; // xor + 4'b0101: R = A << B[4:0]; // sll + 4'b0110: R = A >> B[4:0]; // srl + 4'b0111: R = ($signed(A) < $signed(B)) ? 1 : 0; // slt (shift if less than signed) + 4'b1000: R = (A < B) ? 1 : 0; // sltu (shift if less than unsigned) + 4'b1001: R = $signed(A) >>> B[4:0]; // sra (shift right arithmetic) + 4'b1010: R = 32'b0; // nop + default: R = 32'b0; // default: nop endcase end diff --git a/riscv-ac.srcs/sources_1/new/control.v b/riscv-ac.srcs/sources_1/new/control.v index 16d7ec6..cfacd76 100644 --- a/riscv-ac.srcs/sources_1/new/control.v +++ b/riscv-ac.srcs/sources_1/new/control.v @@ -1,19 +1,19 @@ `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: +// Company: nope +// Engineer: Jose // // Create Date: 02/20/2026 09:21:52 AM -// Design Name: +// Design Name: Control Unit // Module Name: control -// Project Name: -// Target Devices: -// Tool Versions: -// Description: +// Project Name: riscv-ac +// Target Devices: Artix 7 +// Tool Versions: 2025.2 +// Description: Manages the logic in the ID stage // // Dependencies: // -// Revision: +// Revision: 1.0 // Revision 0.01 - File Created // Additional Comments: // @@ -22,22 +22,25 @@ module control( input [6:0] opcode, - input [2:0] funct3, - input [6:0] funct7, + input [2:0] aux, + input [6:0] func, output reg we_reg, output reg we_mem, output reg mem_to_reg, output reg alu_src, output reg [3:0] alu_op, - output reg branch + output reg branch, + output reg jump ); -localparam OP_R = 7'b0110011; -localparam OP_I = 7'b0010011; -localparam OP_LOAD= 7'b0000011; -localparam OP_STORE=7'b0100011; -localparam OP_BRANCH=7'b1100011; -localparam OP_JAL = 7'b1101111; +// formatos de instrucciones +localparam ALU_R = 7'b0110011; +localparam ALU_I = 7'b0010011; +localparam OP_LOAD = 7'b0000011; +localparam OP_STORE = 7'b0100011; +localparam OP_BRANCH = 7'b1100011; +localparam OP_JAL = 7'b1101111; +localparam OP_JALR = 7'b1100111; always @(*) begin we_reg = 0; @@ -46,12 +49,13 @@ always @(*) begin alu_src = 0; alu_op = 4'b0000; branch = 0; + jump = 0; case(opcode) - OP_R: begin + ALU_R: begin we_reg = 1; alu_src = 0; - case({funct7,funct3}) + case({func,aux}) 10'b0000000000: alu_op = 4'b0000; // ADD 10'b0100000000: alu_op = 4'b0001; // SUB 10'b0000000111: alu_op = 4'b0010; // AND @@ -65,16 +69,16 @@ always @(*) begin endcase end - OP_I: begin + ALU_I: begin we_reg = 1; alu_src = 1; - case(funct3) + case(aux) 3'b000: alu_op = 4'b0000; // ADDI 3'b111: alu_op = 4'b0010; // ANDI 3'b110: alu_op = 4'b0011; // ORI 3'b100: alu_op = 4'b0100; // XORI 3'b001: alu_op = 4'b0101; // SLLI - 3'b101: alu_op = (funct7==7'b0000000)?4'b0110:4'b0111; // SRLI/SRAI + 3'b101: alu_op = (func==7'b0000000)?4'b0110:4'b1001; // SRLI/SRAI 3'b010: alu_op = 4'b1000; // SLTI 3'b011: alu_op = 4'b1001; // SLTIU endcase @@ -82,32 +86,32 @@ always @(*) begin OP_LOAD: begin we_reg = 1; - we_mem = 0; mem_to_reg = 1; - alu_src = 1; // addr = rs1 + immediate - alu_op = 4'b0000; + alu_src = 1; end OP_STORE: begin we_mem = 1; - alu_src = 1; // addr = rs1 + immediate - alu_op = 4'b0000; + alu_src = 1; end OP_BRANCH: begin branch = 1; - alu_src = 0; alu_op = 4'b0001; end OP_JAL: begin - we_reg = 1; // rd <- PC+4 + we_reg = 1; // para guardar la dirección de retorno + jump = 1; + end + + OP_JALR: begin + we_reg = 1; alu_src = 1; - alu_op = 4'b0000; + jump = 1; end default: begin end - endcase end diff --git a/riscv-ac.srcs/sources_1/new/dmem.v b/riscv-ac.srcs/sources_1/new/dmem.v index 6371fe0..06ae330 100644 --- a/riscv-ac.srcs/sources_1/new/dmem.v +++ b/riscv-ac.srcs/sources_1/new/dmem.v @@ -1,19 +1,19 @@ `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: +// Company: nope +// Engineer: Jose // // Create Date: 02/20/2026 09:21:52 AM -// Design Name: +// Design Name: Data Memory // Module Name: dmem -// Project Name: -// Target Devices: -// Tool Versions: -// Description: +// Project Name: riscv-ac +// Target Devices: Artix 7 +// Tool Versions: 2025.2 +// Description: Stores data // // Dependencies: // -// Revision: +// Revision: 1.0 // Revision 0.01 - File Created // Additional Comments: // @@ -29,12 +29,21 @@ module dmem( ); reg [31:0] memory[0:255]; +reg [31:0] data; + +integer i; +initial begin + for (i = 0; i < 256; i = i + 1) begin + memory[i] = 32'b0; + end +end always @(posedge clk) begin if (we) memory[address[9:2]] <= write_data; + data <= memory[address[9:2]]; end -assign read_data = memory[address[9:2]]; +assign read_data = data; endmodule \ No newline at end of file diff --git a/riscv-ac.srcs/sources_1/new/ex_me.v b/riscv-ac.srcs/sources_1/new/ex_me.v new file mode 100644 index 0000000..71f4743 --- /dev/null +++ b/riscv-ac.srcs/sources_1/new/ex_me.v @@ -0,0 +1,42 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: nope +// Engineer: Jose +// +// Create Date: 02/20/2026 09:21:52 AM +// Design Name: EX/ME register +// Module Name: ex_me +// Project Name: riscv-ac +// Target Devices: Artix 7 +// Tool Versions: 2025.2 +// Description: Register between EX/ME stages +// +// Dependencies: +// +// Revision: 1.0 +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module ex_me ( + input clk, rst, + input we_reg_in, we_mem_in, mem_to_reg_in, + output reg we_reg_out, we_mem_out, mem_to_reg_out, + input [31:0] alu_in, regB_in, pc4_in, + input [4:0] rd_in, + output reg [31:0] alu_out, regB_out, pc4_out, + output reg [4:0] rd_out +); + + always @(posedge clk or posedge rst) begin + if (rst) begin + we_reg_out <= 0; we_mem_out <= 0; mem_to_reg_out <= 0; + alu_out <= 0; regB_out <= 0; pc4_out <= 0; rd_out <= 0; + end else begin + we_reg_out <= we_reg_in; we_mem_out <= we_mem_in; mem_to_reg_out <= mem_to_reg_in; + alu_out <= alu_in; regB_out <= regB_in; pc4_out <= pc4_in; rd_out <= rd_in; + end + end +endmodule \ No newline at end of file diff --git a/riscv-ac.srcs/sources_1/new/forwarding.v b/riscv-ac.srcs/sources_1/new/forwarding.v new file mode 100644 index 0000000..6fce5b9 --- /dev/null +++ b/riscv-ac.srcs/sources_1/new/forwarding.v @@ -0,0 +1,69 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: nope +// Engineer: Jose +// +// Create Date: 02/20/2026 09:21:52 AM +// Design Name: Forwarding +// Module Name: forwarding +// Project Name: riscv-ac +// Target Devices: Artix 7 +// Tool Versions: 2025.2 +// Description: Manages forwarding MUXes selection inputs +// +// Dependencies: +// +// Revision: 1.0 +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module forwarding ( + input [4:0] ID_EX_Rs1, + input [4:0] ID_EX_Rs2, + input [4:0] IF_ID_Rs1, + input [4:0] IF_ID_Rs2, + input [4:0] EX_ME_Rd, + input EX_ME_RegWrite, + input [4:0] ME_WB_Rd, + input ME_WB_RegWrite, + output reg [1:0] EX_ForwardA, + output reg [1:0] EX_ForwardB, + output reg [1:0] ID_ForwardA, + output reg [1:0] ID_ForwardB +); + + always @(*) begin + EX_ForwardA = 2'b00; + EX_ForwardB = 2'b00; + ID_ForwardA = 2'b00; + ID_ForwardB = 2'b00; + + // Bypass A (EX) + if (EX_ME_RegWrite && (EX_ME_Rd != 0) && (EX_ME_Rd == ID_EX_Rs1)) + EX_ForwardA = 2'b10; + else if (ME_WB_RegWrite && (ME_WB_Rd != 0) && (ME_WB_Rd == ID_EX_Rs1)) + EX_ForwardA = 2'b01; + + // Bypass B (EX) + if (EX_ME_RegWrite && (EX_ME_Rd != 0) && (EX_ME_Rd == ID_EX_Rs2)) + EX_ForwardB = 2'b10; + else if (ME_WB_RegWrite && (ME_WB_Rd != 0) && (ME_WB_Rd == ID_EX_Rs2)) + EX_ForwardB = 2'b01; + + // Bypass A (ID) + if (EX_ME_RegWrite && (EX_ME_Rd != 0) && (EX_ME_Rd == IF_ID_Rs1)) + ID_ForwardA = 2'b10; + else if (ME_WB_RegWrite && (ME_WB_Rd != 0) && (ME_WB_Rd == IF_ID_Rs1)) + ID_ForwardA = 2'b01; + + // Bypass B (ID) + if (EX_ME_RegWrite && (EX_ME_Rd != 0) && (EX_ME_Rd == IF_ID_Rs2)) + ID_ForwardB = 2'b10; + else if (ME_WB_RegWrite && (ME_WB_Rd != 0) && (ME_WB_Rd == IF_ID_Rs2)) + ID_ForwardB = 2'b01; + end + +endmodule diff --git a/riscv-ac.srcs/sources_1/new/hazard.v b/riscv-ac.srcs/sources_1/new/hazard.v new file mode 100644 index 0000000..4d7ce2a --- /dev/null +++ b/riscv-ac.srcs/sources_1/new/hazard.v @@ -0,0 +1,62 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: nope +// Engineer: Jose +// +// Create Date: 02/20/2026 09:21:52 AM +// Design Name: Hazard Unit +// Module Name: hazard +// Project Name: riscv-ac +// Target Devices: Artix 7 +// Tool Versions: 2025.2 +// Description: Manages hazards between memory instructions and any other +// +// Dependencies: +// +// Revision: 1.0 +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module hazard ( + input [4:0] IF_ID_Rs1, + input [4:0] IF_ID_Rs2, + input [4:0] ID_EX_Rd, + input ID_EX_MemRead, + input Branch_Taken, + output reg PC_En, + output reg IF_ID_En, + output reg IF_ID_Clr, + output reg ID_EX_Clr +); + + always @(*) begin + PC_En = 1'b1; + IF_ID_En = 1'b1; + IF_ID_Clr = 1'b0; + ID_EX_Clr = 1'b0; + + // si: + // - se lee de memoria + // - el Rd no es x0 + // - el Rd es Rs1 o Rs2 + // entonces: + // bloqueamos para que el dato generado en ME lo pueda coger EX + if (ID_EX_MemRead && (ID_EX_Rd != 5'b0) && + ((ID_EX_Rd == IF_ID_Rs1) || (ID_EX_Rd == IF_ID_Rs2))) begin + PC_En = 1'b0; + IF_ID_En = 1'b0; + ID_EX_Clr = 1'b1; + end + // si: + // - salto tomado + // entonces: + // flush síncrono al reg IF/ID + else if (Branch_Taken) begin + IF_ID_Clr = 1'b1; + end + end + +endmodule \ No newline at end of file diff --git a/riscv-ac.srcs/sources_1/new/id_ex.v b/riscv-ac.srcs/sources_1/new/id_ex.v new file mode 100644 index 0000000..2d99b23 --- /dev/null +++ b/riscv-ac.srcs/sources_1/new/id_ex.v @@ -0,0 +1,57 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: nope +// Engineer: Jose +// +// Create Date: 02/20/2026 09:21:52 AM +// Design Name: ID/EX register +// Module Name: id_ex +// Project Name: riscv-ac +// Target Devices: Artix 7 +// Tool Versions: 2025.2 +// Description: Register between ID/EX stages +// +// Dependencies: +// +// Revision: 1.0 +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module id_ex ( + input clk, rst, clr, + + // señales de la UC y ALU + input we_reg_in, we_mem_in, mem_to_reg_in, alu_src_in, branch_in, jump_in, + input [3:0] alu_op_in, + + output reg we_reg_out, we_mem_out, mem_to_reg_out, alu_src_out, branch_out, jump_out, + output reg [3:0] alu_op_out, + + // PC4, A, B, C, Rd + input [31:0] pc4_in, regA_in, regB_in, regC_in, + input [4:0] rs1_in, rs2_in, rd_in, + + output reg [31:0] pc4_out, regA_out, regB_out, regC_out, + output reg [4:0] rs1_out, rs2_out, rd_out +); + + always @(posedge clk or posedge rst) begin + if (rst || clr) begin + we_reg_out <= 0; we_mem_out <= 0; mem_to_reg_out <= 0; + alu_src_out <= 0; branch_out <= 0; jump_out <= 0; alu_op_out <= 4'b0; + pc4_out <= 0; regA_out <= 0; regB_out <= 0; regC_out <= 0; + rs1_out <= 0; rs2_out <= 0; rd_out <= 0; + end + else begin + we_reg_out <= we_reg_in; we_mem_out <= we_mem_in; + mem_to_reg_out <= mem_to_reg_in; alu_src_out <= alu_src_in; + branch_out <= branch_in; jump_out <= jump_in; alu_op_out <= alu_op_in; + pc4_out <= pc4_in; + regA_out <= regA_in; regB_out <= regB_in; regC_out <= regC_in; + rs1_out <= rs1_in; rs2_out <= rs2_in; rd_out <= rd_in; + end + end +endmodule \ No newline at end of file diff --git a/riscv-ac.srcs/sources_1/new/if_id.v b/riscv-ac.srcs/sources_1/new/if_id.v new file mode 100644 index 0000000..a54ab48 --- /dev/null +++ b/riscv-ac.srcs/sources_1/new/if_id.v @@ -0,0 +1,51 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: nope +// Engineer: Jose +// +// Create Date: 02/20/2026 09:21:52 AM +// Design Name: IF/ID register +// Module Name: if_id +// Project Name: riscv-ac +// Target Devices: Artix 7 +// Tool Versions: 2025.2 +// Description: Register between IF/ID stages +// +// Dependencies: +// +// Revision: 1.0 +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module if_id ( + input clk, + input rst, + input en, + input clr, + input [31:0] npc_in, + input [31:0] pc4_in, + input [31:0] ir_in, + output reg [31:0] npc_out, + output reg [31:0] pc4_out, + output reg [31:0] ir_out +); + + always @(posedge clk or posedge rst) begin + if (rst) begin + npc_out <= 32'b0; + pc4_out <= 32'b0; + ir_out <= 32'b0; + end else if (clr) begin + npc_out <= 32'b0; + pc4_out <= 32'b0; + ir_out <= 32'b0; + end else if (en) begin + npc_out <= npc_in; + pc4_out <= pc4_in; + ir_out <= ir_in; + end + end +endmodule \ No newline at end of file diff --git a/riscv-ac.srcs/sources_1/new/imem.v b/riscv-ac.srcs/sources_1/new/imem.v index a524e3a..1fba927 100644 --- a/riscv-ac.srcs/sources_1/new/imem.v +++ b/riscv-ac.srcs/sources_1/new/imem.v @@ -1,19 +1,19 @@ `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: +// Company: nope +// Engineer: Jose // // Create Date: 02/20/2026 09:21:52 AM -// Design Name: +// Design Name: Instruction Memory // Module Name: imem -// Project Name: -// Target Devices: -// Tool Versions: -// Description: +// Project Name: riscv-ac +// Target Devices: Artix 7 +// Tool Versions: 2025.2 +// Description: Stores instructions // // Dependencies: // -// Revision: +// Revision: 1.0 // Revision 0.01 - File Created // Additional Comments: // @@ -29,12 +29,21 @@ module imem( ); reg [31:0] memory[0:255]; +reg [31:0] ir; + +integer i; +initial begin + for (i = 0; i < 256; i = i + 1) begin + memory[i] = 32'b0; + end +end always @(posedge clk) begin if(we) memory[write_addr] <= write_data; + ir <= memory[address[9:2]]; end -assign instruction = memory[address[9:2]]; +assign instruction = ir; endmodule diff --git a/riscv-ac.srcs/sources_1/new/imm_gen.v b/riscv-ac.srcs/sources_1/new/imm_gen.v index c136e35..2be97c0 100644 --- a/riscv-ac.srcs/sources_1/new/imm_gen.v +++ b/riscv-ac.srcs/sources_1/new/imm_gen.v @@ -1,37 +1,54 @@ `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: +// Company: nope +// Engineer: Jose // // Create Date: 02/20/2026 09:21:52 AM -// Design Name: +// Design Name: Immediate Generator // Module Name: imm_gen -// Project Name: -// Target Devices: -// Tool Versions: -// Description: +// Project Name: riscv-ac +// Target Devices: Artix 7 +// Tool Versions: 2025.2 +// Description: Retrieves the immediate from the instruction (uses verilog concat) // // Dependencies: // -// Revision: +// Revision: 1.0 // Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// - module imm_gen( - input [31:0] instr, + input [31:0] instr, output reg [31:0] imm_out ); always @(*) begin case(instr[6:0]) - 7'b0010011, - 7'b0000011: + // Formato I + 7'b0010011, + 7'b0000011, + 7'b1100111: imm_out = {{20{instr[31]}}, instr[31:20]}; + + // Formato S + 7'b0100011: + imm_out = {{20{instr[31]}}, instr[31:25], instr[11:7]}; + + // Formato B + 7'b1100011: + imm_out = {{19{instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0}; + + // Formato J 7'b1101111: imm_out = {{11{instr[31]}}, instr[31], instr[19:12], instr[20], instr[30:21], 1'b0}; + + // Formato U + 7'b0110111, + 7'b0010111: + imm_out = {instr[31:12], 12'b0}; + default: imm_out = 32'b0; endcase diff --git a/riscv-ac.srcs/sources_1/new/me_wb.v b/riscv-ac.srcs/sources_1/new/me_wb.v new file mode 100644 index 0000000..d272a1d --- /dev/null +++ b/riscv-ac.srcs/sources_1/new/me_wb.v @@ -0,0 +1,42 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: nope +// Engineer: Jose +// +// Create Date: 02/20/2026 09:21:52 AM +// Design Name: ME/WB register +// Module Name: me_wb +// Project Name: riscv-ac +// Target Devices: Artix 7 +// Tool Versions: 2025.2 +// Description: Register between ME/WB stages +// +// Dependencies: +// +// Revision: 1.0 +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + + +module me_wb ( + input clk, rst, + input we_reg_in, mem_to_reg_in, + output reg we_reg_out, mem_to_reg_out, + input [31:0] alu_in, mem_data_in, pc4_in, + input [4:0] rd_in, + output reg [31:0] alu_out, mem_data_out, pc4_out, + output reg [4:0] rd_out +); + + always @(posedge clk or posedge rst) begin + if (rst) begin + we_reg_out <= 0; mem_to_reg_out <= 0; + alu_out <= 0; mem_data_out <= 0; pc4_out <= 0; rd_out <= 0; + end else begin + we_reg_out <= we_reg_in; mem_to_reg_out <= mem_to_reg_in; + alu_out <= alu_in; mem_data_out <= mem_data_in; pc4_out <= pc4_in; rd_out <= rd_in; + end + end +endmodule \ No newline at end of file diff --git a/riscv-ac.srcs/sources_1/new/pc.v b/riscv-ac.srcs/sources_1/new/pc.v index 4a61970..c42e336 100644 --- a/riscv-ac.srcs/sources_1/new/pc.v +++ b/riscv-ac.srcs/sources_1/new/pc.v @@ -1,19 +1,19 @@ `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: +// Company: nope +// Engineer: Jose // // Create Date: 02/20/2026 09:21:52 AM -// Design Name: +// Design Name: Program Counter // Module Name: pc -// Project Name: -// Target Devices: -// Tool Versions: -// Description: +// Project Name: riscv-ac +// Target Devices: Artix 7 +// Tool Versions: 2025.2 +// Description: Points to the next instruction // // Dependencies: // -// Revision: +// Revision: 1.0 // Revision 0.01 - File Created // Additional Comments: // diff --git a/riscv-ac.srcs/sources_1/new/regfile.v b/riscv-ac.srcs/sources_1/new/regfile.v index 09ad50d..590e8c4 100644 --- a/riscv-ac.srcs/sources_1/new/regfile.v +++ b/riscv-ac.srcs/sources_1/new/regfile.v @@ -1,19 +1,19 @@ `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: +// Company: nope +// Engineer: Jose // // Create Date: 02/20/2026 09:21:52 AM -// Design Name: +// Design Name: Register File // Module Name: regfile -// Project Name: -// Target Devices: -// Tool Versions: -// Description: +// Project Name: riscv-ac +// Target Devices: Artix 7 +// Tool Versions: 2025.2 +// Description: Stores temporal values // // Dependencies: // -// Revision: +// Revision: 1.0 // Revision 0.01 - File Created // Additional Comments: // @@ -29,6 +29,13 @@ module regfile( reg [31:0] regs[0:31]; +integer i; +initial begin + for (i = 0; i < 32; i = i + 1) begin + regs[i] = 32'b0; + end +end + assign read_data_1 = (rs1 == 0) ? 0 : regs[rs1]; assign read_data_2 = (rs2 == 0) ? 0 : regs[rs2]; diff --git a/riscv-ac.srcs/sources_1/new/top.v b/riscv-ac.srcs/sources_1/new/top.v index e525507..fa8a752 100644 --- a/riscv-ac.srcs/sources_1/new/top.v +++ b/riscv-ac.srcs/sources_1/new/top.v @@ -1,135 +1,197 @@ `timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 02/20/2026 09:21:52 AM -// Design Name: -// Module Name: top -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// +`default_nettype none - -module top( - input clk, rst, - input [31:0] uart_data, - output [31:0] pc_out, alu_out, mem_data +module top ( + input clk, + input rst, + output [1:0] leds, + output [31:0] debug ); -// = PC =================================== -wire [31:0] pc_next, pc; -wire branch_taken; + // ========================================== + // ETAPA IF + // ========================================== + wire [31:0] npc_IF, pc4_IF, ir_IF, next_pc_IF, pc_stall; + wire PC_En, IF_ID_En, IF_ID_Clr; -pc pc_inst( - .clk(clk), - .rst(rst), - .next_pc(pc_next), - .imem_addr(pc_curr) -); + assign next_pc_IF = (Branch_Taken) ? branch_target_ID : pc4_IF; + assign pc4_IF = npc_IF + 4; + assign pc_stall = (PC_En) ? next_pc_IF : npc_IF; -assign pc_out = pc_curr; -// ======================================== + pc u_pc ( + .clk(clk), + .rst(rst), + .next_pc(pc_stall), + .imem_addr(npc_IF) + ); -// = IMEM ================================= -wire [31:0] instr; + imem u_imem ( + .clk(clk), .address(npc_IF), .we(1'b0), + .write_data(32'b0), .write_addr(8'b0), .instruction(ir_IF) + ); -imem imem_inst( - .address(pc_curr), - .instruction(instr) -); -// ======================================== + // ========================================== + // REGISTRO IF/ID + // ========================================== + wire [31:0] npc_ID, pc4_ID, ir_ID; -// = DECODE =============================== -wire [6:0] opcode = instr[6:0]; -wire [4:0] rd = instr[11:7]; -wire [2:0] funct3 = instr[14:12]; -wire [4:0] rs1 = instr[19:15]; -wire [4:0] rs2 = instr[24:20]; -wire [6:0] funct7 = instr[31:25]; -// ======================================== + if_id u_if_id ( + .clk(clk), .rst(rst), .en(IF_ID_En), .clr(IF_ID_Clr), + .npc_in(npc_IF), .pc4_in(pc4_IF), .ir_in(ir_IF), + .npc_out(npc_ID), .pc4_out(pc4_ID), .ir_out(ir_ID) + ); -// regfile mux -wire [31:0] reg_write_data; -assign reg_write_data = mem_to_reg ? dmem_read_data : alu_out; + // ========================================== + // ETAPA ID + // ========================================== + wire [4:0] rs1_ID = ir_ID[19:15]; + wire [4:0] rs2_ID = ir_ID[24:20]; + wire [4:0] rd_ID = ir_ID[11:7]; + wire [31:0] imm_ID, regA_ID, regB_ID; + + // Señales de Control + wire we_reg_ID, we_mem_ID, mem_to_reg_ID, alu_src_ID, branch_ID, jump_ID; + wire [3:0] alu_op_ID; + wire Branch_Taken; + wire [31:0] branch_target_ID; -// = REGFILE =============================== -wire [31:0] reg_r1, reg_r2; -wire we_reg; + control u_control ( + .opcode(ir_ID[6:0]), .aux(ir_ID[14:12]), .func(ir_ID[31:25]), + .we_reg(we_reg_ID), .we_mem(we_mem_ID), .mem_to_reg(mem_to_reg_ID), + .alu_src(alu_src_ID), .alu_op(alu_op_ID), .branch(branch_ID), .jump(jump_ID) + ); + + wire [31:0] write_data_WB; -regfile regfile_inst( - .clk(clk), - .regwrite(we_reg), - .rs1(rs1), - .rs2(rs2), - .rd(rd), - .write_data(reg_write_data), - .read_data_1(reg_r1), - .read_data_2(reg_r2) -); -// ======================================== + regfile u_regfile ( + .clk(~clk), + .regwrite(we_reg_WB), .rs1(rs1_ID), .rs2(rs2_ID), .rd(rd_WB), + .write_data(write_data_WB), .read_data_1(regA_ID), .read_data_2(regB_ID) + ); -// = IMMGEN =============================== -wire [31:0] imm_out; + imm_gen u_imm_gen ( + .instr(ir_ID), .imm_out(imm_ID) + ); -imm_gen imm_gen_inst( - .instr(instr), - .imm_out(imm_out) -); -// ======================================== + wire [1:0] ID_ForwardA, ID_ForwardB; + wire [31:0] cmp_A = (ID_ForwardA == 2'b10) ? alu_res_ME : (ID_ForwardA == 2'b01) ? write_data_WB : regA_ID; + wire [31:0] cmp_B = (ID_ForwardB == 2'b10) ? alu_res_ME : (ID_ForwardB == 2'b01) ? write_data_WB : regB_ID; + + // salto si JAL/JALR o si condición de BRANCH ok + assign Branch_Taken = jump_ID | (branch_ID & (cmp_A == cmp_B)); + + // MUX DirSalto + wire is_jalr = (ir_ID[6:0] == 7'b1100111); + wire [31:0] base_salto = is_jalr ? cmp_A : npc_ID; + + assign branch_target_ID = (base_salto + imm_ID) & ~32'b1; -// = CONTROL =============================== -wire we_mem, mem_to_reg, alu_src; -wire [3:0] alu_op; + // detector de riesgos + wire ID_EX_Clr; + hazard u_hazard ( + .IF_ID_Rs1(rs1_ID), .IF_ID_Rs2(rs2_ID), + .ID_EX_Rd(rd_EX), .ID_EX_MemRead(mem_to_reg_EX), + .Branch_Taken(Branch_Taken), + .PC_En(PC_En), .IF_ID_En(IF_ID_En), .IF_ID_Clr(IF_ID_Clr), .ID_EX_Clr(ID_EX_Clr) + ); -control control_inst( - .opcode(opcode), - .funct3(funct3), - .funct7(funct7), - .we_reg(we_reg), - .we_mem(we_mem), - .mem_to_reg(mem_to_reg), - .alu_src(alu_src), - .alu_op(alu_op), - .branch(branch_taken) -); -// ======================================== + // ========================================== + // REGISTRO ID/EX + // ========================================== + wire [31:0] pc_EX, pc4_EX, regA_EX, regB_EX, imm_EX; + wire [4:0] rs1_EX, rs2_EX, rd_EX; + wire we_reg_EX, we_mem_EX, mem_to_reg_EX, alu_src_EX, branch_EX, jump_EX; + wire [3:0] alu_op_EX; -// = ALU ================================== -wire [31:0] alu_b = alu_src ? imm_out : reg_r2; + id_ex u_id_ex ( + .clk(clk), .rst(rst), .clr(ID_EX_Clr), + .we_reg_in(we_reg_ID), .we_mem_in(we_mem_ID), .mem_to_reg_in(mem_to_reg_ID), + .alu_src_in(alu_src_ID), .branch_in(branch_ID), .alu_op_in(alu_op_ID), + .jump_in(jump_ID), + .we_reg_out(we_reg_EX), .we_mem_out(we_mem_EX), .mem_to_reg_out(mem_to_reg_EX), + .alu_src_out(alu_src_EX), .branch_out(branch_EX), .alu_op_out(alu_op_EX), + .jump_out(jump_EX), + .pc4_in(pc4_ID), .regA_in(regA_ID), .regB_in(regB_ID), .regC_in(imm_ID), + .rs1_in(rs1_ID), .rs2_in(rs2_ID), .rd_in(rd_ID), + .pc4_out(pc4_EX), .regA_out(regA_EX), .regB_out(regB_EX), .regC_out(imm_EX), + .rs1_out(rs1_EX), .rs2_out(rs2_EX), .rd_out(rd_EX) + ); -alu alu_inst( - .A(reg_r1), - .B(alu_b), - .sel(alu_op), - .R(alu_out) -); -// ======================================== + // ========================================== + // ETAPA EX + // ========================================== + wire [1:0] EX_ForwardA, EX_ForwardB; + wire [31:0] alu_A, alu_B_temp, alu_B, alu_res_EX_raw, alu_res_EX; + wire alu_zero_EX; + wire [31:0] alu_res_ME; -// = DMEM ================================= -wire [31:0] dmem_read_data; + forwarding u_forwarding ( + .ID_EX_Rs1(rs1_EX), .ID_EX_Rs2(rs2_EX), .IF_ID_Rs1(rs1_ID), .IF_ID_Rs2(rs2_ID), + .EX_ME_Rd(rd_ME), .EX_ME_RegWrite(we_reg_ME), .ME_WB_Rd(rd_WB), .ME_WB_RegWrite(we_reg_WB), + .EX_ForwardA(EX_ForwardA), .EX_ForwardB(EX_ForwardB), + .ID_ForwardA(ID_ForwardA), .ID_ForwardB(ID_ForwardB) + ); -dmem dmem_inst( - .clk(clk), - .we(we_mem), - .address(alu_out), - .write_data(reg_r2), - .read_data(dmem_read_data) -); + assign alu_A = (EX_ForwardA == 2'b10) ? alu_res_ME : (EX_ForwardA == 2'b01) ? write_data_WB : regA_EX; + assign alu_B_temp = (EX_ForwardB == 2'b10) ? alu_res_ME : (EX_ForwardB == 2'b01) ? write_data_WB : regB_EX; + assign alu_B = (alu_src_EX) ? imm_EX : alu_B_temp; -assign mem_data = dmem_read_data; -// ======================================== + alu u_alu ( + .A(alu_A), .B(alu_B), .sel(alu_op_EX), .R(alu_res_EX_raw), .zero(alu_zero_EX) + ); -// PC increment -assign pc_next = branch_taken ? (pc_curr + imm_out) : (pc_curr + 4); + // MUX post-ALU para guardar PC+4 si es un salto (JAL/JALR) + assign alu_res_EX = jump_EX ? pc4_EX : alu_res_EX_raw; -endmodule + // ========================================== + // REGISTRO EX/ME + // ========================================== + wire [31:0] regB_ME, pc4_ME; + wire [4:0] rd_ME; + wire we_reg_ME, we_mem_ME, mem_to_reg_ME; + + ex_me u_ex_me ( + .clk(clk), .rst(rst), + .we_reg_in(we_reg_EX), .we_mem_in(we_mem_EX), .mem_to_reg_in(mem_to_reg_EX), + .we_reg_out(we_reg_ME), .we_mem_out(we_mem_ME), .mem_to_reg_out(mem_to_reg_ME), + .alu_in(alu_res_EX), .regB_in(alu_B_temp), .pc4_in(pc4_EX), .rd_in(rd_EX), + .alu_out(alu_res_ME), .regB_out(regB_ME), .pc4_out(pc4_ME), .rd_out(rd_ME) + ); + + // ========================================== + // ETAPA ME & WB + // ========================================== + wire [31:0] mem_data_ME; + dmem u_dmem ( + .clk(clk), .we(we_mem_ME), .address(alu_res_ME), + .write_data(regB_ME), .read_data(mem_data_ME) + ); + + wire [31:0] alu_res_WB, mem_data_WB, pc4_WB; + wire [4:0] rd_WB; + wire we_reg_WB, mem_to_reg_WB; + + me_wb u_me_wb ( + .clk(clk), .rst(rst), + .we_reg_in(we_reg_ME), .mem_to_reg_in(mem_to_reg_ME), + .we_reg_out(we_reg_WB), .mem_to_reg_out(mem_to_reg_WB), + .alu_in(alu_res_ME), .mem_data_in(mem_data_ME), .pc4_in(pc4_ME), .rd_in(rd_ME), + .alu_out(alu_res_WB), .mem_data_out(mem_data_WB), .pc4_out(pc4_WB), .rd_out(rd_WB) + ); + + assign write_data_WB = (mem_to_reg_WB) ? mem_data_WB : alu_res_WB; + + // ========================================== + // DEBUG + // ========================================== + assign leds[0] = Branch_Taken; // se enciende cuando hay salto + assign leds[1] = ID_EX_Clr; // se enciende en bloqueos + + assign debug = { + alu_res_EX[15:0], + rd_WB, + rs1_ID, + npc_IF[7:2] + }; + +endmodule \ No newline at end of file diff --git a/riscv-ac.xpr b/riscv-ac.xpr index 7aa4913..0157eac 100644 --- a/riscv-ac.xpr +++ b/riscv-ac.xpr @@ -4,7 +4,7 @@ - +