prototype works

riscv-ac.srcs/sources_1/new/regfile.v

@@ -1,19 +1,19 @@
 `timescale 1ns / 1ps
 //////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
+// Company: nope
+// Engineer: Jose
 // 
 // Create Date: 02/20/2026 09:21:52 AM
-// Design Name: 
+// Design Name: Register File
 // Module Name: regfile
-// Project Name: 
-// Target Devices: 
-// Tool Versions: 
-// Description: 
+// Project Name: riscv-ac
+// Target Devices: Artix 7
+// Tool Versions: 2025.2
+// Description: Stores temporal values
 // 
 // Dependencies: 
 // 
-// Revision:
+// Revision: 1.0
 // Revision 0.01 - File Created
 // Additional Comments:
 // 
@@ -29,6 +29,13 @@ module regfile(
 
 reg [31:0] regs[0:31];
 
+integer i;
+initial begin
+    for (i = 0; i < 32; i = i + 1) begin
+        regs[i] = 32'b0;
+    end
+end
+
 assign read_data_1 = (rs1 == 0) ? 0 : regs[rs1];
 assign read_data_2 = (rs2 == 0) ? 0 : regs[rs2];