prototype works

riscv-ac.srcs/sources_1/new/imm_gen.v

@@ -1,37 +1,54 @@
 `timescale 1ns / 1ps
 //////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
+// Company: nope
+// Engineer: Jose
 // 
 // Create Date: 02/20/2026 09:21:52 AM
-// Design Name: 
+// Design Name: Immediate Generator
 // Module Name: imm_gen
-// Project Name: 
-// Target Devices: 
-// Tool Versions: 
-// Description: 
+// Project Name: riscv-ac
+// Target Devices: Artix 7
+// Tool Versions: 2025.2
+// Description: Retrieves the immediate from the instruction (uses verilog concat)
 // 
 // Dependencies: 
 // 
-// Revision:
+// Revision: 1.0
 // Revision 0.01 - File Created
 // Additional Comments:
 // 
 //////////////////////////////////////////////////////////////////////////////////
 
-
 module imm_gen(
-    input [31:0] instr,
+    input  [31:0] instr,
     output reg [31:0] imm_out
 );
 
 always @(*) begin 
     case(instr[6:0]) 
-        7'b0010011,
-        7'b0000011:
+        // Formato I
+        7'b0010011, 
+        7'b0000011,
+        7'b1100111:
             imm_out = {{20{instr[31]}}, instr[31:20]};
+
+        // Formato S
+        7'b0100011:
+            imm_out = {{20{instr[31]}}, instr[31:25], instr[11:7]};
+
+        // Formato B
+        7'b1100011:
+            imm_out = {{19{instr[31]}}, instr[31], instr[7], instr[30:25], instr[11:8], 1'b0};
+
+        // Formato J
         7'b1101111:
             imm_out = {{11{instr[31]}}, instr[31], instr[19:12], instr[20], instr[30:21], 1'b0};
+
+        // Formato U
+        7'b0110111, 
+        7'b0010111:
+            imm_out = {instr[31:12], 12'b0};
+
         default:
             imm_out = 32'b0;
     endcase